[deliverable/binutils-gdb.git] / sim / or1k / sim-if.c

/* Main simulator entry points specific to the OR1K.
   Copyright (C) 2017-2021 Free Software Foundation, Inc.

   This file is part of GDB, the GNU debugger.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

/* This must come before any other includes.  */
#include "defs.h"

#include "sim-main.h"
#include "sim-options.h"
#include "libiberty.h"
#include "bfd.h"

#include <string.h>
#include <stdlib.h>

static void free_state (SIM_DESC);
\f

/* Cover function of sim_state_free to free the cpu buffers as well.  */

static void
free_state (SIM_DESC sd)
{
  if (STATE_MODULES (sd) != NULL)
    sim_module_uninstall (sd);
  sim_cpu_free_all (sd);
  sim_state_free (sd);
}

/* Defaults for user passed arguments.  */
static const USI or1k_default_vr = 0x0;
static const USI or1k_default_upr = 0x0
  | SPR_FIELD_MASK_SYS_UPR_UP;
static const USI or1k_default_cpucfgr = 0x0
  | SPR_FIELD_MASK_SYS_CPUCFGR_OB32S
  | SPR_FIELD_MASK_SYS_CPUCFGR_OF32S;

static UWI or1k_upr;
static UWI or1k_vr;
static UWI or1k_cpucfgr;

enum
{
  OPTION_OR1K_VR,
  OPTION_OR1K_UPR,
  OPTION_OR1K_CPUCFGR = OPTION_START,
};

/* Setup help and handlers for the user defined arguments.  */
DECLARE_OPTION_HANDLER (or1k_option_handler);

static const OPTION or1k_options[] = {
  {{"or1k-cpucfgr", required_argument, NULL, OPTION_OR1K_CPUCFGR},
   '\0', "INTEGER|default", "Set simulator CPUCFGR value",
   or1k_option_handler},
  {{"or1k-vr", required_argument, NULL, OPTION_OR1K_VR},
   '\0', "INTEGER|default", "Set simulator VR value",
   or1k_option_handler},
  {{"or1k-upr", required_argument, NULL, OPTION_OR1K_UPR},
   '\0', "INTEGER|default", "Set simulator UPR value",
   or1k_option_handler},
  {{NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL}
};

/* Handler for parsing user defined arguments.  Currently we support
   configuring some of the CPU implementation specific registers including
   the Version Register (VR), the Unit Present Register (UPR) and the CPU
   Configuration Register (CPUCFGR).  */
SIM_RC
or1k_option_handler (SIM_DESC sd, sim_cpu *cpu, int opt, char *arg,
		     int is_command)
{
  switch (opt)
    {
    case OPTION_OR1K_VR:
      if (strcmp ("default", arg) == 0)
	or1k_vr = or1k_default_vr;
      else
	{
	  unsigned long long n;
	  char *endptr;

	  n = strtoull (arg, &endptr, 0);
	  if (*arg != '\0' && *endptr == '\0')
	    or1k_vr = n;
	  else
	    return SIM_RC_FAIL;
	}
      return SIM_RC_OK;

    case OPTION_OR1K_UPR:
      if (strcmp ("default", arg) == 0)
	or1k_upr = or1k_default_upr;
      else
	{
	  unsigned long long n;
	  char *endptr;

	  n = strtoull (arg, &endptr, 0);
	  if (*arg != '\0' && *endptr == '\0')
	    or1k_upr = n;
	  else
	    {
	      sim_io_eprintf
		(sd, "invalid argument to option --or1k-upr: `%s'\n", arg);
	      return SIM_RC_FAIL;
	    }
	}
      return SIM_RC_OK;

    case OPTION_OR1K_CPUCFGR:
      if (strcmp ("default", arg) == 0)
	or1k_cpucfgr = or1k_default_cpucfgr;
      else
	{
	  unsigned long long n;
	  char *endptr;

	  n = strtoull (arg, &endptr, 0);
	  if (*arg != '\0' && *endptr == '\0')
	    or1k_cpucfgr = n;
	  else
	    {
	      sim_io_eprintf
		(sd, "invalid argument to option --or1k-cpucfgr: `%s'\n", arg);
	      return SIM_RC_FAIL;
	    }
	}
      return SIM_RC_OK;

    default:
      sim_io_eprintf (sd, "Unknown or1k option %d\n", opt);
      return SIM_RC_FAIL;
    }

  return SIM_RC_FAIL;
}

extern const SIM_MACH * const or1k_sim_machs[];

/* Create an instance of the simulator.  */

SIM_DESC
sim_open (SIM_OPEN_KIND kind, host_callback *callback, struct bfd *abfd,
	  char * const *argv)
{
  SIM_DESC sd = sim_state_alloc (kind, callback);
  char c;
  int i;

  /* Set default options before parsing user options.  */
  STATE_MACHS (sd) = or1k_sim_machs;
  current_target_byte_order = BFD_ENDIAN_BIG;

  /* The cpu data is kept in a separately allocated chunk of memory.  */
  if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)
    {
      free_state (sd);
      return 0;
    }

  /* Perform initial sim setups.  */
  if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
    {
      free_state (sd);
      return 0;
    }

  or1k_upr = or1k_default_upr;
  or1k_vr = or1k_default_vr;
  or1k_cpucfgr = or1k_default_cpucfgr;
  sim_add_option_table (sd, NULL, or1k_options);

  /* Parse the user passed arguments.  */
  if (sim_parse_args (sd, argv) != SIM_RC_OK)
    {
      free_state (sd);
      return 0;
    }

  /* Allocate core managed memory if none specified by user.
     Use address 4 here in case the user wanted address 0 unmapped.  */
  if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0)
    {
      sim_do_commandf (sd, "memory region 0,0x%x", OR1K_DEFAULT_MEM_SIZE);
    }

  /* Check for/establish the reference program image.  */
  if (sim_analyze_program (sd,
			   (STATE_PROG_ARGV (sd) != NULL
			    ? *STATE_PROG_ARGV (sd)
			    : NULL), abfd) != SIM_RC_OK)
    {
      free_state (sd);
      return 0;
    }

  /* Establish any remaining configuration options.  */
  if (sim_config (sd) != SIM_RC_OK)
    {
      free_state (sd);
      return 0;
    }

  if (sim_post_argv_init (sd) != SIM_RC_OK)
    {
      free_state (sd);
      return 0;
    }

  /* Make sure delay slot mode is consistent with the loaded binary.  */
  if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_or1knd)
    or1k_cpucfgr |= SPR_FIELD_MASK_SYS_CPUCFGR_ND;
  else
    or1k_cpucfgr &= ~SPR_FIELD_MASK_SYS_CPUCFGR_ND;

  /* Open a copy of the cpu descriptor table and initialize the
     disassembler.  These initialization functions are generated by CGEN
     using the binutils scheme cpu description files.  */
  {
    CGEN_CPU_DESC cd =
      or1k_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name,
			    CGEN_ENDIAN_BIG);
    for (i = 0; i < MAX_NR_PROCESSORS; ++i)
      {
	SIM_CPU *cpu = STATE_CPU (sd, i);
	CPU_CPU_DESC (cpu) = cd;
	CPU_DISASSEMBLER (cpu) = sim_cgen_disassemble_insn;
      }
    or1k_cgen_init_dis (cd);
  }

  /* Do some final OpenRISC sim specific initializations.  */
  for (c = 0; c < MAX_NR_PROCESSORS; ++c)
    {
      SIM_CPU *cpu = STATE_CPU (sd, i);
      /* Only needed for profiling, but the structure member is small.  */
      memset (CPU_OR1K_MISC_PROFILE (cpu), 0,
	      sizeof (*CPU_OR1K_MISC_PROFILE (cpu)));

      or1k_cpu_init (sd, cpu, or1k_vr, or1k_upr, or1k_cpucfgr);
    }

  return sd;
}
\f

SIM_RC
sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
		     char * const *argv, char * const *envp)
{
  SIM_CPU *current_cpu = STATE_CPU (sd, 0);
  SIM_ADDR addr;

  if (abfd != NULL)
    addr = bfd_get_start_address (abfd);
  else
    addr = 0;
  sim_pc_set (current_cpu, addr);

  return SIM_RC_OK;
}
Commit	Line	Data
fa8b7c21	1	/* Main simulator entry points specific to the OR1K.
3666a048	2	Copyright (C) 2017-2021 Free Software Foundation, Inc.
fa8b7c21 SH	3
	4	This file is part of GDB, the GNU debugger.
	5
	6	This program is free software; you can redistribute it and/or modify
	7	it under the terms of the GNU General Public License as published by
	8	the Free Software Foundation; either version 3 of the License, or
	9	(at your option) any later version.
	10
	11	This program is distributed in the hope that it will be useful,
	12	but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	GNU General Public License for more details.
	15
	16	You should have received a copy of the GNU General Public License
	17	along with this program. If not, see <http://www.gnu.org/licenses/>. */
	18
6df01ab8 MF	19	/* This must come before any other includes. */
	20	#include "defs.h"
	21
fa8b7c21 SH	22	#include "sim-main.h"
	23	#include "sim-options.h"
	24	#include "libiberty.h"
	25	#include "bfd.h"
	26
fa8b7c21	27	#include <string.h>
fa8b7c21	28	#include <stdlib.h>
fa8b7c21 SH	29
	30	static void free_state (SIM_DESC);
	31	\f
	32
	33	/* Cover function of sim_state_free to free the cpu buffers as well. */
	34
	35	static void
	36	free_state (SIM_DESC sd)
	37	{
	38	if (STATE_MODULES (sd) != NULL)
	39	sim_module_uninstall (sd);
	40	sim_cpu_free_all (sd);
	41	sim_state_free (sd);
	42	}
	43
	44	/* Defaults for user passed arguments. */
	45	static const USI or1k_default_vr = 0x0;
	46	static const USI or1k_default_upr = 0x0
	47	\| SPR_FIELD_MASK_SYS_UPR_UP;
	48	static const USI or1k_default_cpucfgr = 0x0
	49	\| SPR_FIELD_MASK_SYS_CPUCFGR_OB32S
	50	\| SPR_FIELD_MASK_SYS_CPUCFGR_OF32S;
	51
	52	static UWI or1k_upr;
	53	static UWI or1k_vr;
	54	static UWI or1k_cpucfgr;
	55
	56	enum
	57	{
	58	OPTION_OR1K_VR,
	59	OPTION_OR1K_UPR,
	60	OPTION_OR1K_CPUCFGR = OPTION_START,
	61	};
	62
	63	/* Setup help and handlers for the user defined arguments. */
	64	DECLARE_OPTION_HANDLER (or1k_option_handler);
	65
	66	static const OPTION or1k_options[] = {
	67	{{"or1k-cpucfgr", required_argument, NULL, OPTION_OR1K_CPUCFGR},
	68	'\0', "INTEGER\|default", "Set simulator CPUCFGR value",
	69	or1k_option_handler},
	70	{{"or1k-vr", required_argument, NULL, OPTION_OR1K_VR},
	71	'\0', "INTEGER\|default", "Set simulator VR value",
	72	or1k_option_handler},
	73	{{"or1k-upr", required_argument, NULL, OPTION_OR1K_UPR},
	74	'\0', "INTEGER\|default", "Set simulator UPR value",
	75	or1k_option_handler},
	76	{{NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL}
	77	};
	78
	79	/* Handler for parsing user defined arguments. Currently we support
	80	configuring some of the CPU implementation specific registers including
	81	the Version Register (VR), the Unit Present Register (UPR) and the CPU
	82	Configuration Register (CPUCFGR). */
	83	SIM_RC
	84	or1k_option_handler (SIM_DESC sd, sim_cpu cpu, int opt, char arg,
	85	int is_command)
	86	{
	87	switch (opt)
	88	{
	89	case OPTION_OR1K_VR:
	90	if (strcmp ("default", arg) == 0)
	91	or1k_vr = or1k_default_vr;
	92	else
93	{
94	unsigned long long n;
95	char *endptr;
96
97	n = strtoull (arg, &endptr, 0);
98	if (arg != '\0' && endptr == '\0')
99	or1k_vr = n;
100	else
101	return SIM_RC_FAIL;
102	}
103	return SIM_RC_OK;
104
105	case OPTION_OR1K_UPR:
106	if (strcmp ("default", arg) == 0)
107	or1k_upr = or1k_default_upr;
108	else
109	{
110	unsigned long long n;
111	char *endptr;
112
113	n = strtoull (arg, &endptr, 0);
114	if (arg != '\0' && endptr == '\0')
115	or1k_upr = n;
116	else
117	{
118	sim_io_eprintf
119	(sd, "invalid argument to option --or1k-upr: `%s'\n", arg);
120	return SIM_RC_FAIL;
121	}
122	}
123	return SIM_RC_OK;
124
125	case OPTION_OR1K_CPUCFGR:
126	if (strcmp ("default", arg) == 0)
127	or1k_cpucfgr = or1k_default_cpucfgr;
128	else
129	{
130	unsigned long long n;
131	char *endptr;
132
133	n = strtoull (arg, &endptr, 0);
134	if (arg != '\0' && endptr == '\0')
135	or1k_cpucfgr = n;
136	else
137	{
138	sim_io_eprintf
139	(sd, "invalid argument to option --or1k-cpucfgr: `%s'\n", arg);
140	return SIM_RC_FAIL;
141	}
142	}
143	return SIM_RC_OK;
144
145	default:
146	sim_io_eprintf (sd, "Unknown or1k option %d\n", opt);
147	return SIM_RC_FAIL;
148	}
149
150	return SIM_RC_FAIL;
151	}
152
1c636da0 MF	153	extern const SIM_MACH * const or1k_sim_machs[];
1c636da0 MF	154
fa8b7c21 SH	155	/* Create an instance of the simulator. */
	156
	157	SIM_DESC
	158	sim_open (SIM_OPEN_KIND kind, host_callback callback, struct bfd abfd,
	159	char * const *argv)
	160	{
	161	SIM_DESC sd = sim_state_alloc (kind, callback);
	162	char c;
	163	int i;
	164
f9a4d543	165	/* Set default options before parsing user options. */
1c636da0	166	STATE_MACHS (sd) = or1k_sim_machs;
f9a4d543 MF	167	current_target_byte_order = BFD_ENDIAN_BIG;
f9a4d543 MF	168
fa8b7c21	169	/* The cpu data is kept in a separately allocated chunk of memory. */
d5a71b11	170	if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)
fa8b7c21 SH	171	{
	172	free_state (sd);
	173	return 0;
	174	}
	175
	176	/* Perform initial sim setups. */
	177	if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
	178	{
	179	free_state (sd);
	180	return 0;
	181	}
	182
	183	or1k_upr = or1k_default_upr;
	184	or1k_vr = or1k_default_vr;
	185	or1k_cpucfgr = or1k_default_cpucfgr;
	186	sim_add_option_table (sd, NULL, or1k_options);
	187
	188	/* Parse the user passed arguments. */
	189	if (sim_parse_args (sd, argv) != SIM_RC_OK)
	190	{
	191	free_state (sd);
	192	return 0;
	193	}
	194
	195	/* Allocate core managed memory if none specified by user.
	196	Use address 4 here in case the user wanted address 0 unmapped. */
	197	if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0)
	198	{
	199	sim_do_commandf (sd, "memory region 0,0x%x", OR1K_DEFAULT_MEM_SIZE);
	200	}
	201
	202	/* Check for/establish the reference program image. */
	203	if (sim_analyze_program (sd,
	204	(STATE_PROG_ARGV (sd) != NULL
	205	? *STATE_PROG_ARGV (sd)
	206	: NULL), abfd) != SIM_RC_OK)
	207	{
	208	free_state (sd);
	209	return 0;
	210	}
	211
	212	/* Establish any remaining configuration options. */
	213	if (sim_config (sd) != SIM_RC_OK)
	214	{
	215	free_state (sd);
	216	return 0;
	217	}
	218
	219	if (sim_post_argv_init (sd) != SIM_RC_OK)
	220	{
	221	free_state (sd);
	222	return 0;
	223	}
	224
	225	/* Make sure delay slot mode is consistent with the loaded binary. */
	226	if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_or1knd)
	227	or1k_cpucfgr \|= SPR_FIELD_MASK_SYS_CPUCFGR_ND;
	228	else
	229	or1k_cpucfgr &= ~SPR_FIELD_MASK_SYS_CPUCFGR_ND;
	230
	231	/* Open a copy of the cpu descriptor table and initialize the
	232	disassembler. These initialization functions are generated by CGEN
	233	using the binutils scheme cpu description files. */
	234	{
235	CGEN_CPU_DESC cd =
236	or1k_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name,
237	CGEN_ENDIAN_BIG);
238	for (i = 0; i < MAX_NR_PROCESSORS; ++i)
239	{
240	SIM_CPU *cpu = STATE_CPU (sd, i);
241	CPU_CPU_DESC (cpu) = cd;
242	CPU_DISASSEMBLER (cpu) = sim_cgen_disassemble_insn;
243	}
244	or1k_cgen_init_dis (cd);
245	}
246
fa8b7c21 SH	247	/* Do some final OpenRISC sim specific initializations. */
	248	for (c = 0; c < MAX_NR_PROCESSORS; ++c)
	249	{
	250	SIM_CPU *cpu = STATE_CPU (sd, i);
	251	/* Only needed for profiling, but the structure member is small. */
	252	memset (CPU_OR1K_MISC_PROFILE (cpu), 0,
	253	sizeof (*CPU_OR1K_MISC_PROFILE (cpu)));
	254
	255	or1k_cpu_init (sd, cpu, or1k_vr, or1k_upr, or1k_cpucfgr);
	256	}
	257
	258	return sd;
	259	}
	260	\f
	261
	262	SIM_RC
	263	sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
	264	char * const argv, char const *envp)
	265	{
	266	SIM_CPU *current_cpu = STATE_CPU (sd, 0);
	267	SIM_ADDR addr;
	268
	269	if (abfd != NULL)
	270	addr = bfd_get_start_address (abfd);
	271	else
	272	addr = 0;
	273	sim_pc_set (current_cpu, addr);
	274
	275	return SIM_RC_OK;
	276	}