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fa8b7c21 | 1 | /* Main simulator entry points specific to the OR1K. |
3666a048 | 2 | Copyright (C) 2017-2021 Free Software Foundation, Inc. |
fa8b7c21 SH |
3 | |
4 | This file is part of GDB, the GNU debugger. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 3 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
18 | ||
19 | #include "sim-main.h" | |
20 | #include "sim-options.h" | |
21 | #include "libiberty.h" | |
22 | #include "bfd.h" | |
23 | ||
fa8b7c21 | 24 | #include <string.h> |
fa8b7c21 | 25 | #include <stdlib.h> |
fa8b7c21 SH |
26 | |
27 | static void free_state (SIM_DESC); | |
28 | \f | |
29 | ||
30 | /* Cover function of sim_state_free to free the cpu buffers as well. */ | |
31 | ||
32 | static void | |
33 | free_state (SIM_DESC sd) | |
34 | { | |
35 | if (STATE_MODULES (sd) != NULL) | |
36 | sim_module_uninstall (sd); | |
37 | sim_cpu_free_all (sd); | |
38 | sim_state_free (sd); | |
39 | } | |
40 | ||
41 | /* Defaults for user passed arguments. */ | |
42 | static const USI or1k_default_vr = 0x0; | |
43 | static const USI or1k_default_upr = 0x0 | |
44 | | SPR_FIELD_MASK_SYS_UPR_UP; | |
45 | static const USI or1k_default_cpucfgr = 0x0 | |
46 | | SPR_FIELD_MASK_SYS_CPUCFGR_OB32S | |
47 | | SPR_FIELD_MASK_SYS_CPUCFGR_OF32S; | |
48 | ||
49 | static UWI or1k_upr; | |
50 | static UWI or1k_vr; | |
51 | static UWI or1k_cpucfgr; | |
52 | ||
53 | enum | |
54 | { | |
55 | OPTION_OR1K_VR, | |
56 | OPTION_OR1K_UPR, | |
57 | OPTION_OR1K_CPUCFGR = OPTION_START, | |
58 | }; | |
59 | ||
60 | /* Setup help and handlers for the user defined arguments. */ | |
61 | DECLARE_OPTION_HANDLER (or1k_option_handler); | |
62 | ||
63 | static const OPTION or1k_options[] = { | |
64 | {{"or1k-cpucfgr", required_argument, NULL, OPTION_OR1K_CPUCFGR}, | |
65 | '\0', "INTEGER|default", "Set simulator CPUCFGR value", | |
66 | or1k_option_handler}, | |
67 | {{"or1k-vr", required_argument, NULL, OPTION_OR1K_VR}, | |
68 | '\0', "INTEGER|default", "Set simulator VR value", | |
69 | or1k_option_handler}, | |
70 | {{"or1k-upr", required_argument, NULL, OPTION_OR1K_UPR}, | |
71 | '\0', "INTEGER|default", "Set simulator UPR value", | |
72 | or1k_option_handler}, | |
73 | {{NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL} | |
74 | }; | |
75 | ||
76 | /* Handler for parsing user defined arguments. Currently we support | |
77 | configuring some of the CPU implementation specific registers including | |
78 | the Version Register (VR), the Unit Present Register (UPR) and the CPU | |
79 | Configuration Register (CPUCFGR). */ | |
80 | SIM_RC | |
81 | or1k_option_handler (SIM_DESC sd, sim_cpu *cpu, int opt, char *arg, | |
82 | int is_command) | |
83 | { | |
84 | switch (opt) | |
85 | { | |
86 | case OPTION_OR1K_VR: | |
87 | if (strcmp ("default", arg) == 0) | |
88 | or1k_vr = or1k_default_vr; | |
89 | else | |
90 | { | |
91 | unsigned long long n; | |
92 | char *endptr; | |
93 | ||
94 | n = strtoull (arg, &endptr, 0); | |
95 | if (*arg != '\0' && *endptr == '\0') | |
96 | or1k_vr = n; | |
97 | else | |
98 | return SIM_RC_FAIL; | |
99 | } | |
100 | return SIM_RC_OK; | |
101 | ||
102 | case OPTION_OR1K_UPR: | |
103 | if (strcmp ("default", arg) == 0) | |
104 | or1k_upr = or1k_default_upr; | |
105 | else | |
106 | { | |
107 | unsigned long long n; | |
108 | char *endptr; | |
109 | ||
110 | n = strtoull (arg, &endptr, 0); | |
111 | if (*arg != '\0' && *endptr == '\0') | |
112 | or1k_upr = n; | |
113 | else | |
114 | { | |
115 | sim_io_eprintf | |
116 | (sd, "invalid argument to option --or1k-upr: `%s'\n", arg); | |
117 | return SIM_RC_FAIL; | |
118 | } | |
119 | } | |
120 | return SIM_RC_OK; | |
121 | ||
122 | case OPTION_OR1K_CPUCFGR: | |
123 | if (strcmp ("default", arg) == 0) | |
124 | or1k_cpucfgr = or1k_default_cpucfgr; | |
125 | else | |
126 | { | |
127 | unsigned long long n; | |
128 | char *endptr; | |
129 | ||
130 | n = strtoull (arg, &endptr, 0); | |
131 | if (*arg != '\0' && *endptr == '\0') | |
132 | or1k_cpucfgr = n; | |
133 | else | |
134 | { | |
135 | sim_io_eprintf | |
136 | (sd, "invalid argument to option --or1k-cpucfgr: `%s'\n", arg); | |
137 | return SIM_RC_FAIL; | |
138 | } | |
139 | } | |
140 | return SIM_RC_OK; | |
141 | ||
142 | default: | |
143 | sim_io_eprintf (sd, "Unknown or1k option %d\n", opt); | |
144 | return SIM_RC_FAIL; | |
145 | } | |
146 | ||
147 | return SIM_RC_FAIL; | |
148 | } | |
149 | ||
150 | /* Create an instance of the simulator. */ | |
151 | ||
152 | SIM_DESC | |
153 | sim_open (SIM_OPEN_KIND kind, host_callback *callback, struct bfd *abfd, | |
154 | char * const *argv) | |
155 | { | |
156 | SIM_DESC sd = sim_state_alloc (kind, callback); | |
157 | char c; | |
158 | int i; | |
159 | ||
160 | /* The cpu data is kept in a separately allocated chunk of memory. */ | |
161 | if (sim_cpu_alloc_all (sd, 1, cgen_cpu_max_extra_bytes ()) != SIM_RC_OK) | |
162 | { | |
163 | free_state (sd); | |
164 | return 0; | |
165 | } | |
166 | ||
167 | /* Perform initial sim setups. */ | |
168 | if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) | |
169 | { | |
170 | free_state (sd); | |
171 | return 0; | |
172 | } | |
173 | ||
174 | or1k_upr = or1k_default_upr; | |
175 | or1k_vr = or1k_default_vr; | |
176 | or1k_cpucfgr = or1k_default_cpucfgr; | |
177 | sim_add_option_table (sd, NULL, or1k_options); | |
178 | ||
179 | /* Parse the user passed arguments. */ | |
180 | if (sim_parse_args (sd, argv) != SIM_RC_OK) | |
181 | { | |
182 | free_state (sd); | |
183 | return 0; | |
184 | } | |
185 | ||
186 | /* Allocate core managed memory if none specified by user. | |
187 | Use address 4 here in case the user wanted address 0 unmapped. */ | |
188 | if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0) | |
189 | { | |
190 | sim_do_commandf (sd, "memory region 0,0x%x", OR1K_DEFAULT_MEM_SIZE); | |
191 | } | |
192 | ||
193 | /* Check for/establish the reference program image. */ | |
194 | if (sim_analyze_program (sd, | |
195 | (STATE_PROG_ARGV (sd) != NULL | |
196 | ? *STATE_PROG_ARGV (sd) | |
197 | : NULL), abfd) != SIM_RC_OK) | |
198 | { | |
199 | free_state (sd); | |
200 | return 0; | |
201 | } | |
202 | ||
203 | /* Establish any remaining configuration options. */ | |
204 | if (sim_config (sd) != SIM_RC_OK) | |
205 | { | |
206 | free_state (sd); | |
207 | return 0; | |
208 | } | |
209 | ||
210 | if (sim_post_argv_init (sd) != SIM_RC_OK) | |
211 | { | |
212 | free_state (sd); | |
213 | return 0; | |
214 | } | |
215 | ||
216 | /* Make sure delay slot mode is consistent with the loaded binary. */ | |
217 | if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_or1knd) | |
218 | or1k_cpucfgr |= SPR_FIELD_MASK_SYS_CPUCFGR_ND; | |
219 | else | |
220 | or1k_cpucfgr &= ~SPR_FIELD_MASK_SYS_CPUCFGR_ND; | |
221 | ||
222 | /* Open a copy of the cpu descriptor table and initialize the | |
223 | disassembler. These initialization functions are generated by CGEN | |
224 | using the binutils scheme cpu description files. */ | |
225 | { | |
226 | CGEN_CPU_DESC cd = | |
227 | or1k_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name, | |
228 | CGEN_ENDIAN_BIG); | |
229 | for (i = 0; i < MAX_NR_PROCESSORS; ++i) | |
230 | { | |
231 | SIM_CPU *cpu = STATE_CPU (sd, i); | |
232 | CPU_CPU_DESC (cpu) = cd; | |
233 | CPU_DISASSEMBLER (cpu) = sim_cgen_disassemble_insn; | |
234 | } | |
235 | or1k_cgen_init_dis (cd); | |
236 | } | |
237 | ||
238 | /* Initialize various cgen things not done by common framework. | |
239 | Must be done after or1k_cgen_cpu_open. */ | |
240 | cgen_init (sd); | |
241 | ||
242 | /* Do some final OpenRISC sim specific initializations. */ | |
243 | for (c = 0; c < MAX_NR_PROCESSORS; ++c) | |
244 | { | |
245 | SIM_CPU *cpu = STATE_CPU (sd, i); | |
246 | /* Only needed for profiling, but the structure member is small. */ | |
247 | memset (CPU_OR1K_MISC_PROFILE (cpu), 0, | |
248 | sizeof (*CPU_OR1K_MISC_PROFILE (cpu))); | |
249 | ||
250 | or1k_cpu_init (sd, cpu, or1k_vr, or1k_upr, or1k_cpucfgr); | |
251 | } | |
252 | ||
253 | return sd; | |
254 | } | |
255 | \f | |
256 | ||
257 | SIM_RC | |
258 | sim_create_inferior (SIM_DESC sd, struct bfd *abfd, | |
259 | char * const *argv, char * const *envp) | |
260 | { | |
261 | SIM_CPU *current_cpu = STATE_CPU (sd, 0); | |
262 | SIM_ADDR addr; | |
263 | ||
264 | if (abfd != NULL) | |
265 | addr = bfd_get_start_address (abfd); | |
266 | else | |
267 | addr = 0; | |
268 | sim_pc_set (current_cpu, addr); | |
269 | ||
270 | return SIM_RC_OK; | |
271 | } |