Commit | Line | Data |
---|---|---|
c906108c SS |
1 | /* This file is part of the program psim. |
2 | ||
3 | Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au> | |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
3fd725ef | 7 | the Free Software Foundation; either version 3 of the License, or |
c906108c SS |
8 | (at your option) any later version. |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
51b318de | 16 | along with this program; if not, see <http://www.gnu.org/licenses/>. |
c906108c SS |
17 | |
18 | */ | |
19 | ||
20 | ||
21 | #ifndef _CPU_H_ | |
22 | #define _CPU_H_ | |
23 | ||
24 | #include "basics.h" | |
25 | #include "registers.h" | |
26 | #include "device.h" | |
27 | #include "corefile.h" | |
28 | #include "vm.h" | |
29 | #include "events.h" | |
30 | #include "interrupts.h" | |
31 | #include "psim.h" | |
32 | #include "idecode.h" | |
33 | #include "itable.h" | |
34 | #include "os_emul.h" | |
35 | #include "mon.h" | |
36 | #include "model.h" | |
37 | ||
38 | #ifndef CONST_ATTRIBUTE | |
39 | #define CONST_ATTRIBUTE __attribute__((__const__)) | |
40 | #endif | |
41 | ||
42 | /* typedef struct _cpu cpu; | |
43 | ||
44 | Declared in basics.h because it is used opaquely throughout the | |
45 | code */ | |
46 | ||
47 | ||
48 | /* Create a cpu object */ | |
49 | ||
50 | INLINE_CPU\ | |
51 | (cpu *) cpu_create | |
52 | (psim *system, | |
53 | core *memory, | |
54 | cpu_mon *monitor, | |
55 | os_emul *cpu_emulation, | |
56 | int cpu_nr); | |
57 | ||
58 | INLINE_CPU\ | |
59 | (void) cpu_init | |
60 | (cpu *processor); | |
61 | ||
62 | /* Find our way home */ | |
63 | ||
64 | INLINE_CPU\ | |
65 | (psim *) cpu_system | |
66 | (cpu *processor) CONST_ATTRIBUTE; | |
67 | ||
68 | INLINE_CPU\ | |
69 | (cpu_mon *) cpu_monitor | |
70 | (cpu *processor) CONST_ATTRIBUTE; | |
71 | ||
72 | INLINE_CPU\ | |
73 | (os_emul *) cpu_os_emulation | |
74 | (cpu *processor); | |
75 | ||
76 | INLINE_CPU\ | |
77 | (int) cpu_nr | |
78 | (cpu *processor) CONST_ATTRIBUTE; | |
79 | ||
80 | ||
81 | /* manipulate the processors program counter and execution state. | |
82 | ||
83 | The program counter is not included in the register file. Instead | |
84 | it is extracted and then later restored (set, reset, halt). This | |
85 | is to give the user of the cpu (and the compiler) the chance to | |
86 | minimize the need to load/store the cpu's PC value. (Especially in | |
87 | the case of a single processor) */ | |
88 | ||
89 | INLINE_CPU\ | |
90 | (void) cpu_set_program_counter | |
91 | (cpu *processor, | |
92 | unsigned_word new_program_counter); | |
93 | ||
94 | INLINE_CPU\ | |
95 | (unsigned_word) cpu_get_program_counter | |
96 | (cpu *processor); | |
97 | ||
98 | INLINE_CPU\ | |
99 | (void) cpu_restart | |
100 | (cpu *processor, | |
101 | unsigned_word nia); | |
102 | ||
103 | INLINE_CPU\ | |
104 | (void) cpu_halt | |
105 | (cpu *processor, | |
106 | unsigned_word nia, | |
107 | stop_reason reason, | |
108 | int signal); | |
109 | ||
110 | EXTERN_CPU\ | |
111 | (void) cpu_error | |
112 | (cpu *processor, | |
113 | unsigned_word cia, | |
114 | const char *fmt, | |
115 | ...) __attribute__ ((format (printf, 3, 4))); | |
116 | ||
117 | ||
118 | /* The processors local concept of time */ | |
119 | ||
120 | INLINE_CPU\ | |
121 | (signed64) cpu_get_time_base | |
122 | (cpu *processor); | |
123 | ||
124 | INLINE_CPU\ | |
125 | (void) cpu_set_time_base | |
126 | (cpu *processor, | |
127 | signed64 time_base); | |
128 | ||
129 | INLINE_CPU\ | |
130 | (signed32) cpu_get_decrementer | |
131 | (cpu *processor); | |
132 | ||
133 | INLINE_CPU\ | |
134 | (void) cpu_set_decrementer | |
135 | (cpu *processor, | |
136 | signed32 decrementer); | |
137 | ||
138 | ||
139 | #if WITH_IDECODE_CACHE_SIZE | |
140 | /* Return the cache entry that matches the given CIA. No guarentee | |
141 | that the cache entry actually contains the instruction for that | |
142 | address */ | |
143 | ||
144 | INLINE_CPU\ | |
145 | (idecode_cache) *cpu_icache_entry | |
146 | (cpu *processor, | |
147 | unsigned_word cia); | |
148 | ||
149 | INLINE_CPU\ | |
150 | (void) cpu_flush_icache | |
151 | (cpu *processor); | |
152 | #endif | |
153 | ||
154 | ||
155 | /* reveal the processors VM: | |
156 | ||
157 | At first sight it may seem better to, instead of exposing the cpu's | |
158 | inner vm maps, to have the cpu its self provide memory manipulation | |
159 | functions. (eg cpu_instruction_fetch() cpu_data_read_4()) | |
160 | ||
161 | Unfortunatly in addition to these functions is the need (for the | |
162 | debugger) to be able to read/write to memory in ways that violate | |
163 | the vm protection (eg store breakpoint instruction in the | |
164 | instruction map). */ | |
165 | ||
166 | INLINE_CPU\ | |
167 | (vm_data_map *) cpu_data_map | |
168 | (cpu *processor); | |
169 | ||
170 | INLINE_CPU\ | |
171 | (vm_instruction_map *) cpu_instruction_map | |
172 | (cpu *processor); | |
173 | ||
174 | INLINE_CPU\ | |
175 | (void) cpu_page_tlb_invalidate_entry | |
176 | (cpu *processor, | |
177 | unsigned_word ea); | |
178 | ||
179 | INLINE_CPU\ | |
180 | (void) cpu_page_tlb_invalidate_all | |
181 | (cpu *processor); | |
182 | ||
183 | ||
184 | /* reveal the processors interrupt state */ | |
185 | ||
186 | INLINE_CPU\ | |
187 | (interrupts *) cpu_interrupts | |
188 | (cpu *processor); | |
189 | ||
190 | ||
191 | /* grant access to the reservation information */ | |
192 | ||
193 | typedef struct _memory_reservation { | |
194 | int valid; | |
195 | unsigned_word addr; | |
196 | unsigned_word data; | |
197 | } memory_reservation; | |
198 | ||
199 | INLINE_CPU\ | |
200 | (memory_reservation *) cpu_reservation | |
201 | (cpu *processor); | |
202 | ||
203 | ||
204 | /* Registers: | |
205 | ||
206 | This model exploits the PowerPC's requirement for a synchronization | |
207 | to occure after (or before) the update of any context controlling | |
208 | register. All context sync points must call the sync function | |
209 | below to when ever a synchronization point is reached */ | |
210 | ||
211 | INLINE_CPU\ | |
212 | (registers *) cpu_registers | |
213 | (cpu *processor) CONST_ATTRIBUTE; | |
214 | ||
215 | INLINE_CPU\ | |
216 | (void) cpu_synchronize_context | |
217 | (cpu *processor, | |
218 | unsigned_word cia); | |
219 | ||
220 | #define IS_PROBLEM_STATE(PROCESSOR) \ | |
221 | (CURRENT_ENVIRONMENT == OPERATING_ENVIRONMENT \ | |
222 | ? (cpu_registers(PROCESSOR)->msr & msr_problem_state) \ | |
223 | : 1) | |
224 | ||
225 | #define IS_64BIT_MODE(PROCESSOR) \ | |
226 | (WITH_TARGET_WORD_BITSIZE == 64 \ | |
227 | ? (CURRENT_ENVIRONMENT == OPERATING_ENVIRONMENT \ | |
228 | ? (cpu_registers(PROCESSOR)->msr & msr_64bit_mode) \ | |
229 | : 1) \ | |
230 | : 0) | |
231 | ||
232 | #define IS_FP_AVAILABLE(PROCESSOR) \ | |
233 | (CURRENT_ENVIRONMENT == OPERATING_ENVIRONMENT \ | |
234 | ? (cpu_registers(PROCESSOR)->msr & msr_floating_point_available) \ | |
235 | : 1) | |
236 | ||
237 | ||
238 | ||
239 | INLINE_CPU\ | |
240 | (void) cpu_print_info | |
241 | (cpu *processor, | |
242 | int verbose); | |
243 | ||
244 | INLINE_CPU\ | |
245 | (model_data *) cpu_model | |
246 | (cpu *processor) CONST_ATTRIBUTE; | |
247 | ||
248 | ||
249 | #if (CPU_INLINE & INCLUDE_MODULE) | |
250 | # include "cpu.c" | |
251 | #endif | |
252 | ||
253 | #endif |