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345d88d9 AC |
1 | /* e500 registers, for PSIM, the PowerPC simulator. |
2 | ||
3 | Copyright 2003 Free Software Foundation, Inc. | |
4 | ||
5 | Contributed by Red Hat Inc; developed under contract from Motorola. | |
6 | Written by matthew green <mrg@redhat.com>. | |
7 | ||
8 | This file is part of GDB. | |
9 | ||
10 | This program is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2 of the License, or | |
13 | (at your option) any later version. | |
14 | ||
15 | This program is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with this program; if not, write to the Free Software | |
22 | Foundation, Inc., 59 Temple Place - Suite 330, | |
23 | Boston, MA 02111-1307, USA. */ | |
24 | ||
25 | /* e500 accumulator. */ | |
26 | ||
27 | typedef unsigned64 accreg; | |
28 | ||
29 | enum { | |
30 | msr_e500_spu_enable = BIT(38) | |
31 | }; | |
32 | ||
33 | /* E500 regsiters. */ | |
34 | ||
35 | enum | |
36 | { | |
37 | spefscr_sovh = BIT(32), /* summary integer overlow (high) */ | |
38 | spefscr_ovh = BIT(33), /* int overflow (high) */ | |
39 | spefscr_fgh = BIT(34), /* FP guard (high) */ | |
40 | spefscr_fxh = BIT(35), /* FP sticky (high) */ | |
41 | spefscr_finvh = BIT(36), /* FP invalid operand (high) */ | |
42 | spefscr_fdbzh = BIT(37), /* FP divide by zero (high) */ | |
43 | spefscr_funfh = BIT(38), /* FP underflow (high) */ | |
44 | spefscr_fovfh = BIT(39), /* FP overflow (high) */ | |
45 | spefscr_finxs = BIT(42), /* FP inexact sticky */ | |
46 | spefscr_finvs = BIT(43), /* FP invalid operand sticky */ | |
47 | spefscr_fdbzs = BIT(44), /* FP divide by zero sticky */ | |
48 | spefscr_funfs = BIT(45), /* FP underflow sticky */ | |
49 | spefscr_fovfs = BIT(46), /* FP overflow sticky */ | |
50 | spefscr_mode = BIT(47), /* SPU MODE (read only) */ | |
51 | spefscr_sov = BIT(48), /* Summary integer overlow (low) */ | |
52 | spefscr_ov = BIT(49), /* int overflow (low) */ | |
53 | spefscr_fg = BIT(50), /* FP guard (low) */ | |
54 | spefscr_fx = BIT(51), /* FP sticky (low) */ | |
55 | spefscr_finv = BIT(52), /* FP invalid operand (low) */ | |
56 | spefscr_fdbz = BIT(53), /* FP divide by zero (low) */ | |
57 | spefscr_funf = BIT(54), /* FP underflow (low) */ | |
58 | spefscr_fovf = BIT(55), /* FP overflow (low) */ | |
59 | spefscr_finxe = BIT(57), /* FP inexact enable */ | |
60 | spefscr_finve = BIT(58), /* FP invalid operand enable */ | |
61 | spefscr_fdbze = BIT(59), /* FP divide by zero enable */ | |
62 | spefscr_funfe = BIT(60), /* FP underflow enable */ | |
63 | spefscr_fovfe = BIT(61), /* FP overflow enable */ | |
64 | spefscr_frmc0 = BIT(62), /* FP round mode control */ | |
65 | spefscr_frmc1 = BIT(63), | |
66 | spefscr_frmc = (spefscr_frmc0 | spefscr_frmc1), | |
67 | }; | |
68 | ||
69 | struct e500_regs { | |
70 | /* e500 high bits. */ | |
71 | signed_word gprh[32]; | |
72 | /* Accumulator */ | |
73 | accreg acc; | |
74 | }; | |
75 | ||
76 | /* SPE partially visible acculator */ | |
77 | #define ACC cpu_registers(processor)->e500.acc | |
78 | ||
79 | /* e500 register high bits */ | |
80 | #define GPRH(N) cpu_registers(processor)->e500.gprh[N] | |
81 | ||
71d39cfc JB |
82 | /* e500 unified vector register |
83 | We need to cast the gpr value to an unsigned type so that it | |
84 | doesn't get sign-extended when it's or-ed with a 64-bit value; that | |
85 | would wipe out the upper 32 bits of the register's value. */ | |
86 | #define EVR(N) ((((unsigned64)GPRH(N)) << 32) | (unsigned32) GPR(N)) |