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c906108c SS |
1 | /* This file is part of the program psim. |
2 | ||
3 | Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au> | |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
3fd725ef | 7 | the Free Software Foundation; either version 3 of the License, or |
c906108c SS |
8 | (at your option) any later version. |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
51b318de | 16 | along with this program; if not, see <http://www.gnu.org/licenses/>. |
c906108c SS |
17 | |
18 | */ | |
19 | ||
20 | ||
21 | /* Instruction field macros: | |
22 | ||
23 | The macro's below greatly simplify the process of translating the | |
24 | pseudo code found in the PowerPC manual into C. | |
25 | ||
26 | In addition to the below, more will be found in the gen program's | |
27 | cache table */ | |
28 | ||
29 | ||
30 | /* map some statements and variables directly across */ | |
31 | ||
32 | #define is_64bit_implementation (WITH_TARGET_WORD_BITSIZE == 64) | |
33 | #define is_64bit_mode IS_64BIT_MODE(processor) | |
34 | ||
35 | #define NIA nia | |
36 | #define CIA cia | |
37 | ||
38 | ||
39 | /* reservation */ | |
40 | ||
41 | #define RESERVE cpu_reservation(processor)->valid | |
42 | #define RESERVE_ADDR cpu_reservation(processor)->addr | |
43 | #define RESERVE_DATA cpu_reservation(processor)->data | |
44 | ||
45 | #define real_addr(EA, IS_READ) vm_real_data_addr(cpu_data_map(processor), \ | |
46 | EA, \ | |
47 | IS_READ, \ | |
48 | processor, \ | |
49 | cia) | |
50 | ||
51 | ||
52 | /* depending on mode return a 32 or 64bit number */ | |
53 | ||
54 | #define IEA(X) (is_64bit_mode \ | |
55 | ? (X) \ | |
56 | : MASKED((X), 32, 63)) | |
57 | ||
58 | /* Expand argument to current architecture size */ | |
59 | ||
60 | #define EXTS(X) EXTS_##X | |
61 | ||
62 | ||
63 | /* Gen translates text of the form A{XX:YY} into A_XX_YY_ the macro's | |
64 | below define such translated text into real expressions */ | |
65 | ||
66 | /* the spr field as it normally is used */ | |
67 | ||
68 | #define SPR_5_9_ (SPR & 0x1f) | |
69 | #define SPR_0_4_ (SPR >> 5) | |
70 | #define SPR_0_ ((SPR & BIT10(0)) != 0) | |
71 | ||
72 | #define tbr_5_9_ (tbr & 0x1f) | |
73 | #define tbr_0_4_ (tbr >> 5) | |
74 | ||
75 | ||
76 | #define TB cpu_get_time_base(processor) | |
77 | ||
78 | ||
79 | /* various registers with important masks */ | |
80 | ||
81 | #define LR_0b00 (LR & ~3) | |
82 | #define CTR_0b00 (CTR & ~3) | |
83 | ||
84 | #define CR_BI_ ((CR & BIT32_BI) != 0) | |
85 | #define CR_BA_ ((CR & BIT32_BA) != 0) | |
86 | #define CR_BB_ ((CR & BIT32_BB) != 0) | |
87 | ||
88 | ||
89 | /* extended extracted fields */ | |
90 | ||
91 | #define TO_0_ ((TO & BIT5(0)) != 0) | |
92 | #define TO_1_ ((TO & BIT5(1)) != 0) | |
93 | #define TO_2_ ((TO & BIT5(2)) != 0) | |
94 | #define TO_3_ ((TO & BIT5(3)) != 0) | |
95 | #define TO_4_ ((TO & BIT5(4)) != 0) | |
96 | ||
97 | #define BO_0_ ((BO & BIT5(0)) != 0) | |
98 | #define BO_1_ ((BO & BIT5(1)) != 0) | |
99 | #define BO_2_ ((BO & BIT5(2)) != 0) | |
100 | #define BO_3_ ((BO & BIT5(3)) != 0) | |
101 | #define BO_4_ ((BO & BIT5(4)) != 0) | |
102 | ||
103 | #define GOTO(dest) goto XCONCAT4(label__,dest,__,MY_PREFIX) | |
104 | #define LABEL(dest) XCONCAT4(label__,dest,__,MY_PREFIX) |