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5b4d72dd MM |
1 | # |
2 | # This file is part of the program psim. | |
3 | # | |
4 | # Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au> | |
5 | # | |
6 | # This program is free software; you can redistribute it and/or modify | |
7 | # it under the terms of the GNU General Public License as published by | |
8 | # the Free Software Foundation; either version 2 of the License, or | |
9 | # (at your option) any later version. | |
10 | # | |
11 | # This program is distributed in the hope that it will be useful, | |
12 | # but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | # GNU General Public License for more details. | |
15 | # | |
16 | # You should have received a copy of the GNU General Public License | |
17 | # along with this program; if not, write to the Free Software | |
18 | # Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | # | |
20 | # | |
21 | # Instruction unpacking: | |
22 | # | |
23 | # Once the instruction has been decoded, the register (and other) | |
24 | # fields within the instruction need to be extracted. | |
25 | # | |
26 | # The table that follows determines how each field should be treated. | |
27 | # Importantly it considers the case where the extracted field is to | |
28 | # be used immediatly or stored in an instruction cache. | |
29 | # | |
30 | # <valid> | |
31 | # | |
32 | # Zero marks the end of the table. More importantly 1. indicates | |
33 | # that the entry is valid and can be cached. 2. indicates that that | |
34 | # the entry is valid but can not be cached. | |
35 | # | |
36 | # <old_name> | |
37 | # | |
38 | # The field name as given in the instruction spec. | |
39 | # | |
40 | # <new_name> | |
41 | # | |
42 | # A name for <old_name> once it has been extracted from the | |
43 | # instructioin (and possibly stored in the instruction cache). | |
44 | # | |
45 | # <type> | |
46 | # | |
47 | # String specifying the storage type for <new_name> (the extracted | |
48 | # field>. | |
49 | # | |
50 | # <expression> | |
51 | # | |
52 | # Specifies how to get <new_name> from <old_name>. If null, old and | |
53 | # new name had better be the same. */ | |
54 | # | |
55 | # | |
56 | 1:RA:RA:: | |
57 | 1:RA:rA:signed_word *:(cpu_registers(processor)->gpr + RA) | |
45525d8d | 58 | 1:RA:RA_BITMASK:unsigned32:(1 << RA) |
5b4d72dd MM |
59 | 1:RT:RT:: |
60 | 1:RT:rT:signed_word *:(cpu_registers(processor)->gpr + RT) | |
45525d8d | 61 | 1:RT:RT_BITMASK:unsigned32:(1 << RT) |
5b4d72dd MM |
62 | 2:RS:RS:: |
63 | 1:RS:rS:signed_word *:(cpu_registers(processor)->gpr + RS) | |
45525d8d | 64 | 1:RS:RS_BITMASK:unsigned32:(1 << RS) |
5b4d72dd MM |
65 | 2:RB:RB:: |
66 | 1:RB:rB:signed_word *:(cpu_registers(processor)->gpr + RB) | |
45525d8d | 67 | 1:RB:RB_BITMASK:unsigned32:(1 << RB) |
5b4d72dd MM |
68 | 2:FRA:FRA:: |
69 | 1:FRA:frA:unsigned64 *:(cpu_registers(processor)->fpr + FRA) | |
45525d8d | 70 | 1:FRA:FRA_BITMASK:unsigned32:(1 << FRA) |
5b4d72dd MM |
71 | 2:FRB:FRB:: |
72 | 1:FRB:frB:unsigned64 *:(cpu_registers(processor)->fpr + FRB) | |
45525d8d | 73 | 1:FRB:FRB_BITMASK:unsigned32:(1 << FRB) |
5b4d72dd MM |
74 | 2:FRC:FRC:: |
75 | 1:FRC:frC:unsigned64 *:(cpu_registers(processor)->fpr + FRC) | |
45525d8d | 76 | 1:FRC:FRC_BITMASK:unsigned32:(1 << FRC) |
5b4d72dd MM |
77 | 2:FRS:FRS:: |
78 | 1:FRS:frS:unsigned64 *:(cpu_registers(processor)->fpr + FRS) | |
45525d8d | 79 | 1:FRS:FRS_BITMASK:unsigned32:(1 << FRS) |
5b4d72dd MM |
80 | 2:FRT:FRT:: |
81 | 1:FRT:frT:unsigned64 *:(cpu_registers(processor)->fpr + FRT) | |
45525d8d | 82 | 1:FRT:FRT_BITMASK:unsigned32:(1 << FRT) |
5b4d72dd MM |
83 | 1:SI:EXTS_SI:unsigned_word:((signed_word)(signed16)instruction) |
84 | 2:BI:BI:: | |
85 | 1:BI:BIT32_BI::BIT32(BI) | |
45525d8d MM |
86 | 1:BF:BF:: |
87 | 1:BF:BF_BITMASK:unsigned32:(1 << BF) | |
5b4d72dd MM |
88 | 2:BA:BA:: |
89 | 1:BA:BIT32_BA::BIT32(BA) | |
45525d8d | 90 | 1:BA:BA_BITMASK:unsigned32:(1 << BA) |
5b4d72dd MM |
91 | 2:BB:BB:: |
92 | 1:BB:BIT32_BB::BIT32(BB) | |
45525d8d MM |
93 | 1:BB:BB_BITMASK:unsigned32:(1 << BB) |
94 | 1:BT:BT:: | |
95 | 1:BT:BT_BITMASK:unsigned32:(1 << BT) | |
5b4d72dd MM |
96 | 1:BD:EXTS_BD_0b00:unsigned_word:(((signed_word)(signed16)instruction) & ~3) |
97 | #1:BD:CIA_plus_EXTS_BD_0b00:unsigned_word:CIA + EXTS(BD_0b00) | |
98 | 1:LI:EXTS_LI_0b00:unsigned_word:((((signed_word)(signed32)(instruction << 6)) >> 6) & ~0x3) | |
99 | 1:D:EXTS_D:unsigned_word:((signed_word)(signed16)(instruction)) | |
100 | 1:DS:EXTS_DS_0b00:unsigned_word:(((signed_word)(signed16)instruction) & ~0x3) |