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c143ef62 MM |
1 | # |
2 | # This file is part of the program psim. | |
3 | # | |
4 | # Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au> | |
5 | # | |
6 | # -- | |
7 | # | |
8 | # The pseudo-code that appears below, translated into C, was copied | |
9 | # by Andrew Cagney of Moss Vale, Australia. | |
10 | # | |
11 | # This pseudo-code is copied by permission from the publication | |
12 | # "The PowerPC Architecture: A Specification for A New Family of | |
13 | # RISC Processors" (ISBN 1-55860-316-6) copyright 1993, 1994 by | |
14 | # International Business Machines Corporation. | |
15 | # | |
16 | # THIS PERMISSION IS PROVIDED WITHOUT WARRANTY OF ANY KIND, EITHER | |
17 | # EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO IMPLIED WARRANTIES | |
18 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. | |
19 | # | |
20 | # -- | |
21 | # | |
22 | # This program is free software; you can redistribute it and/or modify | |
23 | # it under the terms of the GNU General Public License as published by | |
24 | # the Free Software Foundation; either version 2 of the License, or | |
25 | # (at your option) any later version. | |
26 | # | |
27 | # This program is distributed in the hope that it will be useful, | |
28 | # but WITHOUT ANY WARRANTY; without even the implied warranty of | |
29 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
30 | # GNU General Public License for more details. | |
31 | # | |
32 | # You should have received a copy of the GNU General Public License | |
33 | # along with this program; if not, write to the Free Software | |
34 | # Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
35 | # | |
36 | # -- | |
37 | # | |
38 | # | |
39 | # Fields: | |
40 | # | |
41 | # 1 Instruction format as a `start-bit,content' pairs. | |
42 | # the content is one of a digit, field name or `/' (aka.0) | |
43 | # | |
44 | # 2 Format specifier | |
45 | # | |
46 | # 3 Flags: 64 - 64bit only | |
47 | # f - floating point enabled required | |
48 | # | |
49 | # 4 short name | |
50 | # | |
51 | # 5 Description | |
52 | # | |
53 | ||
54 | # The following (illegal) instruction is `known' by gen and is | |
55 | # called when ever an illegal instruction is encountered | |
56 | ::internal::illegal | |
57 | program_interrupt(processor, cia, | |
58 | illegal_instruction_program_interrupt); | |
59 | return 0; | |
60 | ||
61 | ||
62 | # The following (floating point unavailable) instruction is `known' by gen | |
63 | # and is called when ever an a floating point instruction is to be | |
64 | # executed but floating point is make unavailable by the MSR | |
65 | ::internal::floating_point_unavailable | |
66 | floating_point_unavailable_interrupt(processor, cia); | |
67 | return 0; | |
68 | ||
69 | ||
70 | # | |
71 | # Floating point support functions | |
72 | # | |
73 | ||
74 | # Convert 32bit single to 64bit double | |
75 | unsigned64::function::DOUBLE:unsigned32 WORD | |
76 | unsigned64 FRT; | |
77 | if (EXTRACTED32(WORD, 1, 8) > 0 | |
78 | && EXTRACTED32(WORD, 1, 8) < 255) { | |
79 | /* normalized operand */ | |
80 | int not_word_1_1 = !EXTRACTED32(WORD, 1, 1); /*2.6.3 bug*/ | |
81 | FRT = (INSERTED64(EXTRACTED32(WORD, 0, 1), 0, 1) | |
82 | | INSERTED64(not_word_1_1, 2, 2) | |
83 | | INSERTED64(not_word_1_1, 3, 3) | |
84 | | INSERTED64(not_word_1_1, 4, 4) | |
85 | | INSERTED64(EXTRACTED32(WORD, 2, 31), 5, (63 - 29))); | |
86 | } | |
87 | else if (EXTRACTED32(WORD, 1, 8) == 0 | |
88 | && EXTRACTED32(WORD, 9, 31) != 0) { | |
89 | /* denormalized operand */ | |
90 | int sign = EXTRACTED32(WORD, 0, 0); | |
91 | int exp = -126; | |
92 | unsigned64 frac = INSERTED64(EXTRACTED32(WORD, 9, 31), 1, (52 - 29)); | |
93 | /* normalize the operand */ | |
94 | while (MASKED64(frac, 0, 0) == 0) { | |
95 | frac <<= 1; | |
96 | exp -= 1; | |
97 | } | |
98 | FRT = (INSERTED64(sign, 0, 0) | |
99 | | INSERTED64(exp + 1023, 1, 11) | |
100 | | INSERTED64(EXTRACTED64(frac, 1, 52), 12, 63)); | |
101 | } | |
102 | else if (EXTRACTED32(WORD, 1, 8) == 255 | |
103 | || EXTRACTED32(WORD, 1, 31) == 0) { | |
104 | FRT = (INSERTED64(EXTRACTED32(WORD, 0, 1), 0, 1) | |
105 | | INSERTED64(EXTRACTED32(WORD, 1, 1), 2, 2) | |
106 | | INSERTED64(EXTRACTED32(WORD, 1, 1), 3, 3) | |
107 | | INSERTED64(EXTRACTED32(WORD, 1, 1), 4, 4) | |
108 | | INSERTED64(EXTRACTED32(WORD, 2, 31), 5, (63 - 29))); | |
109 | } | |
110 | else { | |
111 | error("DOUBLE - unknown case\n"); | |
112 | FRT = 0; | |
113 | } | |
114 | return FRT; | |
115 | ||
116 | # Convert 64bit single to 32bit double | |
117 | unsigned32::function::SINGLE:unsigned64 FRS | |
118 | unsigned32 WORD; | |
119 | if (EXTRACTED64(FRS, 1, 11) > 896 | |
120 | || EXTRACTED64(FRS, 1, 63) == 0) { | |
121 | /* no denormalization required (includes Zero/Infinity/NaN) */ | |
122 | WORD = (INSERTED32(EXTRACTED64(FRS, 0, 1), 0, 1) | |
123 | | INSERTED32(EXTRACTED64(FRS, 5, 34), 2, 31)); | |
124 | } | |
125 | else if (874 <= EXTRACTED64(FRS, 1, 11) | |
126 | && EXTRACTED64(FRS, 1, 11) <= 896) { | |
127 | /* denormalization required */ | |
128 | int sign = EXTRACTED64(FRS, 0, 0); | |
129 | int exp = EXTRACTED64(FRS, 1, 11) - 1023; | |
130 | unsigned64 frac = (BIT64(0) | |
131 | | INSERTED64(EXTRACTED64(FRS, 12, 63), 1, 52)); | |
132 | /* denormalize the operand */ | |
133 | while (exp < -126) { | |
134 | frac = INSERTED64(EXTRACTED64(frac, 0, 62), 1, 63); | |
135 | exp += 1; | |
136 | } | |
137 | WORD = (INSERTED32(sign, 0, 0) | |
138 | | INSERTED32(0x00, 1, 8) | |
139 | | INSERTED32(EXTRACTED64(frac, 1, 23), 9, 31)); | |
140 | } | |
141 | else { | |
142 | WORD = 0x0; /* ??? */ | |
143 | } | |
144 | return WORD; | |
145 | ||
146 | ||
147 | # round 64bit double to 64bit but single | |
148 | void::function::Round_Single:cpu *processor, int sign, int *exp, unsigned64 *frac_grx | |
149 | /* comparisons ignore u bits */ | |
150 | unsigned64 out; | |
151 | int inc = 0; | |
152 | int lsb = EXTRACTED64(*frac_grx, 23, 23); | |
153 | int gbit = EXTRACTED64(*frac_grx, 24, 24); | |
154 | int rbit = EXTRACTED64(*frac_grx, 25, 25); | |
155 | int xbit = EXTRACTED64(*frac_grx, 26, 55) != 0; | |
156 | if ((FPSCR & fpscr_rn) == fpscr_rn_round_to_nearest) { | |
157 | if (lsb == 1 && gbit == 1) inc = 1; | |
158 | if (lsb == 0 && gbit == 1 && rbit == 1) inc = 1; | |
159 | if (lsb == 0 && gbit == 1 && xbit == 1) inc = 1; | |
160 | } | |
161 | if ((FPSCR & fpscr_rn) == fpscr_rn_round_towards_pos_infinity) { | |
162 | if (sign == 0 && gbit == 1) inc = 1; | |
163 | if (sign == 0 && rbit == 1) inc = 1; | |
164 | if (sign == 0 && xbit == 1) inc = 1; | |
165 | } | |
166 | if ((FPSCR & fpscr_rn) == fpscr_rn_round_towards_neg_infinity) { | |
167 | if (sign == 1 && gbit == 1) inc = 1; | |
168 | if (sign == 1 && rbit == 1) inc = 1; | |
169 | if (sign == 1 && xbit == 1) inc = 1; | |
170 | } | |
171 | /* work out addition in low 25 bits of out */ | |
172 | out = EXTRACTED64(*frac_grx, 0, 23) + inc; | |
173 | *frac_grx = INSERTED64(out, 0, 23); | |
174 | if (out & BIT64(64 - 23 - 1 - 1)) { | |
175 | *frac_grx = (BIT64(0) | | |
176 | INSERTED64(EXTRACTED64(*frac_grx, 0, 22), 1, 23)); | |
177 | *exp = *exp + 1; | |
178 | } | |
179 | /* frac_grx[24:52] = 0 already */ | |
180 | FPSCR_SET_FR(inc); | |
181 | FPSCR_SET_FI(gbit || rbit || xbit); | |
182 | ||
183 | ||
184 | # | |
185 | void::function::Round_Integer:cpu *processor, int sign, unsigned64 *frac, int *frac64, int gbit, int rbit, int xbit, fpscreg round_mode | |
186 | int inc = 0; | |
187 | if (round_mode == fpscr_rn_round_to_nearest) { | |
188 | if (*frac64 == 1 && gbit == 1) inc = 1; | |
189 | if (*frac64 == 0 && gbit == 1 && rbit == 1) inc = 1; | |
190 | if (*frac64 == 0 && gbit == 1 && xbit == 1) inc = 1; | |
191 | } | |
192 | if (round_mode == fpscr_rn_round_towards_pos_infinity) { | |
193 | if (sign == 0 && gbit == 1) inc = 1; | |
194 | if (sign == 0 && rbit == 1) inc = 1; | |
195 | if (sign == 0 && xbit == 1) inc = 1; | |
196 | } | |
197 | if (round_mode == fpscr_rn_round_towards_neg_infinity) { | |
198 | if (sign == 1 && gbit == 1) inc = 1; | |
199 | if (sign == 1 && rbit == 1) inc = 1; | |
200 | if (sign == 1 && xbit == 1) inc = 1; | |
201 | } | |
202 | /* frac[0:64] = frac[0:64} + inc */ | |
203 | *frac += (*frac64 && inc ? 1 : 0); | |
204 | *frac64 = (*frac64 + inc) & 0x1; | |
205 | FPSCR_SET_FR(inc); | |
206 | FPSCR_SET_FI(gbit | rbit | xbit); | |
207 | ||
208 | ||
209 | void::function::Round_Float:cpu *processor, int sign, int *exp, unsigned64 *frac, fpscreg round_mode | |
210 | int carry_out; | |
211 | int inc = 0; | |
212 | int lsb = EXTRACTED64(*frac, 52, 52); | |
213 | int gbit = EXTRACTED64(*frac, 53, 53); | |
214 | int rbit = EXTRACTED64(*frac, 54, 54); | |
215 | int xbit = EXTRACTED64(*frac, 55, 55); | |
216 | if (round_mode == fpscr_rn_round_to_nearest) { | |
217 | if (lsb == 1 && gbit == 1) inc = 1; | |
218 | if (lsb == 0 && gbit == 1 && rbit == 1) inc = 1; | |
219 | if (lsb == 0 && gbit == 1 && xbit == 1) inc = 1; | |
220 | } | |
221 | if (round_mode == fpscr_rn_round_towards_pos_infinity) { | |
222 | if (sign == 0 && gbit == 1) inc = 1; | |
223 | if (sign == 0 && rbit == 1) inc = 1; | |
224 | if (sign == 0 && xbit == 1) inc = 1; | |
225 | } | |
226 | if (round_mode == fpscr_rn_round_towards_neg_infinity) { | |
227 | if (sign == 1 && gbit == 1) inc = 1; | |
228 | if (sign == 1 && rbit == 1) inc = 1; | |
229 | if (sign == 1 && xbit == 1) inc = 1; | |
230 | } | |
231 | /* frac//carry_out = frac + inc */ | |
232 | *frac = (*frac >> 1) + (INSERTED64(inc, 52, 52) >> 1); | |
233 | carry_out = EXTRACTED64(*frac, 0, 0); | |
234 | *frac <<= 1; | |
235 | if (carry_out == 1) *exp = *exp + 1; | |
236 | FPSCR_SET_FR(inc); | |
237 | FPSCR_SET_FI(gbit | rbit | xbit); | |
238 | FPSCR_SET_XX(FPSCR & fpscr_fi); | |
239 | ||
240 | ||
241 | # conversion of FP to integer | |
242 | void::function::convert_to_integer:cpu *processor, unsigned_word cia, unsigned64 *frt, unsigned64 frb, fpscreg round_mode, int tgt_precision | |
243 | int i; | |
244 | int exp = 0; | |
245 | unsigned64 frac = 0; | |
246 | int frac64 = 0; | |
247 | int gbit = 0; | |
248 | int rbit = 0; | |
249 | int xbit = 0; | |
250 | int sign = EXTRACTED64(frb, 0, 0); | |
251 | if (EXTRACTED64(frb, 1, 11) == 2047 && EXTRACTED64(frb, 12, 63) == 0) | |
252 | goto Infinity_Operand; | |
253 | if (EXTRACTED64(frb, 1, 11) == 2047 && EXTRACTED64(frb, 12, 12) == 0) | |
254 | goto SNaN_Operand; | |
255 | if (EXTRACTED64(frb, 1, 11) == 2047 && EXTRACTED64(frb, 12, 12) == 1) | |
256 | goto QNaN_Operand; | |
257 | if (EXTRACTED64(frb, 1, 11) > 1086) goto Large_Operand; | |
258 | if (EXTRACTED64(frb, 1, 11) > 0) exp = EXTRACTED64(frb, 1, 11) - 1023; | |
259 | if (EXTRACTED64(frb, 1, 11) == 0) exp = -1022; | |
260 | if (EXTRACTED64(frb, 1, 11) > 0) { /* normal */ | |
261 | frac = BIT64(1) | INSERTED64(EXTRACTED64(frb, 12, 63), 2, 53); | |
262 | frac64 = 0; | |
263 | } | |
264 | if (EXTRACTED64(frb, 1, 11) == 0) { /* denorm */ | |
265 | frac = INSERTED64(EXTRACTED64(frb, 12, 63), 2, 53); | |
266 | frac64 = 0; | |
267 | } | |
268 | gbit = 0, rbit = 0, xbit = 0; | |
269 | for (i = 1; i <= 63 - exp; i++) { | |
270 | xbit = rbit | xbit; | |
271 | rbit = gbit; | |
272 | gbit = frac64; | |
273 | frac64 = EXTRACTED64(frac, 63, 63); | |
274 | frac = INSERTED64(EXTRACTED64(frac, 0, 62), 1, 63); | |
275 | } | |
276 | Round_Integer(processor, sign, &frac, &frac64, gbit, rbit, xbit, round_mode); | |
277 | if (sign == 1) { /* frac[0:64] = ~frac[0:64] + 1 */ | |
278 | frac = ~frac; | |
279 | frac64 ^= 1; | |
280 | frac += (frac64 ? 1 : 0); | |
281 | frac64 = (frac64 + 1) & 0x1; | |
282 | } | |
283 | if (tgt_precision == 32 /* can ignore frac64 in compare */ | |
284 | && (signed64)frac > (signed64)MASK64(33+1, 63)/*2^31-1 >>1*/) | |
285 | goto Large_Operand; | |
286 | if (tgt_precision == 64 /* can ignore frac64 in compare */ | |
287 | && (signed64)frac > (signed64)MASK64(1+1, 63)/*2^63-1 >>1*/) | |
288 | goto Large_Operand; | |
289 | if (tgt_precision == 32 /* can ignore frac64 in compare */ | |
290 | && (signed64)frac < (signed64)MASK64(0, 32+1)/*-2^31 >>1*/) | |
291 | goto Large_Operand; | |
292 | if (tgt_precision == 64 /* can ignore frac64 in compare */ | |
293 | && (signed64)frac < (signed64)MASK64(0, 0+1)/*-2^63 >>1*/) | |
294 | goto Large_Operand; | |
295 | FPSCR_SET_XX(FPSCR & fpscr_fi); | |
296 | if (tgt_precision == 32) | |
297 | *frt = MASKED64(*frt, 0, 31) | (EXTRACTED64(frac, 33, 63) << 1) | frac64; | |
298 | if (tgt_precision == 64) | |
299 | *frt = (EXTRACTED64(frac, 1, 63) << 1) | frac64; | |
300 | /*FPSCR[fprf] = undefined */ | |
301 | goto Done; | |
302 | /**/ | |
303 | Infinity_Operand: | |
304 | FPSCR_SET_FR(0); | |
305 | FPSCR_SET_FI(0); | |
306 | FPSCR_OR_VX(fpscr_vxcvi); | |
307 | if ((FPSCR & fpscr_ve) == 0) { | |
308 | if (tgt_precision == 32) { | |
309 | if (sign == 0) *frt = MASKED64(*frt, 0, 31) | 0x7FFFFFFF; | |
310 | if (sign == 1) *frt = MASKED64(*frt, 0, 31) | 0x80000000; | |
311 | } | |
312 | else { | |
313 | if (sign == 0) *frt = MASK64(1, 63); /*0x7FFF_FFFF_FFFF_FFFF*/ | |
314 | if (sign == 1) *frt = BIT64(0); /*0x8000_0000_0000_0000*/ | |
315 | } | |
316 | /* FPSCR[FPRF] = undefined */ | |
317 | } | |
318 | goto Done; | |
319 | /**/ | |
320 | SNaN_Operand: | |
321 | FPSCR_SET_FR(0); | |
322 | FPSCR_SET_FI(0); | |
323 | FPSCR_OR_VX(fpscr_vxsnan | fpscr_vxcvi); | |
324 | if ((FPSCR & fpscr_ve) == 0) { | |
325 | if (tgt_precision == 32) *frt = MASKED64(*frt, 0, 31) | 0x80000000; | |
326 | if (tgt_precision == 64) *frt = BIT64(0); /*0x8000_0000_0000_0000*/ | |
327 | /* FPSCR[fprf] = undefined */ | |
328 | } | |
329 | goto Done; | |
330 | /**/ | |
331 | QNaN_Operand: | |
332 | FPSCR_SET_FR(0); | |
333 | FPSCR_SET_FI(0); | |
334 | FPSCR_OR_VX(fpscr_vxcvi); | |
335 | if ((FPSCR & fpscr_ve) == 0) { | |
336 | if (tgt_precision == 32) *frt = MASKED64(*frt, 0, 31) | 0x80000000; | |
337 | if (tgt_precision == 64) *frt = BIT64(0);/*0x8000_0000_0000_0000*/ | |
338 | /* FPSCR[fprf] = undefined */ | |
339 | } | |
340 | goto Done; | |
341 | /**/ | |
342 | Large_Operand: | |
343 | FPSCR_SET_FR(0); | |
344 | FPSCR_SET_FI(0); | |
345 | FPSCR_OR_VX(fpscr_vxcvi); | |
346 | if ((FPSCR & fpscr_ve) == 0) { | |
347 | if (tgt_precision == 32) { | |
348 | if (sign == 0) *frt = MASKED64(*frt, 0, 31) | 0x7fffffff; | |
349 | if (sign == 1) *frt = MASKED64(*frt, 0, 31) | 0x80000000; | |
350 | } | |
351 | else { | |
352 | if (sign == 0) *frt = MASK64(1, 63); /*0x7FFF_FFFF_FFFF_FFFF*/ | |
353 | if (sign == 1) *frt = BIT64(0); /*0x8000_0000_0000_0000*/ | |
354 | } | |
355 | /* FPSCR[fprf] = undefined */ | |
356 | } | |
357 | /**/ | |
358 | Done: | |
359 | ||
360 | ||
361 | # extract out raw fields of a FP number | |
362 | int::function::sign:unsigned64 FRS | |
363 | return (MASKED64(FRS, 0, 0) | |
364 | ? -1 | |
365 | : 1); | |
366 | int::function::biased_exp:unsigned64 frs, int single | |
367 | if (single) | |
368 | return EXTRACTED64(frs, 1, 8); | |
369 | else | |
370 | return EXTRACTED64(frs, 1, 11); | |
371 | unsigned64::function::fraction:unsigned64 frs, int single | |
372 | if (single) | |
373 | return EXTRACTED64(frs, 9, 31); | |
374 | else | |
375 | return EXTRACTED64(frs, 12, 63); | |
376 | ||
377 | # a number?, each of the below return +1 or -1 (based on sign bit) | |
378 | # if true. | |
379 | int::function::is_nor:unsigned64 frs, int single | |
380 | int exp = biased_exp(frs, single); | |
381 | return (exp >= 1 | |
382 | && exp <= (single ? 254 : 2046)); | |
383 | int::function::is_zero:unsigned64 FRS | |
384 | return (MASKED64(FRS, 1, 63) == 0 | |
385 | ? sign(FRS) | |
386 | : 0); | |
387 | int::function::is_den:unsigned64 frs, int single | |
388 | int exp = biased_exp(frs, single); | |
389 | unsigned64 frac = fraction(frs, single); | |
390 | return (exp == 0 && frac != 0 | |
391 | ? sign(frs) | |
392 | : 0); | |
393 | int::function::is_inf:unsigned64 frs, int single | |
394 | int exp = biased_exp(frs, single); | |
395 | int frac = fraction(frs, single); | |
396 | return (exp == (single ? 255 : 2047) && frac == 0 | |
397 | ? sign(frs) | |
398 | : 0); | |
399 | int::function::is_NaN:unsigned64 frs, int single | |
400 | int exp = biased_exp(frs, single); | |
401 | int frac = fraction(frs, single); | |
402 | return (exp == (single ? 255 : 2047) && frac != 0 | |
403 | ? sign(frs) | |
404 | : 0); | |
405 | int::function::is_SNaN:unsigned64 frs, int single | |
406 | return (is_NaN(frs, single) | |
407 | && !(frs & (single ? MASK64(9, 9) : MASK64(12, 12))) | |
408 | ? sign(frs) | |
409 | : 0); | |
410 | int::function::is_QNaN:unsigned64 frs, int single | |
411 | return (is_NaN(frs, single) && !is_SNaN(frs, single)); | |
412 | int::function::is_less_than:unsigned64 *fra, unsigned64 *frb | |
413 | return *(double*)fra < *(double*)frb; | |
414 | int::function::is_greater_than:unsigned64 *fra, unsigned64 *frb | |
415 | return *(double*)fra > *(double*)frb; | |
416 | int::function::is_equan_to:unsigned64 *fra, unsigned64 *frb | |
417 | return *(double*)fra == *(double*)frb; | |
418 | ||
419 | ||
420 | # which quiet nan should become the result | |
421 | unsigned64::function::select_qnan:unsigned64 fra, unsigned64 frb, unsigned64 frc, int instruction_is_frsp, int generate_qnan, int single | |
422 | unsigned64 frt = 0; | |
423 | if (is_NaN(fra, single)) | |
424 | frt = fra; | |
425 | else if (is_NaN(frb, single)) | |
426 | if (instruction_is_frsp) | |
427 | frt = MASKED64(frb, 0, 34); | |
428 | else | |
429 | frt = frb; | |
430 | else if (is_NaN(frc, single)) | |
431 | frt = frc; | |
432 | else if (generate_qnan) | |
433 | frt = MASK64(1, 12); /* 0x7FF8_0000_0000_0000 */ | |
434 | else | |
435 | error("select_qnan - default reached\n"); | |
436 | return frt; | |
437 | ||
438 | ||
439 | # detect invalid operation | |
440 | int::function::is_invalid_operation:cpu *processor, unsigned_word cia, unsigned64 fra, unsigned64 frb, fpscreg check, int single, int negate | |
441 | int fail = 0; | |
442 | if ((check & fpscr_vxsnan) | |
443 | && (is_SNaN(fra, single) || is_SNaN(frb, single))) { | |
444 | FPSCR_OR_VX(fpscr_vxsnan); | |
445 | fail = 1; | |
446 | } | |
447 | if ((check & fpscr_vxisi) | |
448 | && (is_inf(fra, single) && is_inf(frb, single)) | |
449 | && ((negate && sign(fra) != sign(frb)) | |
450 | || (!negate && sign(fra) == sign(frb)))) { | |
451 | /*FIXME: don't handle inf-inf VS inf+-inf */ | |
452 | FPSCR_OR_VX(fpscr_vxisi); | |
453 | fail = 1; | |
454 | } | |
455 | if ((check & fpscr_vxidi) | |
456 | && (is_inf(fra, single) && is_inf(frb, single))) { | |
457 | FPSCR_OR_VX(fpscr_vxidi); | |
458 | fail = 1; | |
459 | } | |
460 | if ((check & fpscr_vxzdz) | |
461 | && (is_zero(fra) && is_zero(frb))) { | |
462 | FPSCR_OR_VX(fpscr_vxzdz); | |
463 | fail = 1; | |
464 | } | |
465 | if ((check & fpscr_vximz) | |
466 | && (is_zero(fra) && is_inf(frb, single))) { | |
467 | FPSCR_OR_VX(fpscr_vximz); | |
468 | fail = 1; | |
469 | } | |
470 | if ((check & fpscr_vxvc) | |
471 | && (is_NaN(fra, single) || is_NaN(frb, single))) { | |
472 | FPSCR_OR_VX(fpscr_vxvc); | |
473 | fail = 1; | |
474 | } | |
475 | if ((check & fpscr_vxsoft)) { | |
476 | FPSCR_OR_VX(fpscr_vxsoft); | |
477 | fail = 1; | |
478 | } | |
479 | if ((check & fpscr_vxsqrt) | |
480 | && sign(fra) < 0) { | |
481 | FPSCR_OR_VX(fpscr_vxsqrt); | |
482 | fail = 1; | |
483 | } | |
484 | /* if ((check && fpscr_vxcvi) { | |
485 | && (is_inf(fra, single) || is_NaN(fra, single) || is_large(fra, single))) | |
486 | FPSCR_OR_VX(fpscr_vxcvi); | |
487 | fail = 1; | |
488 | } | |
489 | */ | |
490 | return fail; | |
491 | ||
492 | ||
493 | ||
494 | ||
495 | ||
496 | # handle case of invalid operation | |
497 | void::function::invalid_arithemetic_operation:cpu *processor, unsigned_word cia, unsigned64 *frt, unsigned64 fra, unsigned64 frb, unsigned64 frc, int instruction_is_frsp, int instruction_is_convert_to_64bit, int instruction_is_convert_to_32bit, int single | |
498 | if (FPSCR & fpscr_ve) { | |
499 | /* invalid operation exception enabled */ | |
500 | /* FRT unchaged */ | |
501 | FPSCR_SET_FR(0); | |
502 | FPSCR_SET_FI(0); | |
503 | /* fpscr_FPRF unchanged */ | |
504 | } | |
505 | else { | |
506 | /* invalid operation exception disabled */ | |
507 | if (instruction_is_convert_to_64bit) { | |
508 | error("oopsi"); | |
509 | } | |
510 | else if (instruction_is_convert_to_32bit) { | |
511 | error("oopsi"); | |
512 | } | |
513 | else { /* arrith, frsp */ | |
514 | *frt = select_qnan(fra, frb, frc, | |
515 | instruction_is_frsp, 0/*generate*/, single); | |
516 | FPSCR_SET_FR(0); | |
517 | FPSCR_SET_FI(0); | |
518 | FPSCR_SET_FPRF(fpscr_rf_quiet_nan); | |
519 | } | |
520 | } | |
521 | ||
522 | ||
523 | ||
524 | ||
525 | # | |
526 | # I.2.4.1 Branch Instructions | |
527 | # | |
528 | 0.18,6.LI,30.AA,31.LK:I:t::Branch | |
529 | if (AA) NIA = IEA(EXTS(LI_0b00)); | |
530 | else NIA = IEA(CIA + EXTS(LI_0b00)); | |
531 | if (LK) LR = (spreg)CIA+4; | |
532 | 0.16,6.BO,11.BI,16.BD,30.AA,31.LK:B:t::Branch Conditional | |
533 | int M, ctr_ok, cond_ok; | |
534 | if (is_64bit_implementation && is_64bit_mode) M = 0; | |
535 | else M = 32; | |
536 | if (!BO{2}) CTR = CTR - 1; | |
537 | ctr_ok = BO{2} || ((MASKED(CTR, M, 63) != 0) != (BO{3})); | |
538 | cond_ok = BO{0} || ((CR{BI}) == (BO{1})); | |
539 | if (ctr_ok && cond_ok) | |
540 | if (AA) NIA = IEA(EXTS(BD_0b00)); | |
541 | else NIA = IEA(CIA + EXTS(BD_0b00)); | |
542 | if (LK) LR = (spreg)IEA(CIA + 4); | |
543 | 0.19,6.BO,11.BI,16./,21.16,31.LK:XL:t::Branch Conditional to Link Register | |
544 | int M, ctr_ok, cond_ok; | |
545 | if (is_64bit_implementation && is_64bit_mode) M = 0; | |
546 | else M = 32; | |
547 | if (!BO{2}) CTR = CTR - 1; | |
548 | ctr_ok = BO{2} || ((MASKED(CTR, M, 63) != 0) != BO{3}); | |
549 | cond_ok = BO{0} || (CR{BI} == BO{1}); | |
550 | if (ctr_ok && cond_ok) NIA = IEA(LR_0b00); | |
551 | if (LK) LR = (spreg)IEA(CIA + 4); | |
552 | 0.19,6.BO,11.BI,16./,21.528,31.LK:XL:t::Branch Conditional to Count Register | |
553 | int cond_ok; | |
554 | cond_ok = BO{0} || (CR{BI} == BO{1}); | |
555 | if (cond_ok) NIA = IEA(CTR_0b00); | |
556 | if (LK) LR = (spreg)IEA(CIA + 4); | |
557 | ||
558 | # | |
559 | # I.2.4.2 System Call Instruction | |
560 | # | |
561 | 0.17,6./,11./,16./,30.1,31./:SC:t::System Call | |
562 | system_call_interrupt(processor, cia); | |
563 | ||
564 | # | |
565 | # I.2.4.3 Condition Register Logical Instructions | |
566 | # | |
567 | 0.19,6.BT,11.BA,16.BB,21.257,31./:XL::crand:Condition Register AND | |
568 | BLIT32(CR, BT, CR{BA} && CR{BB}); | |
569 | 0.19,6.BT,11.BA,16.BB,21.449,31./:XL::cror:Condition Register OR | |
570 | BLIT32(CR, BT, CR{BA} || CR{BB}); | |
571 | 0.19,6.BT,11.BA,16.BB,21.193,31./:XL::crxor:Condition Register XOR | |
572 | BLIT32(CR, BT, CR{BA} != CR{BB}); | |
573 | 0.19,6.BT,11.BA,16.BB,21.225,31./:XL::crnand:Condition Register NAND | |
574 | BLIT32(CR, BT, !(CR{BA} && CR{BB})); | |
575 | 0.19,6.BT,11.BA,16.BB,21.33,31./:XL::crnor:Condition Register NOR | |
576 | BLIT32(CR, BT, !(CR{BA} || CR{BB})); | |
577 | 0.19,6.BT,11.BA,16.BB,21.289,31./:XL::creqv:Condition Register Equivalent | |
578 | BLIT32(CR, BT, CR{BA} == CR{BB}); | |
579 | 0.19,6.BT,11.BA,16.BB,21.129,31./:XL::crandc:Condition Register AND with Complement | |
580 | BLIT32(CR, BT, CR{BA} && !CR{BB}); | |
581 | 0.19,6.BT,11.BA,16.BB,21.417,31./:XL::crorc:Condition Register OR with Complement | |
582 | BLIT32(CR, BT, CR{BA} || !CR{BB}); | |
583 | ||
584 | # | |
585 | # I.2.4.4 Condition Register Field Instruction | |
586 | # | |
587 | 0.19,6.BF,9./,11.BFA,14./,16./,21.0,31./:XL:::Move Condition Register Field | |
588 | MBLIT32(CR, 4*BF, 4*BF+3, EXTRACTED32(CR, 4*BFA, 4*BFA+3)); | |
589 | ||
590 | ||
591 | # | |
592 | # I.3.3.2 Fixed-Point Load Instructions | |
593 | # | |
594 | ||
595 | 0.34,6.RT,11.RA,16.D:D:::Load Byte and Zero | |
596 | unsigned_word b; | |
597 | unsigned_word EA; | |
598 | if (RA == 0) b = 0; | |
599 | else b = *rA; | |
600 | EA = b + EXTS(D); | |
601 | *rT = MEM(unsigned, EA, 1); | |
602 | 0.31,6.RT,11.RA,16.RB,21.87,31./:X:::Load Byte and Zero Indexed | |
603 | unsigned_word b; | |
604 | unsigned_word EA; | |
605 | if (RA == 0) b = 0; | |
606 | else b = *rA; | |
607 | EA = b + *rB; | |
608 | *rT = MEM(unsigned, EA, 1); | |
609 | 0.35,6.RT,11.RA,16.D:D:::Load Byte and Zero with Update | |
610 | unsigned_word EA; | |
611 | if (RA == 0 || RA == RT) | |
612 | program_interrupt(processor, cia, | |
613 | illegal_instruction_program_interrupt); | |
614 | EA = *rA + EXTS(D); | |
615 | *rT = MEM(unsigned, EA, 1); | |
616 | *rA = EA; | |
617 | 0.31,6.RT,11.RA,16.RB,21.119,31./:X:::Load Byte and Zero with Update Indexed | |
618 | unsigned_word EA; | |
619 | if (RA == 0 || RA == RT) | |
620 | program_interrupt(processor, cia, | |
621 | illegal_instruction_program_interrupt); | |
622 | EA = *rA + *rB; | |
623 | *rT = MEM(unsigned, EA, 1); | |
624 | *rA = EA; | |
625 | ||
626 | 0.40,6.RT,11.RA,16.D:D:::Load Halfword and Zero | |
627 | unsigned_word b; | |
628 | unsigned_word EA; | |
629 | if (RA == 0) b = 0; | |
630 | else b = *rA; | |
631 | EA = b + EXTS(D); | |
632 | *rT = MEM(unsigned, EA, 2); | |
633 | 0.31,6.RT,11.RA,16.RB,21.279,31./:X:::Load Halfword and Zero Indexed | |
634 | unsigned_word b; | |
635 | unsigned_word EA; | |
636 | if (RA == 0) b = 0; | |
637 | else b = *rA; | |
638 | EA = b + *rB; | |
639 | *rT = MEM(unsigned, EA, 2); | |
640 | 0.41,6.RT,11.RA,16.D:D:::Load Halfword and Zero with Update | |
641 | unsigned_word EA; | |
642 | if (RA == 0 || RA == RT) | |
643 | program_interrupt(processor, cia, | |
644 | illegal_instruction_program_interrupt); | |
645 | EA = *rA + EXTS(D); | |
646 | *rT = MEM(unsigned, EA, 2); | |
647 | *rA = EA; | |
648 | 0.31,6.RT,11.RA,16.RB,21.311,31./:X:::Load Halfword and Zero with Update Indexed | |
649 | unsigned_word EA; | |
650 | if (RA == 0 || RA == RT) | |
651 | program_interrupt(processor, cia, | |
652 | illegal_instruction_program_interrupt); | |
653 | EA = *rA + *rB; | |
654 | *rT = MEM(unsigned, EA, 2); | |
655 | *rA = EA; | |
656 | ||
657 | 0.42,6.RT,11.RA,16.D:D:::Load Halfword Algebraic | |
658 | unsigned_word b; | |
659 | unsigned_word EA; | |
660 | if (RA == 0) b = 0; | |
661 | else b = *rA; | |
662 | EA = b + EXTS(D); | |
663 | *rT = MEM(signed, EA, 2); | |
664 | 0.31,6.RT,11.RA,16.RB,21.343,31./:X:::Load Halfword Algebraic Indexed | |
665 | unsigned_word b; | |
666 | unsigned_word EA; | |
667 | if (RA == 0) b = 0; | |
668 | else b = *rA; | |
669 | EA = b + *rB; | |
670 | *rT = MEM(signed, EA, 2); | |
671 | 0.43,6.RT,11.RA,16.D:D:::Load Halfword Algebraic with Update | |
672 | unsigned_word EA; | |
673 | if (RA == 0 || RA == RT) | |
674 | program_interrupt(processor, cia, | |
675 | illegal_instruction_program_interrupt); | |
676 | EA = *rA + EXTS(D); | |
677 | *rT = MEM(signed, EA, 2); | |
678 | 0.31,6.RT,11.RA,16.RB,21.375,31./:X:::Load Halfword Algebraic with Update Indexed | |
679 | unsigned_word EA; | |
680 | if (RA == 0 || RA == RT) | |
681 | program_interrupt(processor, cia, | |
682 | illegal_instruction_program_interrupt); | |
683 | EA = *rA + *rB; | |
684 | *rT = MEM(signed, EA, 2); | |
685 | *rA = EA; | |
686 | ||
687 | 0.32,6.RT,11.RA,16.D:D:::Load Word and Zero | |
688 | unsigned_word b; | |
689 | unsigned_word EA; | |
690 | if (RA == 0) b = 0; | |
691 | else b = *rA; | |
692 | EA = b + EXTS(D); | |
693 | *rT = MEM(unsigned, EA, 4); | |
694 | 0.31,6.RT,11.RA,16.RB,21.23,31./:X:::Load Word and Zero Indexed | |
695 | unsigned_word b; | |
696 | unsigned_word EA; | |
697 | if (RA == 0) b = 0; | |
698 | else b = *rA; | |
699 | EA = b + *rB; | |
700 | *rT = MEM(unsigned, EA, 4); | |
701 | 0.33,6.RT,11.RA,16.D:D:::Load Word and Zero with Update | |
702 | unsigned_word EA; | |
703 | if (RA == 0 || RA == RT) | |
704 | program_interrupt(processor, cia, | |
705 | illegal_instruction_program_interrupt); | |
706 | EA = *rA + EXTS(D); | |
707 | *rT = MEM(unsigned, EA, 4); | |
708 | *rA = EA; | |
709 | 0.31,6.RT,11.RA,16.RB,21.55,31./:X:::Load Word and Zero with Update Indexed | |
710 | unsigned_word EA; | |
711 | if (RA == 0 || RA == RT) | |
712 | program_interrupt(processor, cia, | |
713 | illegal_instruction_program_interrupt); | |
714 | EA = *rA + *rB; | |
715 | *rT = MEM(unsigned, EA, 4); | |
716 | *rA = EA; | |
717 | ||
718 | 0.58,6.RT,11.RA,16.DS,30.2:DS:64::Load Word Algebraic | |
719 | # unsigned_word b; | |
720 | # unsigned_word EA; | |
721 | # if (RA == 0) b = 0; | |
722 | # else b = *rA; | |
723 | # EA = b + EXTS(DS_0b00); | |
724 | # *rT = MEM(signed, EA, 4); | |
725 | 0.31,6.RT,11.RA,16.RB,21.341,31./:X:64::Load Word Algebraic Indexed | |
726 | # unsigned_word b; | |
727 | # unsigned_word EA; | |
728 | # if (RA == 0) b = 0; | |
729 | # else b = *rA; | |
730 | # EA = b + *rB;; | |
731 | # *rT = MEM(signed, EA, 4); | |
732 | 0.31,6.RT,11.RA,16.RB,21.373,31./:X:64::Load Word Algebraic with Update Indexed | |
733 | # unsigned_word EA; | |
734 | # if (RA == 0 || RA == RT) | |
735 | # program_interrupt(processor, cia | |
736 | # illegal_instruction_program_interrupt); | |
737 | # EA = *rA + *rB; | |
738 | # *rT = MEM(signed, EA, 4); | |
739 | # *rA = EA; | |
740 | ||
741 | 0.58,6.RT,11.RA,16.DS,30.0:DS:64::Load Doubleword | |
742 | # unsigned_word b; | |
743 | # unsigned_word EA; | |
744 | # if (RA == 0) b = 0; | |
745 | # else b = *rA; | |
746 | # EA = b + EXTS(DS_0b00); | |
747 | # *rT = MEM(unsigned, EA, 8); | |
748 | 0.31,6.RT,11.RA,16.RB,21.21,31./:X:64::Load Doubleword Indexed | |
749 | # unsigned_word b; | |
750 | # unsigned_word EA; | |
751 | # if (RA == 0) b = 0; | |
752 | # else b = *rA; | |
753 | # EA = b + *rB; | |
754 | # *rT = MEM(unsigned, EA, 8); | |
755 | 0.58,6.RT,11.RA,16.DS,30.1:DS:64::Load Doubleword with Update | |
756 | # unsigned_word EA; | |
757 | # if (RA == 0 || RA == RT) | |
758 | # program_interrupt(processor, cia | |
759 | # illegal_instruction_program_interrupt); | |
760 | # EA = *rA + EXTS(DS_0b00); | |
761 | # *rT = MEM(unsigned, EA, 8); | |
762 | # *rA = EA; | |
763 | 0.31,6.RT,11.RA,16.RB,21.53,31./:DS:64::Load Doubleword with Update Indexed | |
764 | # unsigned_word EA; | |
765 | # if (RA == 0 || RA == RT) | |
766 | # program_interrupt(processor, cia | |
767 | # illegal_instruction_program_interrupt); | |
768 | # EA = *rA + *rB; | |
769 | # *rT = MEM(unsigned, EA, 8); | |
770 | # *rA = EA; | |
771 | ||
772 | ||
773 | ||
774 | # | |
775 | # I.3.3.3 Fixed-Point Store Instructions | |
776 | # | |
777 | ||
778 | 0.38,6.RS,11.RA,16.D:D:::Store Byte | |
779 | unsigned_word b; | |
780 | unsigned_word EA; | |
781 | if (RA == 0) b = 0; | |
782 | else b = *rA; | |
783 | EA = b + EXTS(D); | |
784 | STORE(EA, 1, *rS); | |
785 | 0.31,6.RS,11.RA,16.RB,21.215,31./:X:::Store Byte Indexed | |
786 | unsigned_word b; | |
787 | unsigned_word EA; | |
788 | if (RA == 0) b = 0; | |
789 | else b = *rA; | |
790 | EA = b + *rB; | |
791 | STORE(EA, 1, *rS); | |
792 | 0.39,6.RS,11.RA,16.D:D:::Store Byte with Update | |
793 | unsigned_word EA; | |
794 | if (RA == 0) | |
795 | program_interrupt(processor, cia, | |
796 | illegal_instruction_program_interrupt); | |
797 | EA = *rA + EXTS(D); | |
798 | STORE(EA, 1, *rS); | |
799 | *rA = EA; | |
800 | 0.31,6.RS,11.RA,16.RB,21.247,31./:X:::Store Byte with Update Indexed | |
801 | unsigned_word EA; | |
802 | if (RA == 0) | |
803 | program_interrupt(processor, cia, | |
804 | illegal_instruction_program_interrupt); | |
805 | EA = *rA + *rB; | |
806 | STORE(EA, 1, *rS); | |
807 | *rA = EA; | |
808 | ||
809 | 0.44,6.RS,11.RA,16.D:D:::Store Half Word | |
810 | unsigned_word b; | |
811 | unsigned_word EA; | |
812 | if (RA == 0) b = 0; | |
813 | else b = *rA; | |
814 | EA = b + EXTS(D); | |
815 | STORE(EA, 2, *rS); | |
816 | 0.31,6.RS,11.RA,16.RB,21.407,31./:X:::Store Half Word Indexed | |
817 | unsigned_word b; | |
818 | unsigned_word EA; | |
819 | if (RA == 0) b = 0; | |
820 | else b = *rA; | |
821 | EA = b + *rB; | |
822 | STORE(EA, 2, *rS); | |
823 | 0.45,6.RS,11.RA,16.D:D:::Store Half Word with Update | |
824 | unsigned_word EA; | |
825 | if (RA == 0) | |
826 | program_interrupt(processor, cia, | |
827 | illegal_instruction_program_interrupt); | |
828 | EA = *rA + EXTS(D); | |
829 | STORE(EA, 2, *rS); | |
830 | *rA = EA; | |
831 | 0.31,6.RS,11.RA,16.RB,21.439,31./:X:::Store Half Word with Update Indexed | |
832 | unsigned_word EA; | |
833 | if (RA == 0) | |
834 | program_interrupt(processor, cia, | |
835 | illegal_instruction_program_interrupt); | |
836 | EA = *rA + *rB; | |
837 | STORE(EA, 2, *rS); | |
838 | *rA = EA; | |
839 | ||
840 | 0.36,6.RS,11.RA,16.D:D:::Store Word | |
841 | unsigned_word b; | |
842 | unsigned_word EA; | |
843 | if (RA == 0) b = 0; | |
844 | else b = *rA; | |
845 | EA = b + EXTS(D); | |
846 | STORE(EA, 4, *rS); | |
847 | 0.31,6.RS,11.RA,16.RB,21.151,31./:X:::Store Word Indexed | |
848 | unsigned_word b; | |
849 | unsigned_word EA; | |
850 | if (RA == 0) b = 0; | |
851 | else b = *rA; | |
852 | EA = b + *rB; | |
853 | STORE(EA, 4, *rS); | |
854 | 0.37,6.RS,11.RA,16.D:D:::Store Word with Update | |
855 | unsigned_word EA; | |
856 | if (RA == 0) | |
857 | program_interrupt(processor, cia, | |
858 | illegal_instruction_program_interrupt); | |
859 | EA = *rA + EXTS(D); | |
860 | STORE(EA, 4, *rS); | |
861 | *rA = EA; | |
862 | 0.31,6.RS,11.RA,16.RB,21.183,31./:X:::Store Word with Update Indexed | |
863 | unsigned_word EA; | |
864 | if (RA == 0) | |
865 | program_interrupt(processor, cia, | |
866 | illegal_instruction_program_interrupt); | |
867 | EA = *rA + *rB; | |
868 | STORE(EA, 4, *rS); | |
869 | *rA = EA; | |
870 | ||
871 | 0.62,6.RS,11.RA,16.DS,30.0:DS:64::Store Doubleword | |
872 | # unsigned_word b; | |
873 | # unsigned_word EA; | |
874 | # if (RA == 0) b = 0; | |
875 | # else b = *rA; | |
876 | # EA = b + EXTS(DS_0b00); | |
877 | # STORE(EA, 8, *rS); | |
878 | 0.31,6.RS,11.RA,16.RB,21.149,31./:X:64::Store Doubleword Indexed | |
879 | # unsigned_word b; | |
880 | # unsigned_word EA; | |
881 | # if (RA == 0) b = 0; | |
882 | # else b = *rA; | |
883 | # EA = b + *rB; | |
884 | # STORE(EA, 8, *rS); | |
885 | 0.62,6.RS,11.RA,16.DS,30.1:DS:64::Store Doubleword with Update | |
886 | # unsigned_word EA; | |
887 | # if (RA == 0) | |
888 | # program_interrupt(processor, cia | |
889 | # illegal_instruction_program_interrupt); | |
890 | # EA = *rA + EXTS(DS_0b00); | |
891 | # STORE(EA, 8, *rS); | |
892 | # *rA = EA; | |
893 | 0.31,6.RS,11.RA,16.RB,21.181,31./:X:64::Store Doubleword with Update Indexed | |
894 | # unsigned_word EA; | |
895 | # if (RA == 0) | |
896 | # program_interrupt(processor, cia | |
897 | # illegal_instruction_program_interrupt); | |
898 | # EA = *rA + *rB; | |
899 | # STORE(EA, 8, *rS); | |
900 | # *rA = EA; | |
901 | ||
902 | ||
903 | # | |
904 | # I.3.3.4 Fixed-Point Load and Store with Byte Reversal Instructions | |
905 | # | |
906 | ||
907 | 0.31,6.RT,11.RA,16.RB,21.790,31./:X:::Load Halfword Byte-Reverse Indexed | |
908 | # unsigned_word b; | |
909 | # unsigned_word EA; | |
910 | # if (RA == 0) b = 0; | |
911 | # else b = *rA; | |
912 | # EA = b + *rB; | |
913 | # *rT = SWAP2(MEM(unsigned, EA, 2)); | |
914 | 0.31,6.RT,11.RA,16.RB,21.534,31./:X:::Load Word Byte-Reverse Indexed | |
915 | # unsigned_word b; | |
916 | # unsigned_word EA; | |
917 | # if (RA == 0) b = 0; | |
918 | # else b = *rA; | |
919 | # EA = b + *rB; | |
920 | # *rT = SWAP4(MEM(unsigned, EA, 4)); | |
921 | ||
922 | 0.31,6.RS,11.RA,16.RB,21.918,31./:X:::Store Half Word Byte-Reversed Indexed | |
923 | # unsigned_word b; | |
924 | # unsigned_word EA; | |
925 | # if (RA == 0) b = 0; | |
926 | # else b = *rA; | |
927 | # EA = b + *rB; | |
928 | # STORE(EA, 2, SWAP2(*rS)); | |
929 | 0.31,6.RS,11.RA,16.RB,21.662,31./:X:::Store Word Byte-Reversed Indexed | |
930 | # unsigned_word b; | |
931 | # unsigned_word EA; | |
932 | # if (RA == 0) b = 0; | |
933 | # else b = *rA; | |
934 | # EA = b + *rB; | |
935 | # STORE(EA, 4, SWAP4(*rS)); | |
936 | ||
937 | ||
938 | # | |
939 | # I.3.3.5 Fixed-Point Load and Store Multiple Instrctions | |
940 | # | |
941 | ||
942 | 0.46,6.RT,11.RA,16.D:D:be::Load Multiple Word | |
943 | 0.47,6.RS,11.RA,16.D:D:be::Store Multiple Word | |
944 | ||
945 | ||
946 | # | |
947 | # I.3.3.6 Fixed-Point Move Assist Instructions | |
948 | # | |
949 | ||
950 | 0.31,6.RT,11.RA,16.NB,21.597,31./:X:be::Load String Word Immediate | |
951 | 0.31,6.RT,11.RA,16.RB,21.533,31./:X:be::Load String Word Indexed | |
952 | ||
953 | 0.31,6.RS,11.RA,16.NB,21.725,31./:X:be::Store String Word Immedate | |
954 | 0.31,6.RS,11.RA,16.RB,21.661,31./:X:be::Store String Word Indexed | |
955 | ||
956 | ||
957 | # | |
958 | # I.3.3.7 Storage Synchronization Instructions | |
959 | # | |
960 | # HACK: Rather than monitor addresses looking for a reason | |
961 | # to cancel a reservation. This code instead keeps | |
962 | # a copy of the data read from memory. Before performing | |
963 | # a store, the memory area is checked to see if it has | |
964 | # been changed. | |
965 | 0.31,6.RT,11.RA,16.RB,21.20,31./:X:::Load Word And Reserve Indexed | |
966 | unsigned_word b; | |
967 | unsigned_word EA; | |
968 | if (RA == 0) b = 0; | |
969 | else b = *rA; | |
970 | EA = b + *rB; | |
971 | RESERVE = 1; | |
972 | RESERVE_ADDR = real_addr(EA, 1/*is-read?*/); | |
973 | RESERVE_DATA = MEM(unsigned, EA, 4); | |
974 | *rT = RESERVE_DATA; | |
975 | 0.31,6.RT,11.RA,16.RB,21.84,31./:X:64::Load Doubleword And Reserve Indexed | |
976 | unsigned_word b; | |
977 | unsigned_word EA; | |
978 | if (RA == 0) b = 0; | |
979 | else b = *rA; | |
980 | EA = b + *rB; | |
981 | RESERVE = 1; | |
982 | RESERVE_ADDR = real_addr(EA, 1/*is-read?*/); | |
983 | RESERVE_DATA = MEM(unsigned, EA, 8); | |
984 | *rT = RESERVE_DATA; | |
985 | ||
986 | 0.31,6.RS,11.RA,16.RB,21.150,31.1:X:::Store Word Conditional Indexed | |
987 | unsigned_word b; | |
988 | unsigned_word EA; | |
989 | if (RA == 0) b = 0; | |
990 | else b = *rA; | |
991 | EA = b + *rB; | |
992 | if (RESERVE) { | |
993 | if (RESERVE_ADDR == real_addr(EA, 0/*is-read?*/) | |
994 | && /*HACK*/ RESERVE_DATA == MEM(unsigned, EA, 4)) { | |
995 | STORE(EA, 4, *rS); | |
996 | CR_SET_XER_SO(0, cr_i_zero); | |
997 | } | |
998 | else { | |
999 | /* ment to randomly to store, we never do! */ | |
1000 | CR_SET_XER_SO(0, 0); | |
1001 | } | |
1002 | RESERVE = 0; | |
1003 | } | |
1004 | else { | |
1005 | CR_SET_XER_SO(0, 0); | |
1006 | } | |
1007 | 0.31,6.RS,11.RA,16.RB,21.214,31.1:X:64::Store Doubleword Conditional Indexed | |
1008 | unsigned_word b; | |
1009 | unsigned_word EA; | |
1010 | if (RA == 0) b = 0; | |
1011 | else b = *rA; | |
1012 | EA = b + *rB; | |
1013 | if (RESERVE) { | |
1014 | if (RESERVE_ADDR == real_addr(EA, 0/*is-read?*/) | |
1015 | && /*HACK*/ RESERVE_DATA == MEM(unsigned, EA, 8)) { | |
1016 | STORE(EA, 8, *rS); | |
1017 | CR_SET_XER_SO(0, cr_i_zero); | |
1018 | } | |
1019 | else { | |
1020 | /* ment to randomly to store, we never do */ | |
1021 | CR_SET_XER_SO(0, 0); | |
1022 | } | |
1023 | RESERVE = 0; | |
1024 | } | |
1025 | else { | |
1026 | CR_SET_XER_SO(0, 0); | |
1027 | } | |
1028 | ||
1029 | 0.31,6./,11./,16./,21.598,31./:X::sync:Synchronize | |
1030 | /* do nothing */ | |
1031 | ||
1032 | ||
1033 | # | |
1034 | # I.3.3.9 Fixed-Point Arithmetic Instructions | |
1035 | # | |
1036 | ||
1037 | 0.14,6.RT,11.RA,16.SI:D:T::Add Immediate | |
1038 | if (RA_is_0) *rT = EXTS(SI); | |
1039 | else *rT = *rA + EXTS(SI); | |
1040 | 0.15,6.RT,11.RA,16.SI:D:::Add Immediate Shifted | |
1041 | if (RA_is_0) *rT = EXTS(SI) << 16; | |
1042 | else *rT = *rA + (EXTS(SI) << 16); | |
1043 | 0.31,6.RT,11.RA,16.RB,21.OE,22.266,31.Rc:XO:::Add | |
1044 | ALU_BEGIN(*rA); | |
1045 | ALU_ADD(*rB); | |
1046 | ALU_END(*rT, 0/*CA*/, OE, Rc); | |
1047 | 0.31,6.RT,11.RA,16.RB,21.OE,22.40,31.Rc:XO:::Subtract From | |
1048 | ALU_BEGIN(*rA); | |
1049 | ALU_NOT; | |
1050 | ALU_ADD(*rB); | |
1051 | ALU_ADD(1); | |
1052 | ALU_END(*rT, 0/*CA*/, OE, Rc); | |
1053 | 0.12,6.RT,11.RA,16.SI:D:::Add Immediate Carrying | |
1054 | ALU_BEGIN(*rA); | |
1055 | ALU_ADD(EXTS(SI)); | |
1056 | ALU_END(*rT, 1/*CA*/, 0/*OE*/, 0/*Rc*/); | |
1057 | 0.13,6.RT,11.RA,16.SI:D:::Add Immediate Carrying and Record | |
1058 | ALU_BEGIN(*rA); | |
1059 | ALU_ADD(EXTS(SI)); | |
1060 | ALU_END(*rT, 1/*CA*/, 0/*OE*/, 1/*Rc*/); | |
1061 | 0.8,6.RT,11.RA,16.SI:D:::Subtract From Immediate Carrying | |
1062 | ALU_BEGIN(*rA); | |
1063 | ALU_NOT; | |
1064 | ALU_ADD(EXTS(SI)); | |
1065 | ALU_ADD(1); | |
1066 | ALU_END(*rT, 1/*CA*/, 0/*OE*/, 0/*Rc*/); | |
1067 | 0.31,6.RT,11.RA,16.RB,21.OE,22.10,31.Rc:XO:::Add Carrying | |
1068 | ALU_BEGIN(*rA); | |
1069 | ALU_ADD(*rB); | |
1070 | ALU_END(*rT, 1/*CA*/, OE, Rc); | |
1071 | 0.31,6.RT,11.RA,16.RB,21.OE,22.8,31.Rc:XO:::Subtract From Carrying | |
1072 | /* RT <- ~RA + RB + 1 === RT <- RB - RA */ | |
1073 | ALU_BEGIN(*rA); | |
1074 | ALU_NOT; | |
1075 | ALU_ADD(*rB); | |
1076 | ALU_ADD(1); | |
1077 | ALU_END(*rT, 1/*CA*/, OE, Rc); | |
1078 | 0.31,6.RT,11.RA,16.RB,21.OE,22.138,31.Rc:XO:::Add Extended | |
1079 | ALU_BEGIN(*rA); | |
1080 | ALU_ADD(*rB); | |
1081 | ALU_ADD_CA; | |
1082 | ALU_END(*rT, 1/*CA*/, OE, Rc); | |
1083 | 0.31,6.RT,11.RA,16.RB,21.OE,22.136,31.Rc:XO:::Subtract From Extended | |
1084 | ALU_BEGIN(*rA); | |
1085 | ALU_NOT; | |
1086 | ALU_ADD(*rB); | |
1087 | ALU_ADD_CA; | |
1088 | ALU_END(*rT, 1/*CA*/, OE, Rc); | |
1089 | 0.31,6.RT,11.RA,16./,21.OE,22.234,31.Rc:XO:::Add to Minus One Extended | |
1090 | # ALU_BEGIN(*rA); | |
1091 | # ALU_ADD_CA; | |
1092 | # ALU_SUB(1); | |
1093 | # ALU_END(*rT, 1/*CA*/, OE, Rc); | |
1094 | 0.31,6.RT,11.RA,16./,21.OE,22.232,31.Rc:XO:::Subtract From Minus One Extended | |
1095 | # ALU_BEGIN(*rA); | |
1096 | # ALU_NOT; | |
1097 | # ALU_ADD_CA; | |
1098 | # ALU_SUB(1); | |
1099 | # ALU_END(*rT, 1/*CA*/, OE, Rc); | |
1100 | 0.31,6.RT,11.RA,16./,21.OE,22.202,31.Rc:XO::addze:Add to Zero Extended | |
1101 | ALU_BEGIN(*rA); | |
1102 | ALU_ADD_CA; | |
1103 | ALU_END(*rT, 1/*CA*/, OE, Rc); | |
1104 | 0.31,6.RT,11.RA,16./,21.OE,22.200,31.Rc:XO:::Subtract from Zero Extended | |
1105 | ALU_BEGIN(*rA); | |
1106 | ALU_NOT; | |
1107 | ALU_ADD_CA; | |
1108 | ALU_END(*rT, 1/*CA*/, OE, Rc); | |
1109 | 0.31,6.RT,11.RA,16./,21.OE,22.104,31.Rc:XO:::Negate | |
1110 | ALU_BEGIN(*rA); | |
1111 | ALU_NOT; | |
1112 | ALU_ADD(1); | |
1113 | ALU_END(*rT,0/*CA*/,OE,Rc); | |
1114 | 0.7,6.RT,11.RA,16.SI:D::mulli:Multiply Low Immediate | |
1115 | signed_word prod = *rA * EXTS(SI); | |
1116 | *rT = prod; | |
1117 | 0.31,6.RT,11.RA,16.RB,21.OE,22.233,31.Rc:D:64::Multiply Low Doubleword | |
1118 | 0.31,6.RT,11.RA,16.RB,21.OE,22.235,31.Rc:XO::mullw:Multiply Low Word | |
1119 | signed64 a = (signed32)(*rA); | |
1120 | signed64 b = (signed32)(*rB); | |
1121 | signed64 prod = a * b; | |
1122 | signed_word t = prod; | |
1123 | *rT = *rA * *rB; | |
1124 | if (t != prod && OE) | |
1125 | XER |= (xer_overflow | xer_summary_overflow); | |
1126 | CR0_COMPARE(t, 0, Rc); | |
1127 | 0.31,6.RT,11.RA,16.RB,21./,22.73,31.Rc:XO:64::Multiply High Doubleword | |
1128 | 0.31,6.RT,11.RA,16.RB,21./,22.75,31.Rc:XO::mulhw:Multiply High Word | |
1129 | signed64 a = (signed32)(*rA); | |
1130 | signed64 b = (signed32)(*rB); | |
1131 | signed64 prod = a * b; | |
1132 | signed_word t = EXTRACTED64(prod, 0, 31); | |
1133 | *rT = t; | |
1134 | CR0_COMPARE(t, 0, Rc); | |
1135 | 0.31,6.RT,11.RA,16.RB,21./,22.9,31.Rc:XO:64::Multiply High Doubleword Unsigned | |
1136 | 0.31,6.RT,11.RA,16.RB,21./,22.11,31.Rc:XO::milhwu:Multiply High Word Unsigned | |
1137 | unsigned64 a = (unsigned32)(*rA); | |
1138 | unsigned64 b = (unsigned32)(*rB); | |
1139 | unsigned64 prod = a * b; | |
1140 | signed_word t = EXTRACTED64(prod, 0, 31); | |
1141 | *rT = t; | |
1142 | CR0_COMPARE(t, 0, Rc); | |
1143 | 0.31,6.RT,11.RA,16.RB,21.OE,22.489,31.Rc:XO:64::Divide Doubleword | |
1144 | 0.31,6.RT,11.RA,16.RB,21.OE,22.491,31.Rc:XO::divw:Divide Word | |
1145 | signed64 dividend = (signed32)(*rA); | |
1146 | signed64 divisor = (signed32)(*rB); | |
1147 | if (divisor == 0 /* nb 0x8000..0 is sign extended */ | |
1148 | || (dividend == 0x80000000 && divisor == -1)) { | |
1149 | if (OE) | |
1150 | XER |= (xer_overflow | xer_summary_overflow); | |
1151 | CR0_COMPARE(0, 0, Rc); | |
1152 | } | |
1153 | else { | |
1154 | signed64 quotent = dividend / divisor; | |
1155 | *rT = quotent; | |
1156 | CR0_COMPARE((signed_word)quotent, 0, Rc); | |
1157 | } | |
1158 | 0.31,6.RT,11.RA,16.RB,21.OE,22.457,31.Rc:XO:64::Divide Doubleword Unsigned | |
1159 | 0.31,6.RT,11.RA,16.RB,21.OE,22.459,31.Rc:XO::divwu:Divide Word Unsigned | |
1160 | unsigned64 dividend = (unsigned32)(*rA); | |
1161 | unsigned64 divisor = (unsigned32)(*rB); | |
1162 | if (divisor == 0) { | |
1163 | if (OE) | |
1164 | XER |= (xer_overflow | xer_summary_overflow); | |
1165 | CR0_COMPARE(0, 0, Rc); | |
1166 | } | |
1167 | else { | |
1168 | unsigned64 quotent = dividend / divisor; | |
1169 | *rT = quotent; | |
1170 | CR0_COMPARE((signed_word)quotent, 0, Rc); | |
1171 | } | |
1172 | ||
1173 | ||
1174 | # | |
1175 | # I.3.3.10 Fixed-Point Compare Instructions | |
1176 | # | |
1177 | ||
1178 | 0.11,6.BF,9./,10.L,11.RA,16.SI:D:::Compare Immediate | |
1179 | if (!is_64bit_mode && L) | |
1180 | program_interrupt(processor, cia, | |
1181 | illegal_instruction_program_interrupt); | |
1182 | else { | |
1183 | signed_word a; | |
1184 | signed_word b = EXTS(SI); | |
1185 | if (L == 0) | |
1186 | a = EXTENDED(*rA); | |
1187 | else | |
1188 | a = *rA; | |
1189 | CR_COMPARE(BF, a, b); | |
1190 | } | |
1191 | 0.31,6.BF,9./,10.L,11.RA,16.RB,21.0,31./:X:::Compare | |
1192 | if (!is_64bit_mode && L) | |
1193 | program_interrupt(processor, cia, | |
1194 | illegal_instruction_program_interrupt); | |
1195 | else { | |
1196 | signed_word a; | |
1197 | signed_word b; | |
1198 | if (L == 0) { | |
1199 | a = EXTENDED(*rA); | |
1200 | b = EXTENDED(*rB); | |
1201 | } | |
1202 | else { | |
1203 | a = *rA; | |
1204 | b = *rB; | |
1205 | } | |
1206 | CR_COMPARE(BF, a, b); | |
1207 | } | |
1208 | 0.10,6.BF,9./,10.L,11.RA,16.UI:D:::Compare Logical Immediate | |
1209 | if (!is_64bit_mode && L) | |
1210 | program_interrupt(processor, cia, | |
1211 | illegal_instruction_program_interrupt); | |
1212 | else { | |
1213 | unsigned_word a; | |
1214 | unsigned_word b = UI; | |
1215 | if (L == 0) | |
1216 | a = MASKED(*rA, 32, 63); | |
1217 | else | |
1218 | a = *rA; | |
1219 | CR_COMPARE(BF, a, b); | |
1220 | } | |
1221 | 0.31,6.BF,9./,10.L,11.RA,16.RB,21.32,31./:X:::Compare Logical | |
1222 | if (!is_64bit_mode && L) | |
1223 | program_interrupt(processor, cia, | |
1224 | illegal_instruction_program_interrupt); | |
1225 | else { | |
1226 | unsigned_word a; | |
1227 | unsigned_word b; | |
1228 | if (L == 0) { | |
1229 | a = MASKED(*rA, 32, 63); | |
1230 | b = MASKED(*rB, 32, 63); | |
1231 | } | |
1232 | else { | |
1233 | a = *rA; | |
1234 | b = *rB; | |
1235 | } | |
1236 | CR_COMPARE(BF, a, b); | |
1237 | } | |
1238 | ||
1239 | ||
1240 | # | |
1241 | # I.3.3.11 Fixed-Point Trap Instructions | |
1242 | # | |
1243 | ||
1244 | 0.2,6.TO,11.RA,16.SI:D:64::Trap Doubleword Immediate | |
1245 | if (!is_64bit_mode) | |
1246 | program_interrupt(processor, cia, | |
1247 | illegal_instruction_program_interrupt); | |
1248 | else { | |
1249 | signed_word a = *rA; | |
1250 | signed_word b = EXTS(SI); | |
1251 | if ((a < b && TO{0}) | |
1252 | || (a > b && TO{1}) | |
1253 | || (a == b && TO{2}) | |
1254 | || ((unsigned_word)a < (unsigned_word)b && TO{3}) | |
1255 | || ((unsigned_word)a > (unsigned_word)b && TO{4}) | |
1256 | ) | |
1257 | program_interrupt(processor, cia, | |
1258 | trap_program_interrupt); | |
1259 | } | |
1260 | 0.3,6.TO,11.RA,16.SI:D:::Trap Word Immediate | |
1261 | signed_word a = EXTENDED(*rA); | |
1262 | signed_word b = EXTS(SI); | |
1263 | if ((a < b && TO{0}) | |
1264 | || (a > b && TO{1}) | |
1265 | || (a == b && TO{2}) | |
1266 | || ((unsigned_word)a < (unsigned_word)b && TO{3}) | |
1267 | || ((unsigned_word)a > (unsigned_word)b && TO{4}) | |
1268 | ) | |
1269 | program_interrupt(processor, cia, | |
1270 | trap_program_interrupt); | |
1271 | 0.31,6.TO,11.RA,16.RB,21.68,31./:X:64::Trap Doubleword | |
1272 | if (!is_64bit_mode) | |
1273 | program_interrupt(processor, cia, | |
1274 | illegal_instruction_program_interrupt); | |
1275 | else { | |
1276 | signed_word a = *rA; | |
1277 | signed_word b = *rB; | |
1278 | if ((a < b && TO{0}) | |
1279 | || (a > b && TO{1}) | |
1280 | || (a == b && TO{2}) | |
1281 | || ((unsigned_word)a < (unsigned_word)b && TO{3}) | |
1282 | || ((unsigned_word)a > (unsigned_word)b && TO{4}) | |
1283 | ) | |
1284 | program_interrupt(processor, cia, | |
1285 | trap_program_interrupt); | |
1286 | } | |
1287 | 0.31,6.TO,11.RA,16.RB,21.4,31./:X:::Trap Word | |
1288 | signed_word a = EXTENDED(*rA); | |
1289 | signed_word b = EXTENDED(*rB); | |
1290 | if (TO == 12 && rA == rB) { | |
1291 | ITRACE(trace_breakpoint, ("breakpoint\n")); | |
1292 | cpu_halt(processor, cia, was_trap, 0); | |
1293 | } | |
1294 | else if ((a < b && TO{0}) | |
1295 | || (a > b && TO{1}) | |
1296 | || (a == b && TO{2}) | |
1297 | || ((unsigned_word)a < (unsigned_word)b && TO{3}) | |
1298 | || ((unsigned_word)a > (unsigned_word)b && TO{4}) | |
1299 | ) | |
1300 | program_interrupt(processor, cia, | |
1301 | trap_program_interrupt); | |
1302 | ||
1303 | # | |
1304 | # I.3.3.12 Fixed-Point Logical Instructions | |
1305 | # | |
1306 | ||
1307 | 0.28,6.RS,11.RA,16.UI:D:::AND Immediate | |
1308 | *rA = *rS & UI; | |
1309 | CR0_COMPARE(*rA, 0, 1/*Rc*/); | |
1310 | 0.29,6.RS,11.RA,16.UI:D:::AND Immediate Shifted | |
1311 | *rA = *rS & (UI << 16); | |
1312 | CR0_COMPARE(*rA, 0, 1/*Rc*/); | |
1313 | 0.24,6.RS,11.RA,16.UI:D:::OR Immediate | |
1314 | *rA = *rS | UI; | |
1315 | 0.25,6.RS,11.RA,16.UI:D:::OR Immediate Shifted | |
1316 | *rA = *rS | (UI << 16); | |
1317 | 0.26,6.RS,11.RA,16.UI:D:::XOR Immediate | |
1318 | *rA = *rS ^ UI; | |
1319 | 0.27,6.RS,11.RA,16.UI:D:::XOR Immediate Shifted | |
1320 | *rA = *rS ^ (UI << 16); | |
1321 | 0.31,6.RS,11.RA,16.RB,21.28,31.Rc:X:::AND | |
1322 | *rA = *rS & *rB; | |
1323 | CR0_COMPARE(*rA, 0, Rc); | |
1324 | 0.31,6.RS,11.RA,16.RB,21.444,31.Rc:X:::OR | |
1325 | *rA = *rS | *rB; | |
1326 | CR0_COMPARE(*rA, 0, Rc); | |
1327 | 0.31,6.RS,11.RA,16.RB,21.316,31.Rc:X:::XOR | |
1328 | *rA = *rS ^ *rB; | |
1329 | CR0_COMPARE(*rA, 0, Rc); | |
1330 | 0.31,6.RS,11.RA,16.RB,21.476,31.Rc:X:::NAND | |
1331 | *rA = ~(*rS & *rB); | |
1332 | CR0_COMPARE(*rA, 0, Rc); | |
1333 | 0.31,6.RS,11.RA,16.RB,21.124,31.Rc:X:::NOR | |
1334 | *rA = ~(*rS | *rB); | |
1335 | CR0_COMPARE(*rA, 0, Rc); | |
1336 | 0.31,6.RS,11.RA,16.RB,21.284,31.Rc:X:::Equivalent | |
1337 | # *rA = ~(*rS ^ *rB); /* A === B */ | |
1338 | # CR0_COMPARE(*rA, 0, Rc); | |
1339 | 0.31,6.RS,11.RA,16.RB,21.60,31.Rc:X:::AND with Complement | |
1340 | *rA = *rS & ~*rB; | |
1341 | CR0_COMPARE(*rA, 0, Rc); | |
1342 | 0.31,6.RS,11.RA,16.RB,21.412,31.Rc:X:::OR with Complement | |
1343 | *rA = *rS | ~*rB; | |
1344 | CR0_COMPARE(*rA, 0, Rc); | |
1345 | 0.31,6.RS,11.RA,16./,21.954,31.Rc:X::extsb:Extend Sign Byte | |
1346 | *rA = (signed_word)(signed8)*rS; | |
1347 | CR0_COMPARE(*rA, 0, Rc); | |
1348 | 0.31,6.RS,11.RA,16./,21.922,31.Rc:X::extsh:Extend Sign Half Word | |
1349 | *rA = (signed_word)(signed16)*rS; | |
1350 | CR0_COMPARE(*rA, 0, Rc); | |
1351 | 0.31,6.RS,11.RA,16./,21.986,31.Rc:X:64::Extend Sign Word | |
1352 | # *rA = (signed_word)(signed32)*rS; | |
1353 | # CR0_COMPARE(*rA, 0, Rc); | |
1354 | 0.31,6.RS,11.RA,16./,21.58,31.Rc:X:64::Count Leading Zeros Doubleword | |
1355 | # int count = 0; | |
1356 | # unsigned64 mask = BIT64(0); | |
1357 | # unsigned64 source = *rS; | |
1358 | # while (!(source & mask) && mask != 0) { | |
1359 | # mask >>= 1; | |
1360 | # count++; | |
1361 | # } | |
1362 | # *rA = count; | |
1363 | # CR0_COMPARE(count, 0, Rc); /* FIXME - is this correct */ | |
1364 | 0.31,6.RS,11.RA,16./,21.26,31.Rc:X:::Count Leading Zeros Word | |
1365 | int count = 0; | |
1366 | unsigned32 mask = BIT32(0); | |
1367 | unsigned32 source = *rS; | |
1368 | while (!(source & mask) && mask != 0) { | |
1369 | mask >>= 1; | |
1370 | count++; | |
1371 | } | |
1372 | *rA = count; | |
1373 | CR0_COMPARE(count, 0, Rc); /* FIXME - is this correct */ | |
1374 | ||
1375 | ||
1376 | # | |
1377 | # I.3.3.13 Fixed-Point Rotate and Shift Instructions | |
1378 | # | |
1379 | ||
1380 | 0.30,6.RS,11.RA,16.sh_0_4,21.mb,27.0,30.sh_5,31.Rc:MD:64::Rotate Left Doubleword Immediate then Clear Left | |
1381 | # long n = (sh_5 << 4) | sh_0_4; | |
1382 | # unsigned_word r = ROTL64(*rS, n); | |
1383 | # long b = (mb_5 << 4) | mb_0_4; | |
1384 | # unsigned_word m = MASK(b, 63); | |
1385 | # signed_word result = r & m; | |
1386 | # *rA = result; | |
1387 | # CR0_COMPARE(result, 0, Rc); /* FIXME - is this correct */ | |
1388 | 0.30,6.RS,11.RA,16.sh_0_4,21.me,27.1,30.sh_5,31.Rc:MD:64::Rotate Left Doubleword Immediate then Clear Right | |
1389 | # long n = (sh_5 << 4) | sh_0_4; | |
1390 | # unsigned_word r = ROTL64(*rS, n); | |
1391 | # long e = (me_5 << 4) | me_0_4; | |
1392 | # unsigned_word m = MASK(0, e); | |
1393 | # signed_word result = r & m; | |
1394 | # *rA = result; | |
1395 | # CR0_COMPARE(result, 0, Rc); /* FIXME - is this correct */ | |
1396 | 0.30,6.RS,11.RA,16.sh_0_4,21.mb,27.2,30.sh_5,31.Rc:MD:64::Rotate Left Doubleword Immediate then Clear | |
1397 | # long n = (sh_5 << 4) | sh_0_4; | |
1398 | # unsigned_word r = ROTL64(*rS, n); | |
1399 | # long b = (mb_5 << 4) | mb_0_4; | |
1400 | # unsigned_word m = MASK(0, (64-n)); | |
1401 | # signed_word result = r & m; | |
1402 | # *rA = result; | |
1403 | # CR0_COMPARE(result, 0, Rc); /* FIXME - is this correct */ | |
1404 | ||
1405 | 0.21,6.RS,11.RA,16.SH,21.MB,26.ME,31.Rc:M:::Rotate Left Word Immediate then AND with Mask | |
1406 | long n = SH; | |
1407 | unsigned32 s = *rS; | |
1408 | unsigned32 r = ROTL32(s, n); | |
1409 | unsigned32 m = MASK(MB+32, ME+32); | |
1410 | signed_word result = r & m; | |
1411 | *rA = result; | |
1412 | CR0_COMPARE(result, 0, Rc); | |
1413 | ITRACE(trace_alu, | |
1414 | ("n=%d, s=0x%x, r=0x%x, m=0x%x, result=0x%x, cr=0x%x\n", | |
1415 | n, s, r, m, result, CR)); | |
1416 | ||
1417 | 0.30,6.RS,11.RA,16.RB,21.mb,27.8,31.Rc:MDS:64::Rotate Left Doubleword then Clear Left | |
1418 | # long n = MASKED(*rB, 58, 63); | |
1419 | # unsigned_word r = ROTL64(*rS, n); | |
1420 | # long b = (mb_5 << 4) | mb_0_4; | |
1421 | # unsigned_word m = MASK(b, 63); | |
1422 | # signed_word result = r & m; | |
1423 | # *rA = result; | |
1424 | # CR0_COMPARE(result, 0, Rc); | |
1425 | 0.30,6.RS,11.RA,16.RB,21.me,27.9,31.Rc:MDS:64::Rotate Left Doubleword then Clear Right | |
1426 | # long n = MASKED(*rB, 58, 63); | |
1427 | # unsigned_word r = ROTL64(*rS, n); | |
1428 | # long e = (me_5 << 4) | me_0_4; | |
1429 | # unsigned_word m = MASK(0, e); | |
1430 | # signed_word result = r & m; | |
1431 | # *rA = result; | |
1432 | # CR0_COMPARE(result, 0, Rc); | |
1433 | ||
1434 | 0.23,6.RS,11.RA,16.RB,21.MB,26.ME,31.Rc:M:::Rotate Left Word then AND with Mask | |
1435 | # long n = MASKED(*rB, 59, 63); | |
1436 | # unsigned32 r = ROTL32(*rS, n); | |
1437 | # unsigned32 m = MASK(MB+32, ME+32); | |
1438 | # signed_word result = r & m; | |
1439 | # *rA = result; | |
1440 | # CR0_COMPARE(result, 0, Rc); | |
1441 | 0.30,6.RS,11.RA,16.sh_0_4,21.mb,27.3,30.sh_5,31.Rc:MD:64::Rotate Left Doubleword Immediate then Mask Insert | |
1442 | # long n = (sh_5 << 4) | sh_0_4; | |
1443 | # unsigned_word r = ROTL64(*rS, n); | |
1444 | # long b = (mb_5 << 4) | mb_0_4; | |
1445 | # unsigned_word m = MASK(b, (64-n)); | |
1446 | # signed_word result = (r & m) | (*rA & ~m) | |
1447 | # *rA = result; | |
1448 | # CR0_COMPARE(result, 0, Rc); | |
1449 | 0.20,6.RS,11.RA,16.SH,21.MB,26.ME,31.Rc:M::rlwimi:Rotate Left Word Immediate then Mask Insert | |
1450 | long n = SH; | |
1451 | unsigned32 r = ROTL32(*rS, n); | |
1452 | unsigned32 m = MASK(MB+32, ME+32); | |
1453 | signed_word result = (r & m) | (*rA & ~m); | |
1454 | *rA = result; | |
1455 | ITRACE(trace_alu, (": n=%d *rS=0x%x r=0x%x m=0x%x result=0x%x\n", | |
1456 | n, *rS, r, m, result)); | |
1457 | CR0_COMPARE(result, 0, Rc); | |
1458 | ||
1459 | ||
1460 | 0.31,6.RS,11.RA,16.RB,21.27,31.Rc:X:64::Shift Left Doubleword | |
1461 | 0.31,6.RS,11.RA,16.RB,21.24,31.Rc:X:::Shift Left Word | |
1462 | int n = MASKED(*rB, 59, 63); | |
1463 | unsigned32 source = *rS; | |
1464 | signed_word shifted; | |
1465 | if (n < 32) | |
1466 | shifted = (source << n); | |
1467 | else | |
1468 | shifted = 0; | |
1469 | *rA = shifted; | |
1470 | CR0_COMPARE(shifted, 0, Rc); | |
1471 | ITRACE(trace_alu, | |
1472 | ("n=%d, source=0x%x, shifted=0x%x\n", | |
1473 | n, source, shifted)); | |
1474 | 0.31,6.RS,11.RA,16.RB,21.539,31.Rc:X:64::Shift Right Doubleword | |
1475 | 0.31,6.RS,11.RA,16.RB,21.536,31.Rc:X:::Shift Right Word | |
1476 | int n = MASKED(*rB, 59, 63); | |
1477 | unsigned32 source = *rS; | |
1478 | signed_word shifted; | |
1479 | if (n < 32) | |
1480 | shifted = (source >> n); | |
1481 | else | |
1482 | shifted = 0; | |
1483 | *rA = shifted; | |
1484 | CR0_COMPARE(shifted, 0, Rc); | |
1485 | ITRACE(trace_alu, \ | |
1486 | ("n=%d, source=0x%x, shifted=0x%x\n", | |
1487 | n, source, shifted)); | |
1488 | ||
1489 | 0.31,6.RS,11.RA,16.sh_0_4,21.413,30.sh_5,31.Rc:XS:64::Shift Right Algebraic Doubleword Immediate | |
1490 | 0.31,6.RS,11.RA,16.SH,21.824,31.Rc:X:::Shift Right Algebraic Word Immediate | |
1491 | int n = SH; | |
1492 | signed_word r = ROTL32(*rS, /*64*/32-n); | |
1493 | signed_word m = MASK(n+32, 63); | |
1494 | int S = MASKED(*rS, 32, 32); | |
1495 | signed_word shifted = (r & m) | (S ? ~m : 0); | |
1496 | *rA = shifted; | |
1497 | if (S && ((r & ~m) & MASK(32, 63)) != 0) | |
1498 | XER |= xer_carry; | |
1499 | else | |
1500 | XER &= ~xer_carry; | |
1501 | CR0_COMPARE(shifted, 0, Rc); | |
1502 | 0.31,6.RS,11.RA,16.RB,21.794,31.Rc:X:64::Shift Right Algebraic Doubleword | |
1503 | 0.31,6.RS,11.RA,16.RB,21.792,31.Rc:X:::Shift Right Algebraic Word | |
1504 | int n = MASKED(*rB, 58, 63); | |
1505 | int shift = (n >= 31 ? 31 : n); | |
1506 | signed32 source = (signed32)*rS; /* signed to keep sign bit */ | |
1507 | signed32 shifted = source >> shift; | |
1508 | unsigned32 mask = ((unsigned32)-1) >> (31-shift); | |
1509 | *rA = (signed_word)shifted; /* if 64bit will sign extend */ | |
1510 | if (source < 0 && (source & mask)) | |
1511 | XER |= xer_carry; | |
1512 | else | |
1513 | XER &= ~xer_carry; | |
1514 | CR0_COMPARE(shifted, 0, Rc); | |
1515 | ||
1516 | ||
1517 | # | |
1518 | # I.3.3.14 Move to/from System Register Instructions | |
1519 | # | |
1520 | ||
1521 | 0.31,6.RS,11.spr,21.467,31./:XFX:::Move to Special Purpose Register | |
1522 | int n = (spr{5:9} << 5) | spr{0:4}; | |
1523 | if (spr{0} && IS_PROBLEM_STATE(processor)) | |
1524 | program_interrupt(processor, cia, | |
1525 | privileged_instruction_program_interrupt); | |
1526 | else if (!spr_is_valid(n) | |
1527 | || spr_is_readonly(n)) | |
1528 | program_interrupt(processor, cia, | |
1529 | illegal_instruction_program_interrupt); | |
1530 | else { | |
1531 | spreg new_val = (spr_length(n) == 64 | |
1532 | ? *rS | |
1533 | : MASKED(*rS, 32, 63)); | |
1534 | /* HACK - time base registers need to be updated immediatly */ | |
1535 | if (WITH_TIME_BASE) { | |
1536 | signed64 time_base; | |
1537 | switch (n) { | |
1538 | case spr_tbu: | |
1539 | cpu_set_time_base(processor, | |
1540 | (MASKED64(cpu_get_time_base(processor), | |
1541 | 32, 63) | |
1542 | | ((signed64)new_val << 32))); | |
1543 | break; | |
1544 | case spr_tbl: | |
1545 | cpu_set_time_base(processor, | |
1546 | (MASKED64(cpu_get_time_base(processor), | |
1547 | 32, 63) | |
1548 | | ((signed64)new_val << 32))); | |
1549 | break; | |
1550 | case spr_dec: | |
1551 | cpu_set_decrementer(processor, new_val); | |
1552 | break; | |
1553 | default: | |
1554 | SPREG(n) = new_val; | |
1555 | break; | |
1556 | } | |
1557 | } | |
1558 | else { | |
1559 | SPREG(n) = new_val; | |
1560 | } | |
1561 | } | |
1562 | 0.31,6.RT,11.spr,21.339,31./:XFX:uea::Move from Special Purpose Register | |
1563 | int n = (spr{5:9} << 5) | spr{0:4}; | |
1564 | if (spr{0} && IS_PROBLEM_STATE(processor)) | |
1565 | program_interrupt(processor, cia, | |
1566 | privileged_instruction_program_interrupt); | |
1567 | else if (!spr_is_valid(n)) | |
1568 | program_interrupt(processor, cia, | |
1569 | illegal_instruction_program_interrupt); | |
1570 | else { | |
1571 | /* HACK - some SPR's need to get their value extracted specially */ | |
1572 | *rT = SPREG(n); | |
1573 | } | |
1574 | 0.31,6.RS,11./,12.FXM,20./,21.144,31./:XFX::mtfcr:Move to Condition Register Fields | |
1575 | if (FXM == 0xff) { | |
1576 | CR = *rS; | |
1577 | } | |
1578 | else { | |
1579 | unsigned_word mask = 0; | |
1580 | unsigned_word f; | |
1581 | for (f = 0; f < 8; f++) { | |
1582 | if (FXM & (0x80 >> f)) | |
1583 | mask |= (0xf << 4*(7-f)); | |
1584 | } | |
1585 | CR = (MASKED(*rS, 32, 63) & mask) | (CR & ~mask); | |
1586 | } | |
1587 | 0.31,6.BF,9./,11./,16./,21.512,31./:X:::Move to Condition Register from XER | |
1588 | 0.31,6.RT,11./,16./,21.19,31./:X:::Move From Condition Register | |
1589 | *rT = (unsigned32)CR; | |
1590 | ||
1591 | # | |
1592 | # I.4.6.2 Floating-Point Load Instructions | |
1593 | # | |
1594 | ||
1595 | 0.48,6.FRT,11.RA,16.D:D:f:lfs:Load Floating-Point Single | |
1596 | unsigned_word b; | |
1597 | unsigned_word EA; | |
1598 | if (RA == 0) b = 0; | |
1599 | else b = *rA; | |
1600 | EA = b + EXTS(D); | |
1601 | *frT = DOUBLE(MEM(unsigned, EA, 4)); | |
1602 | 0.31,6.FRT,11.RA,16.RB,21.535,31./:X:f::Load Floating-Point Single Indexed | |
1603 | unsigned_word b; | |
1604 | unsigned_word EA; | |
1605 | if (RA == 0) b = 0; | |
1606 | else b = *rA; | |
1607 | EA = b + *rB; | |
1608 | *frT = DOUBLE(MEM(unsigned, EA, 4)); | |
1609 | 0.49,6.FRT,11.RA,16.D:D:f::Load Floating-Point Single with Update | |
1610 | unsigned_word EA; | |
1611 | if (RA == 0) | |
1612 | program_interrupt(processor, cia, | |
1613 | illegal_instruction_program_interrupt); | |
1614 | EA = *rA + EXTS(D); | |
1615 | *frT = DOUBLE(MEM(unsigned, EA, 4)); | |
1616 | *rA = EA; | |
1617 | 0.31,6.FRT,11.RA,16.RB,21.576,31./:X:f::Load Floating-Point Single with Update Indexed | |
1618 | unsigned_word EA; | |
1619 | if (RA == 0) | |
1620 | program_interrupt(processor, cia, | |
1621 | illegal_instruction_program_interrupt); | |
1622 | EA = *rA + *rB; | |
1623 | *frT = DOUBLE(MEM(unsigned, EA, 4)); | |
1624 | *rA = EA; | |
1625 | ||
1626 | 0.50,6.FRT,11.RA,16.D:D:f::Load Floating-Point Double | |
1627 | unsigned_word b; | |
1628 | unsigned_word EA; | |
1629 | if (RA == 0) b = 0; | |
1630 | else b = *rA; | |
1631 | EA = b + EXTS(D); | |
1632 | *frT = MEM(unsigned, EA, 8); | |
1633 | 0.31,6.FRT,11.RA,16.RB,21.599,31./:X:f::Load Floating-Point Double Indexed | |
1634 | unsigned_word b; | |
1635 | unsigned_word EA; | |
1636 | if (RA == 0) b = 0; | |
1637 | else b = *rA; | |
1638 | EA = b + *rB; | |
1639 | *frT = MEM(unsigned, EA, 8); | |
1640 | 0.51,6.FRT,11.RA,16.D:D:f::Load Floating-Point Double with Update | |
1641 | unsigned_word EA; | |
1642 | if (RA == 0) | |
1643 | program_interrupt(processor, cia, | |
1644 | illegal_instruction_program_interrupt); | |
1645 | EA = *rA + EXTS(D); | |
1646 | *frT = MEM(unsigned, EA, 8); | |
1647 | *rA = EA; | |
1648 | 0.31,6.FRT,11.RA,16.RB,21.631,31./:X:f::Load Floating-Point Double with Update Indexed | |
1649 | unsigned_word EA; | |
1650 | if (RA == 0) | |
1651 | program_interrupt(processor, cia, | |
1652 | illegal_instruction_program_interrupt); | |
1653 | EA = *rA + *rB; | |
1654 | *frT = MEM(unsigned, EA, 8); | |
1655 | *rA = EA; | |
1656 | ||
1657 | ||
1658 | # | |
1659 | # I.4.6.3 Floating-Point Store Instructions | |
1660 | # | |
1661 | ||
1662 | 0.52,6.FRS,11.RA,16.D:D:f::Store Floating-Point Single | |
1663 | unsigned_word b; | |
1664 | unsigned_word EA; | |
1665 | if (RA == 0) b = 0; | |
1666 | else b = *rA; | |
1667 | EA = b + EXTS(D); | |
1668 | STORE(EA, 4, SINGLE(*frS)); | |
1669 | 0.31,6.FRS,11.RA,16.RB,21.663,31./:X:f::Store Floating-Point Single Indexed | |
1670 | unsigned_word b; | |
1671 | unsigned_word EA; | |
1672 | if (RA == 0) b = 0; | |
1673 | else b = *rA; | |
1674 | EA = b + *rB; | |
1675 | STORE(EA, 4, SINGLE(*frS)); | |
1676 | 0.53,6.FRS,11.RA,16.D:D:f::Store Floating-Point Single with Update | |
1677 | unsigned_word EA; | |
1678 | if (RA == 0) | |
1679 | program_interrupt(processor, cia, | |
1680 | illegal_instruction_program_interrupt); | |
1681 | EA = *rA + EXTS(D); | |
1682 | STORE(EA, 4, SINGLE(*frS)); | |
1683 | *rA = EA; | |
1684 | 0.31,6.FRS,11.RA,16.RB,21.695,31./:X:f::Store Floating-Point Single with Update Indexed | |
1685 | unsigned_word EA; | |
1686 | if (RA == 0) | |
1687 | program_interrupt(processor, cia, | |
1688 | illegal_instruction_program_interrupt); | |
1689 | EA = *rA + *rB; | |
1690 | STORE(EA, 4, SINGLE(*frS)); | |
1691 | *rA = EA; | |
1692 | ||
1693 | 0.54,6.FRS,11.RA,16.D:D:f::Store Floating-Point Double | |
1694 | unsigned_word b; | |
1695 | unsigned_word EA; | |
1696 | if (RA == 0) b = 0; | |
1697 | else b = *rA; | |
1698 | EA = b + EXTS(D); | |
1699 | STORE(EA, 8, *frS); | |
1700 | 0.31,6.FRS,11.RA,16.RB,21.727,31./:X:f::Store Floating-Point Double Indexed | |
1701 | unsigned_word b; | |
1702 | unsigned_word EA; | |
1703 | if (RA == 0) b = 0; | |
1704 | else b = *rA; | |
1705 | EA = b + *rB; | |
1706 | STORE(EA, 8, *frS); | |
1707 | 0.55,6.FRS,11.RA,16.D:D:f::Store Floating-Point Double with Update | |
1708 | unsigned_word EA; | |
1709 | if (RA == 0) | |
1710 | program_interrupt(processor, cia, | |
1711 | illegal_instruction_program_interrupt); | |
1712 | EA = *rA + EXTS(D); | |
1713 | STORE(EA, 8, *frS); | |
1714 | *rA = EA; | |
1715 | 0.31,6.FRS,11.RA,16.RB,21.759,31./:X:f::Store Floating-Point Double with Update Indexed | |
1716 | unsigned_word EA; | |
1717 | if (RA == 0) | |
1718 | program_interrupt(processor, cia, | |
1719 | illegal_instruction_program_interrupt); | |
1720 | EA = *rA + *rB; | |
1721 | STORE(EA, 8, *frS); | |
1722 | *rA = EA; | |
1723 | ||
1724 | ||
1725 | # | |
1726 | # I.4.6.4 Floating-Point Move Instructions | |
1727 | # | |
1728 | ||
1729 | 0.63,6.FRT,11./,16.FRB,21.72,31.Rc:X:f::Floating Move Register | |
1730 | *frT = *frB; | |
1731 | CR1_UPDATE(Rc); | |
1732 | 0.63,6.FRT,11./,16.FRB,21.40,31.Rc:X:f::Floating Negate | |
1733 | *frT = *frB ^ BIT64(0); | |
1734 | CR1_UPDATE(Rc); | |
1735 | 0.63,6.FRT,11./,16.FRB,21.264,31.Rc:X:f::Floating Absolute Value | |
1736 | *frT = *frB & ~BIT64(0); | |
1737 | CR1_UPDATE(Rc); | |
1738 | 0.63,6.FRT,11./,16.FRB,21.136,31.Rc:X:f::Floating Negative Absolute Value | |
1739 | *frT = *frB | BIT64(0); | |
1740 | CR1_UPDATE(Rc); | |
1741 | ||
1742 | ||
1743 | ||
1744 | # | |
1745 | # I.4.6.5 Floating-Point Arithmetic Instructions | |
1746 | # | |
1747 | ||
1748 | 0.63,6.FRT,11.FRA,16.FRB,21./,26.21,31.Rc:A:f:fadd:Floating Add | |
1749 | FPSCR_BEGIN; | |
1750 | if (is_invalid_operation(processor, cia, | |
1751 | *frA, *frB, | |
1752 | fpscr_vxsnan | fpscr_vxisi, | |
1753 | 0, /*single?*/ | |
1754 | 0) /*negate?*/) { | |
1755 | invalid_arithemetic_operation(processor, cia, | |
1756 | frT, *frA, *frB, 0, | |
1757 | 0, /*instruction_is_frsp*/ | |
1758 | 0, /*instruction_is_convert_to_64bit*/ | |
1759 | 0, /*instruction_is_convert_to_32bit*/ | |
1760 | 0); /*single-precision*/ | |
1761 | } | |
1762 | else { | |
1763 | /*HACK!*/ | |
1764 | double s = *(double*)frA + *(double*)frB; | |
1765 | *(double*)frT = s; | |
1766 | } | |
1767 | FPSCR_END(Rc); | |
1768 | 0.59,6.FRT,11.FRA,16.FRB,21./,26.21,31.Rc:A:f:fadds:Floating Add Single | |
1769 | FPSCR_BEGIN; | |
1770 | if (is_invalid_operation(processor, cia, | |
1771 | *frA, *frB, | |
1772 | fpscr_vxsnan | fpscr_vxisi, | |
1773 | 1, /*single?*/ | |
1774 | 0) /*negate?*/) { | |
1775 | invalid_arithemetic_operation(processor, cia, | |
1776 | frT, *frA, *frB, 0, | |
1777 | 0, /*instruction_is_frsp*/ | |
1778 | 0, /*instruction_is_convert_to_64bit*/ | |
1779 | 0, /*instruction_is_convert_to_32bit*/ | |
1780 | 1); /*single-precision*/ | |
1781 | } | |
1782 | else { | |
1783 | /*HACK!*/ | |
1784 | float s = *(double*)frA + *(double*)frB; | |
1785 | *(double*)frT = s; | |
1786 | } | |
1787 | FPSCR_END(Rc); | |
1788 | ||
1789 | 0.63,6.FRT,11.FRA,16.FRB,21./,26.20,31.Rc:A:f:fsub:Floating Subtract | |
1790 | FPSCR_BEGIN; | |
1791 | if (is_invalid_operation(processor, cia, | |
1792 | *frA, *frB, | |
1793 | fpscr_vxsnan | fpscr_vxisi, | |
1794 | 0, /*single?*/ | |
1795 | 1) /*negate?*/) { | |
1796 | invalid_arithemetic_operation(processor, cia, | |
1797 | frT, *frA, *frB, 0, | |
1798 | 0, /*instruction_is_frsp*/ | |
1799 | 0, /*instruction_is_convert_to_64bit*/ | |
1800 | 0, /*instruction_is_convert_to_32bit*/ | |
1801 | 0); /*single-precision*/ | |
1802 | } | |
1803 | else { | |
1804 | /*HACK!*/ | |
1805 | double s = *(double*)frA - *(double*)frB; | |
1806 | *(double*)frT = s; | |
1807 | } | |
1808 | FPSCR_END(Rc); | |
1809 | 0.59,6.FRT,11.FRA,16.FRB,21./,26.20,31.Rc:A:f:fsubs:Floating Subtract Single | |
1810 | FPSCR_BEGIN; | |
1811 | if (is_invalid_operation(processor, cia, | |
1812 | *frA, *frB, | |
1813 | fpscr_vxsnan | fpscr_vxisi, | |
1814 | 1, /*single?*/ | |
1815 | 1) /*negate?*/) { | |
1816 | invalid_arithemetic_operation(processor, cia, | |
1817 | frT, *frA, *frB, 0, | |
1818 | 0, /*instruction_is_frsp*/ | |
1819 | 0, /*instruction_is_convert_to_64bit*/ | |
1820 | 0, /*instruction_is_convert_to_32bit*/ | |
1821 | 1); /*single-precision*/ | |
1822 | } | |
1823 | else { | |
1824 | /*HACK!*/ | |
1825 | float s = *(double*)frA - *(double*)frB; | |
1826 | *(double*)frT = s; | |
1827 | } | |
1828 | FPSCR_END(Rc); | |
1829 | ||
1830 | 0.63,6.FRT,11.FRA,16./,21.FRC,26.25,31.Rc:A:f:fmul:Floating Multiply | |
1831 | FPSCR_BEGIN; | |
1832 | if (is_invalid_operation(processor, cia, | |
1833 | *frA, *frC, | |
1834 | fpscr_vxsnan | fpscr_vximz, | |
1835 | 0, /*single?*/ | |
1836 | 0) /*negate?*/) { | |
1837 | invalid_arithemetic_operation(processor, cia, | |
1838 | frT, *frA, 0, *frC, | |
1839 | 0, /*instruction_is_frsp*/ | |
1840 | 0, /*instruction_is_convert_to_64bit*/ | |
1841 | 0, /*instruction_is_convert_to_32bit*/ | |
1842 | 0); /*single-precision*/ | |
1843 | } | |
1844 | else { | |
1845 | /*HACK!*/ | |
1846 | double s = *(double*)frA * *(double*)frC; | |
1847 | *(double*)frT = s; | |
1848 | } | |
1849 | FPSCR_END(Rc); | |
1850 | 0.59,6.FRT,11.FRA,16./,21.FRC,26.25,31.Rc:A:f:fmuls:Floating Multiply Single | |
1851 | FPSCR_BEGIN; | |
1852 | if (is_invalid_operation(processor, cia, | |
1853 | *frA, *frC, | |
1854 | fpscr_vxsnan | fpscr_vximz, | |
1855 | 1, /*single?*/ | |
1856 | 0) /*negate?*/) { | |
1857 | invalid_arithemetic_operation(processor, cia, | |
1858 | frT, *frA, 0, *frC, | |
1859 | 0, /*instruction_is_frsp*/ | |
1860 | 0, /*instruction_is_convert_to_64bit*/ | |
1861 | 0, /*instruction_is_convert_to_32bit*/ | |
1862 | 1); /*single-precision*/ | |
1863 | } | |
1864 | else { | |
1865 | /*HACK!*/ | |
1866 | float s = *(double*)frA * *(double*)frC; | |
1867 | *(double*)frT = s; | |
1868 | } | |
1869 | FPSCR_END(Rc); | |
1870 | ||
1871 | 0.63,6.FRT,11.FRA,16.FRB,21./,26.18,31.Rc:A:f:fdiv:Floating Divide | |
1872 | FPSCR_BEGIN; | |
1873 | if (is_invalid_operation(processor, cia, | |
1874 | *frA, *frB, | |
1875 | fpscr_vxsnan | fpscr_vxzdz, | |
1876 | 0, /*single?*/ | |
1877 | 0) /*negate?*/) { | |
1878 | invalid_arithemetic_operation(processor, cia, | |
1879 | frT, *frA, *frB, 0, | |
1880 | 0, /*instruction_is_frsp*/ | |
1881 | 0, /*instruction_is_convert_to_64bit*/ | |
1882 | 0, /*instruction_is_convert_to_32bit*/ | |
1883 | 0); /*single-precision*/ | |
1884 | } | |
1885 | else { | |
1886 | /*HACK!*/ | |
1887 | double s = *(double*)frA / *(double*)frB; | |
1888 | *(double*)frT = s; | |
1889 | } | |
1890 | FPSCR_END(Rc); | |
1891 | 0.59,6.FRT,11.FRA,16.FRB,21./,26.18,31.Rc:A:f:fdivs:Floating Divide Single | |
1892 | FPSCR_BEGIN; | |
1893 | if (is_invalid_operation(processor, cia, | |
1894 | *frA, *frB, | |
1895 | fpscr_vxsnan | fpscr_vxzdz, | |
1896 | 1, /*single?*/ | |
1897 | 0) /*negate?*/) { | |
1898 | invalid_arithemetic_operation(processor, cia, | |
1899 | frT, *frA, *frB, 0, | |
1900 | 0, /*instruction_is_frsp*/ | |
1901 | 0, /*instruction_is_convert_to_64bit*/ | |
1902 | 0, /*instruction_is_convert_to_32bit*/ | |
1903 | 1); /*single-precision*/ | |
1904 | } | |
1905 | else { | |
1906 | /*HACK!*/ | |
1907 | float s = *(double*)frA / *(double*)frB; | |
1908 | *(double*)frT = s; | |
1909 | } | |
1910 | FPSCR_END(Rc); | |
1911 | ||
1912 | 0.63,6.FRT,11.FRA,16.FRB,21.FRC,26.29,31.Rc:A:f:fmadd:Floating Multiply-Add | |
1913 | FPSCR_BEGIN; | |
1914 | double product; /*HACK! - incorrectly loosing precision ... */ | |
1915 | /* compute the multiply */ | |
1916 | if (is_invalid_operation(processor, cia, | |
1917 | *frA, *frC, | |
1918 | fpscr_vxsnan | fpscr_vximz, | |
1919 | 0, /*single?*/ | |
1920 | 0) /*negate?*/) { | |
1921 | invalid_arithemetic_operation(processor, cia, | |
1922 | (unsigned64*)&product, *frA, 0, *frC, | |
1923 | 0, /*instruction_is_frsp*/ | |
1924 | 0, /*instruction_is_convert_to_64bit*/ | |
1925 | 0, /*instruction_is_convert_to_32bit*/ | |
1926 | 0); /*single-precision*/ | |
1927 | } | |
1928 | else { | |
1929 | /*HACK!*/ | |
1930 | product = *(double*)frA * *(double*)frC; | |
1931 | } | |
1932 | /* compute the add */ | |
1933 | if (is_invalid_operation(processor, cia, | |
1934 | product, *frB, | |
1935 | fpscr_vxsnan | fpscr_vxisi, | |
1936 | 0, /*single?*/ | |
1937 | 0) /*negate?*/) { | |
1938 | invalid_arithemetic_operation(processor, cia, | |
1939 | frT, product, *frB, 0, | |
1940 | 0, /*instruction_is_frsp*/ | |
1941 | 0, /*instruction_is_convert_to_64bit*/ | |
1942 | 0, /*instruction_is_convert_to_32bit*/ | |
1943 | 0); /*single-precision*/ | |
1944 | } | |
1945 | else { | |
1946 | /*HACK!*/ | |
1947 | double s = product + *(double*)frB; | |
1948 | *(double*)frT = s; | |
1949 | } | |
1950 | FPSCR_END(Rc); | |
1951 | 0.59,6.FRT,11.FRA,16.FRB,21.FRC,26.29,31.Rc:A:f::Floating Multiply-Add Single | |
1952 | ||
1953 | 0.63,6.FRT,11.FRA,16.FRB,21.FRC,26.28,31.Rc:A:f::Floating Multiply-Subtract | |
1954 | 0.59,6.FRT,11.FRA,16.FRB,21.FRC,26.28,31.Rc:A:f::Floating Multiply-Subtract Single | |
1955 | ||
1956 | 0.63,6.FRT,11.FRA,16.FRB,21.FRC,26.31,31.Rc:A:f::Floating Negative Multiply-Add | |
1957 | 0.59,6.FRT,11.FRA,16.FRB,21.FRC,26.31,31.Rc:A:f::Floating Negative Multiply-Add Single | |
1958 | ||
1959 | 0.63,6.FRT,11.FRA,16.FRB,21.FRC,26.30,31.Rc:A:f::Floating Negative Multiply-Subtract | |
1960 | 0.59,6.FRT,11.FRA,16.FRB,21.FRC,26.30,31.Rc:A:f::Floating Negative Multiply-Subtract Single | |
1961 | ||
1962 | ||
1963 | # | |
1964 | # I.4.6.6 Floating-Point Rounding and Conversion Instructions | |
1965 | # | |
1966 | ||
1967 | 0.63,6.FRT,11./,16.FRB,21.12,31.Rc:X:f::Floating Round to Single-Precision | |
1968 | int sign; | |
1969 | int exp; | |
1970 | unsigned64 frac_grx; | |
1971 | /* split off cases for what to do */ | |
1972 | if (EXTRACTED64(*frB, 1, 11) < 897 | |
1973 | && EXTRACTED64(*frB, 1, 63) > 0) { | |
1974 | if ((FPSCR & fpscr_ue) == 0) goto Disabled_Exponent_Underflow; | |
1975 | if ((FPSCR & fpscr_ue) != 0) goto Enabled_Exponent_Underflow; | |
1976 | } | |
1977 | if (EXTRACTED64(*frB, 1, 11) > 1150 | |
1978 | && EXTRACTED64(*frB, 1, 11) < 2047) { | |
1979 | if ((FPSCR & fpscr_oe) == 0) goto Disabled_Exponent_Overflow; | |
1980 | if ((FPSCR & fpscr_oe) != 0) goto Enabled_Exponent_Overflow; | |
1981 | } | |
1982 | if (EXTRACTED64(*frB, 1, 11) > 896 | |
1983 | && EXTRACTED64(*frB, 1, 11) < 1151) goto Normal_Operand; | |
1984 | if (EXTRACTED64(*frB, 1, 63) == 0) goto Zero_Operand; | |
1985 | if (EXTRACTED64(*frB, 1, 11) == 2047) { | |
1986 | if (EXTRACTED64(*frB, 12, 63) == 0) goto Infinity_Operand; | |
1987 | if (EXTRACTED64(*frB, 12, 12) == 1) goto QNaN_Operand; | |
1988 | if (EXTRACTED64(*frB, 12, 12) == 0 | |
1989 | && EXTRACTED64(*frB, 13, 63) > 0) goto SNaN_Operand; | |
1990 | } | |
1991 | /* handle them */ | |
1992 | Disabled_Exponent_Underflow: | |
1993 | sign = EXTRACTED64(*frB, 0, 0); | |
1994 | if (EXTRACTED64(*frB, 1, 11) == 0) { | |
1995 | exp = -1022; | |
1996 | frac_grx = INSERTED64(EXTRACTED64(*frB, 12, 63), 1, 52); | |
1997 | } | |
1998 | if (EXTRACTED64(*frB, 1, 11) > 0) { | |
1999 | exp = EXTRACTED64(*frB, 1, 11) - 1023; | |
2000 | frac_grx = BIT64(0) | INSERTED64(EXTRACTED64(*frB, 12, 63), 1, 52); | |
2001 | } | |
2002 | Denormalize_Operand: | |
2003 | /* G|R|X == zero from above */ | |
2004 | while (exp < -126) { | |
2005 | exp = exp - 1; | |
2006 | frac_grx = (INSERTED64(EXTRACTED64(frac_grx, 0, 54), 1, 55) | |
2007 | | MASKED64(frac_grx, 55, 55)); | |
2008 | } | |
2009 | FPSCR_SET_UX(EXTRACTED64(frac_grx, 24, 55) > 0); | |
2010 | Round_Single(processor, sign, &exp, &frac_grx); | |
2011 | FPSCR_SET_XX(FPSCR & fpscr_fi); | |
2012 | if (EXTRACTED64(frac_grx, 0, 52) == 0) { | |
2013 | *frT = INSERTED64(sign, 0, 0); | |
2014 | if (sign == 0) FPSCR_SET_FPRF(fpscr_rf_pos_zero); | |
2015 | if (sign == 1) FPSCR_SET_FPRF(fpscr_rf_neg_zero); | |
2016 | } | |
2017 | if (EXTRACTED64(frac_grx, 0, 52) > 0) { | |
2018 | if (EXTRACTED64(frac_grx, 0, 0) == 1) { | |
2019 | if (sign == 0) FPSCR_SET_FPRF(fpscr_rf_pos_normal_number); | |
2020 | if (sign == 1) FPSCR_SET_FPRF(fpscr_rf_neg_normal_number); | |
2021 | } | |
2022 | if (EXTRACTED64(frac_grx, 0, 0) == 0) { | |
2023 | if (sign == 0) FPSCR_SET_FPRF(fpscr_rf_pos_denormalized_number); | |
2024 | if (sign == 1) FPSCR_SET_FPRF(fpscr_rf_neg_denormalized_number); | |
2025 | } | |
2026 | /*Normalize_Operand:*/ | |
2027 | while (EXTRACTED64(frac_grx, 0, 0) == 0) { | |
2028 | exp = exp - 1; | |
2029 | frac_grx = INSERTED64(EXTRACTED64(frac_grx, 1, 52), 0, 51); | |
2030 | } | |
2031 | *frT = (INSERTED64(sign, 0, 0) | |
2032 | | INSERTED64(exp + 1023, 1, 11) | |
2033 | | INSERTED64(EXTRACTED64(frac_grx, 1, 52), 12, 63)); | |
2034 | } | |
2035 | goto Done; | |
2036 | Enabled_Exponent_Underflow: | |
2037 | FPSCR_SET_UX(1); | |
2038 | sign = EXTRACTED64(*frB, 0, 0); | |
2039 | if (EXTRACTED64(*frB, 1, 11) == 0) { | |
2040 | exp = -1022; | |
2041 | frac_grx = INSERTED64(EXTRACTED64(*frB, 12, 63), 1, 52); | |
2042 | } | |
2043 | if (EXTRACTED64(*frB, 1, 11) > 0) { | |
2044 | exp = EXTRACTED64(*frB, 1, 11) - 1023; | |
2045 | frac_grx = (BIT64(0) | | |
2046 | INSERTED64(EXTRACTED64(*frB, 12, 63), 1, 52)); | |
2047 | } | |
2048 | /*Normalize_Operand:*/ | |
2049 | while (EXTRACTED64(frac_grx, 0, 0) == 0) { | |
2050 | exp = exp - 1; | |
2051 | frac_grx = INSERTED64(EXTRACTED64(frac_grx, 1, 52), 0, 51); | |
2052 | } | |
2053 | Round_Single(processor, sign, &exp, &frac_grx); | |
2054 | FPSCR_SET_XX(FPSCR & fpscr_fi); | |
2055 | exp = exp + 192; | |
2056 | *frT = (INSERTED64(sign, 0, 0) | |
2057 | | INSERTED64(exp + 1023, 1, 11) | |
2058 | | INSERTED64(EXTRACTED64(frac_grx, 1, 52), 12, 63)); | |
2059 | if (sign == 0) FPSCR_SET_FPRF(fpscr_rf_pos_normal_number); | |
2060 | if (sign == 1) FPSCR_SET_FPRF(fpscr_rf_neg_normal_number); | |
2061 | goto Done; | |
2062 | Disabled_Exponent_Overflow: | |
2063 | FPSCR_SET_OX(1); | |
2064 | if ((FPSCR & fpscr_rn) == fpscr_rn_round_to_nearest) { | |
2065 | if (EXTRACTED64(*frB, 0, 0) == 0) { | |
2066 | *frT = INSERTED64(0x7FF00000, 0, 31) | 0x00000000; | |
2067 | FPSCR_SET_FPRF(fpscr_rf_pos_infinity); | |
2068 | } | |
2069 | if (EXTRACTED64(*frB, 0, 0) == 1) { | |
2070 | *frT = INSERTED64(0xFFF00000, 0, 31) | 0x00000000; | |
2071 | FPSCR_SET_FPRF(fpscr_rf_neg_infinity); | |
2072 | } | |
2073 | } | |
2074 | if ((FPSCR & fpscr_rn) == fpscr_rn_round_towards_zero) { | |
2075 | if (EXTRACTED64(*frB, 0, 0) == 0) { | |
2076 | *frT = INSERTED64(0x47EFFFFF, 0, 31) | 0xE0000000; | |
2077 | FPSCR_SET_FPRF(fpscr_rf_pos_normal_number); | |
2078 | } | |
2079 | if (EXTRACTED64(*frB, 0, 0) == 1) { | |
2080 | *frT = INSERTED64(0xC7EFFFFF, 0, 31) | 0xE0000000; | |
2081 | FPSCR_SET_FPRF(fpscr_rf_neg_normal_number); | |
2082 | } | |
2083 | } | |
2084 | if ((FPSCR & fpscr_rn) == fpscr_rn_round_towards_pos_infinity) { | |
2085 | if (EXTRACTED64(*frB, 0, 0) == 0) { | |
2086 | *frT = INSERTED64(0x7FF00000, 0, 31) | 0x00000000; | |
2087 | FPSCR_SET_FPRF(fpscr_rf_pos_infinity); | |
2088 | } | |
2089 | if (EXTRACTED64(*frB, 0, 0) == 1) { | |
2090 | *frT = INSERTED64(0xC7EFFFFF, 0, 31) | 0xE0000000; | |
2091 | FPSCR_SET_FPRF(fpscr_rf_neg_normal_number); | |
2092 | } | |
2093 | } | |
2094 | if ((FPSCR & fpscr_rn) == fpscr_rn_round_towards_neg_infinity) { | |
2095 | if (EXTRACTED64(*frB, 0, 0) == 0) { | |
2096 | *frT = INSERTED64(0x47EFFFFF, 0, 31) | 0xE0000000; | |
2097 | FPSCR_SET_FPRF(fpscr_rf_pos_normal_number); | |
2098 | } | |
2099 | if (EXTRACTED64(*frB, 0, 0) == 1) { | |
2100 | *frT = INSERTED64(0xFFF00000, 0, 31) | 0x00000000; | |
2101 | FPSCR_SET_FPRF(fpscr_rf_neg_infinity); | |
2102 | } | |
2103 | } | |
2104 | /* FPSCR[FR] <- undefined */ | |
2105 | FPSCR_SET_FI(1); | |
2106 | FPSCR_SET_XX(1); | |
2107 | goto Done; | |
2108 | Enabled_Exponent_Overflow: | |
2109 | sign = EXTRACTED64(*frB, 0, 0); | |
2110 | exp = EXTRACTED64(*frB, 1, 11) - 1023; | |
2111 | frac_grx = BIT64(0) | INSERTED64(EXTRACTED64(*frB, 12, 63), 1, 52); | |
2112 | Round_Single(processor, sign, &exp, &frac_grx); | |
2113 | FPSCR_SET_XX(FPSCR & fpscr_fi); | |
2114 | Enabled_Overflow: | |
2115 | FPSCR_SET_OX(1); | |
2116 | exp = exp - 192; | |
2117 | *frT = (INSERTED64(sign, 0, 0) | |
2118 | | INSERTED64(exp + 1023, 1, 11) | |
2119 | | INSERTED64(EXTRACTED64(frac_grx, 1, 52), 12, 63)); | |
2120 | if (sign == 0) FPSCR_SET_FPRF(fpscr_rf_pos_normal_number); | |
2121 | if (sign == 1) FPSCR_SET_FPRF(fpscr_rf_neg_normal_number); | |
2122 | goto Done; | |
2123 | Zero_Operand: | |
2124 | *frT = *frB; | |
2125 | if (EXTRACTED64(*frB, 0, 0) == 0) FPSCR_SET_FPRF(fpscr_rf_pos_zero); | |
2126 | if (EXTRACTED64(*frB, 0, 0) == 1) FPSCR_SET_FPRF(fpscr_rf_neg_zero); | |
2127 | FPSCR_SET_FR(0); | |
2128 | FPSCR_SET_FI(0); | |
2129 | goto Done; | |
2130 | Infinity_Operand: | |
2131 | *frT = *frB; | |
2132 | if (EXTRACTED64(*frB, 0, 0) == 0) FPSCR_SET_FPRF(fpscr_rf_pos_infinity); | |
2133 | if (EXTRACTED64(*frB, 0, 0) == 1) FPSCR_SET_FPRF(fpscr_rf_neg_infinity); | |
2134 | FPSCR_SET_FR(0); | |
2135 | FPSCR_SET_FI(0); | |
2136 | goto Done; | |
2137 | QNaN_Operand: | |
2138 | *frT = INSERTED64(EXTRACTED64(*frB, 0, 34), 0, 34); | |
2139 | FPSCR_SET_FPRF(fpscr_rf_quiet_nan); | |
2140 | FPSCR_SET_FR(0); | |
2141 | FPSCR_SET_FI(0); | |
2142 | goto Done; | |
2143 | SNaN_Operand: | |
2144 | FPSCR_OR_VX(fpscr_vxsnan); | |
2145 | if ((FPSCR & fpscr_ve) == 0) { | |
2146 | *frT = (MASKED64(*frB, 0, 11) | |
2147 | | BIT64(12) | |
2148 | | MASKED64(*frB, 13, 34)); | |
2149 | FPSCR_SET_FPRF(fpscr_rf_quiet_nan); | |
2150 | } | |
2151 | FPSCR_SET_FR(0); | |
2152 | FPSCR_SET_FI(0); | |
2153 | goto Done; | |
2154 | Normal_Operand: | |
2155 | sign = EXTRACTED64(*frB, 0, 0); | |
2156 | exp = EXTRACTED64(*frB, 1, 11) - 1023; | |
2157 | frac_grx = BIT64(0) | INSERTED64(EXTRACTED64(*frB, 12, 63), 1, 52); | |
2158 | Round_Single(processor, sign, &exp, &frac_grx); | |
2159 | FPSCR_SET_XX(FPSCR & fpscr_fi); | |
2160 | if (exp > 127 && (FPSCR & fpscr_oe) == 0) goto Disabled_Exponent_Overflow; | |
2161 | if (exp > 127 && (FPSCR & fpscr_oe) != 0) goto Enabled_Overflow; | |
2162 | *frT = (INSERTED64(sign, 0, 0) | |
2163 | | INSERTED64(exp + 1023, 1, 11) | |
2164 | | INSERTED64(EXTRACTED64(frac_grx, 1, 52), 12, 63)); | |
2165 | if (sign == 0) FPSCR_SET_FPRF(fpscr_rf_pos_normal_number); | |
2166 | if (sign == 1) FPSCR_SET_FPRF(fpscr_rf_neg_normal_number); | |
2167 | goto Done; | |
2168 | Done: | |
2169 | 0.63,6.FRT,11./,16.FRB,21.814,31.Rc:X:64,f::Floating Convert To Integer Doubleword | |
2170 | 0.63,6.FRT,11./,16.FRB,21.815,31.Rc:X:64,f::Floating Convert To Integer Doubleword with round towards Zero | |
2171 | 0.63,6.FRT,11./,16.FRB,21.14,31.Rc:X:f::Floating Convert To Integer Word | |
2172 | 0.63,6.FRT,11./,16.FRB,21.15,31.Rc:X:f:fctiwz:Floating Convert To Integer Word with round towards Zero | |
2173 | FPSCR_BEGIN; | |
2174 | convert_to_integer(processor, cia, | |
2175 | frT, *frB, | |
2176 | fpscr_rn_round_towards_zero, 32); | |
2177 | FPSCR_END(Rc); | |
2178 | 0.63,6.FRT,11./,16.FRB,21.846,31.Rc:X:64,f::Floating Convert from Integer Doubleword | |
2179 | int sign = EXTRACTED64(*frB, 0, 0); | |
2180 | int exp = 63; | |
2181 | unsigned64 frac = *frB; | |
2182 | if (frac == 0) goto Zero_Operand; | |
2183 | if (sign == 1) frac = ~frac + 1; | |
2184 | while (EXTRACTED64(frac, 0, 0) == 0) { | |
2185 | /*??? do the loop 0 times if (FRB) = max negative integer */ | |
2186 | frac = INSERTED64(EXTRACTED64(frac, 1, 63), 0, 62); | |
2187 | exp = exp - 1; | |
2188 | } | |
2189 | Round_Float(processor, sign, &exp, &frac, FPSCR & fpscr_rn); | |
2190 | if (sign == 0) FPSCR_SET_FPRF(fpscr_rf_pos_normal_number); | |
2191 | if (sign == 1) FPSCR_SET_FPRF(fpscr_rf_pos_normal_number); | |
2192 | *frT = (INSERTED64(sign, 0, 0) | |
2193 | | INSERTED64(exp + 1023, 1, 11) | |
2194 | | INSERTED64(EXTRACTED64(frac, 1, 52), 12, 63)); | |
2195 | goto Done; | |
2196 | /**/ | |
2197 | Zero_Operand: | |
2198 | FPSCR_SET_FR(0); | |
2199 | FPSCR_SET_FI(0); | |
2200 | FPSCR_SET_FPRF(fpscr_rf_pos_zero); | |
2201 | *frT = 0; | |
2202 | goto Done; | |
2203 | /**/ | |
2204 | Done: | |
2205 | ||
2206 | # | |
2207 | # I.4.6.7 Floating-Point Compare Instructions | |
2208 | # | |
2209 | ||
2210 | 0.63,6.BF,9./,11.FRA,16.FRB,21.0,31./:X:f:fcmpu:Floating Compare Unordered | |
2211 | FPSCR_BEGIN; | |
2212 | unsigned c; | |
2213 | if (is_NaN(*frA, 0) || is_NaN(*frB, 0)) | |
2214 | c = cr_i_summary_overflow; /* 0b0001 - (FRA) ? (FRB) */ | |
2215 | else if (is_less_than(frA, frB)) | |
2216 | c = cr_i_negative; /* 0b1000 - (FRA) < (FRB) */ | |
2217 | else if (is_greater_than(frA, frB)) | |
2218 | c = cr_i_positive; /* 0b0100 - (FRA) > (FRB) */ | |
2219 | else | |
2220 | c = cr_i_zero; /* 0b0010 - (FRA) = (FRB) */ | |
2221 | FPSCR_SET_FPCC(c); | |
2222 | CR_SET(BF, c); /* CR[4*BF..4*BF+3] = c */ | |
2223 | if (is_SNaN(*frA, 0) || is_SNaN(*frB, 0)) | |
2224 | FPSCR_OR_VX(fpscr_vxsnan); | |
2225 | FPSCR_END(0); | |
2226 | 0.63,6.BF,9./,11.FRA,16.FRB,21.32,31./:X:f:fcmpo:Floating Compare Ordered | |
2227 | FPSCR_BEGIN; | |
2228 | unsigned c; | |
2229 | if (is_NaN(*frA, 0) || is_NaN(*frB, 0)) | |
2230 | c = cr_i_summary_overflow; /* 0b0001 - (FRA) ? (FRB) */ | |
2231 | else if (is_less_than(frA, frB)) | |
2232 | c = cr_i_negative; /* 0b1000 - (FRA) < (FRB) */ | |
2233 | else if (is_greater_than(frA, frB)) | |
2234 | c = cr_i_positive; /* 0b0100 - (FRA) > (FRB) */ | |
2235 | else | |
2236 | c = cr_i_zero; /* 0b0010 - (FRA) = (FRB) */ | |
2237 | FPSCR_SET_FPCC(c); | |
2238 | CR_SET(BF, c); /* CR[4*BF..4*BF+3] = c */ | |
2239 | if (is_SNaN(*frA, 0) || is_SNaN(*frB, 0)) { | |
2240 | FPSCR_OR_VX(fpscr_vxsnan); | |
2241 | if ((FPSCR & fpscr_ve) == 0) | |
2242 | FPSCR_OR_VX(fpscr_vxvc); | |
2243 | } | |
2244 | else if (is_QNaN(*frA, 0) || is_QNaN(*frB, 0)) { | |
2245 | FPSCR_OR_VX(fpscr_vxvc); | |
2246 | } | |
2247 | FPSCR_END(0); | |
2248 | ||
2249 | ||
2250 | # | |
2251 | # I.4.6.8 Floating-Point Status and Control Register Instructions | |
2252 | # | |
2253 | ||
2254 | 0.63,6.FRT,11./,16./,21.583,31.Rc:X:f::Move From FPSCR | |
2255 | 0.63,6.BF,9./,11.BFA,14./,16./,21.64,31./:X:f::Move to Condition Register from FPSCR | |
2256 | 0.64,6.BF,9./,11./,16.U,20./,21.134,31.Rc:X:f::Move To FPSCR Field Immediate | |
2257 | 0.63,6./,7.FLM,15./,16.FRB,21.711,31.Rc:XFL:f::Move To FPSCR Fields | |
2258 | 0.63,6.BT,11./,16./,21.70,31.Rc:X:f::Move To FPSCR Bit 0 | |
2259 | 0.63,6.BT,11./,16./,21.38,31.Rc:X:f::Move To FPSCR Bit 1 | |
2260 | ||
2261 | ||
2262 | # | |
2263 | # I.A.1.1 Floating-Point Store Instruction | |
2264 | # | |
2265 | 0.31,6.FRS,11.RA,16.RB,21.983,31./:X:f::Store Floating-Point as Integer Word Indexed | |
2266 | ||
2267 | # | |
2268 | # I.A.1.2 Floating-Point Arithmetic Instructions | |
2269 | # | |
2270 | ||
2271 | 0.63,6.FRT,11./,16.FRB,21./,26.22,31.Rc:A:f::Floating Square Root | |
2272 | 0.59,6.FRT,11./,16.FRB,21./,26.22,31.Rc:A:f::Floating Square Root Single | |
2273 | ||
2274 | 0.59,6.FRT,11./,16.FRB,21./,26.24,31.Rc:A:f::Floating Reciprocal Estimate Single | |
2275 | 0.63,6.FRT,11./,16.FRB,21./,26.26,31.Rc:A:f::Floating Reciprocal Square Root Estimate | |
2276 | ||
2277 | # | |
2278 | # I.A.1.3 Floating-Point Select Instruction | |
2279 | # | |
2280 | ||
2281 | 0.63,6.FRT,11.FRA,16.FRB,21.FRC,26.23,31.Rc:A:f::Floating Select | |
2282 | ||
2283 | ||
2284 | # | |
2285 | # II.3.2 Cache Management Instructions | |
2286 | # | |
2287 | ||
2288 | 0.31,6./,11.RA,16.RB,21.982,31./:X::icbi:Instruction Cache Block Invalidate | |
2289 | ; /* nop for now */ | |
2290 | ||
2291 | 0.19,6./,11./,16./,21.150,31./:XL::isync:Instruction Synchronize | |
2292 | cpu_synchronize_context(processor); | |
2293 | ||
2294 | ||
2295 | # | |
2296 | # II.3.2.2 Data Cache Instructions | |
2297 | # | |
2298 | ||
2299 | 0.31,6./,11.RA,16.RB,21.278,31./:X:::Data Cache Block Touch | |
056e975c MM |
2300 | ; /* nop for now */ |
2301 | ||
c143ef62 | 2302 | 0.31,6./,11.RA,16.RB,21.246,31./:X:::Data Cache Block Touch for Store |
056e975c MM |
2303 | ; /* nop for now */ |
2304 | ||
c143ef62 | 2305 | 0.31,6./,11.RA,16.RB,21.1014,31./:X:::Data Cache Block set to Zero |
056e975c MM |
2306 | ; /* nop for now */ |
2307 | ||
c143ef62 | 2308 | 0.31,6./,11.RA,16.RB,21.54,31./:X:::Data Cache Block Store |
056e975c MM |
2309 | ; /* nop for now */ |
2310 | ||
c143ef62 | 2311 | 0.31,6./,11.RA,16.RB,21.86,31./:X:::Data Cache Block Flush |
056e975c | 2312 | ; /* nop for now */ |
c143ef62 MM |
2313 | |
2314 | # | |
2315 | # II.3.3 Envorce In-order Execution of I/O Instruction | |
2316 | # | |
2317 | ||
2318 | 0.31,6./,11./,16./,21.854,31./:X::eieio:Enforce In-order Execution of I/O | |
2319 | /* Since this model has no instruction overlap | |
2320 | this instruction need do nothing */ | |
2321 | ||
2322 | # | |
2323 | # II.4.1 Time Base Instructions | |
2324 | # | |
2325 | ||
2326 | 0.31,6.RT,11.tbr,21.371,31./:XFX::mftb:Move From Time Base | |
2327 | int n = (tbr{5:9} << 5) | tbr{0:4}; | |
2328 | if (n == 268) { | |
2329 | if (is_64bit_implementation) *rT = TB; | |
2330 | else *rT = EXTRACTED64(TB, 32, 63); | |
2331 | } | |
2332 | else if (n == 269) { | |
2333 | if (is_64bit_implementation) *rT = EXTRACTED64(TB, 0, 31); | |
2334 | else *rT = EXTRACTED64(TB, 0, 31); | |
2335 | } | |
2336 | else | |
2337 | program_interrupt(processor, cia, | |
2338 | illegal_instruction_program_interrupt); | |
2339 | ||
2340 | ||
2341 | # | |
2342 | # III.2.3.1 System Linkage Instructions | |
2343 | # | |
2344 | ||
2345 | #0.17,6./,11./,16./,30.1,31./:SC:::System Call | |
2346 | 0.19,6./,11./,16./,21.50,31./:XL:::Return From Interrupt | |
2347 | ||
2348 | # | |
2349 | # III.3.4.1 Move to/from System Register Instructions | |
2350 | # | |
2351 | ||
2352 | #0.31,6.RS,11.spr,21.467,31./:XFX:::Move To Special Purpose Register | |
2353 | #0.31,6.RT,11.spr,21.339,31./:XFX:::Move From Special Purpose Register | |
2354 | 0.31,6.RS,11./,16./,21.146,31./:X:::Move To Machine State Register | |
2355 | if (IS_PROBLEM_STATE(processor)) | |
2356 | program_interrupt(processor, cia, | |
2357 | privileged_instruction_program_interrupt); | |
2358 | else | |
2359 | MSR = *rS; | |
2360 | 0.31,6.RT,11./,16./,21.83,31./:X:::Move From Machine State Register | |
2361 | if (IS_PROBLEM_STATE(processor)) | |
2362 | program_interrupt(processor, cia, | |
2363 | privileged_instruction_program_interrupt); | |
2364 | else | |
2365 | *rT = MSR; | |
2366 | ||
2367 | ||
2368 | # | |
2369 | # III.4.11.1 Cache Management Instructions | |
2370 | # | |
2371 | ||
2372 | 0.31,6./,11.RA,16.RB,21.470,31./:X::dcbi:Data Cache Block Invalidate | |
2373 | ; /* nop for now */ | |
2374 | ||
2375 | # | |
2376 | # III.4.11.2 Segment Register Manipulation Instructions | |
2377 | # | |
2378 | ||
2379 | 0.31,6.RS,11./,12.SR,16./,21.210,31./:X:32:mtsr %SR,%RS:Move To Segment Register | |
2380 | if (IS_PROBLEM_STATE(processor)) | |
2381 | program_interrupt(processor, cia, | |
2382 | privileged_instruction_program_interrupt); | |
2383 | else | |
2384 | SEGREG(SR) = *rS; | |
2385 | 0.31,6.RS,11./,16.RB,21.242,31./:X:32:mtsrin %RS,%RB:Move To Segment Register Indirect | |
2386 | if (IS_PROBLEM_STATE(processor)) | |
2387 | program_interrupt(processor, cia, | |
2388 | privileged_instruction_program_interrupt); | |
2389 | else | |
2390 | SEGREG(EXTRACTED32(*rB, 0, 3)) = *rS; | |
2391 | 0.31,6.RT,11./,12.SR,16./,21.595,31./:X:32:mfsr %RT,%RS:Move From Segment Register | |
2392 | if (IS_PROBLEM_STATE(processor)) | |
2393 | program_interrupt(processor, cia, | |
2394 | privileged_instruction_program_interrupt); | |
2395 | else | |
2396 | *rT = SEGREG(SR); | |
2397 | 0.31,6.RT,11./,16.RB,21.659,31./:X:32:mfsrin %RT,%RB:Move From Segment Register Indirect | |
2398 | if (IS_PROBLEM_STATE(processor)) | |
2399 | program_interrupt(processor, cia, | |
2400 | privileged_instruction_program_interrupt); | |
2401 | else | |
2402 | *rT = SEGREG(EXTRACTED32(*rB, 0, 3)); | |
2403 | ||
2404 | ||
2405 | # | |
2406 | # III.4.11.3 Lookaside Buffer Management Instructions (Optional) | |
2407 | # | |
2408 | ||
2409 | 0.31,6./,11./,16.RB,21.434,31./:X:64::SLB Invalidate Entry | |
2410 | 0.31,6./,11./,16./,21.498,31./:X:64::SLB Invalidate All | |
2411 | ||
2412 | 0.31,6./,11./,16.RB,21.306,31./:X:::TLB Invalidate Entry | |
2413 | 0.31,6./,11./,16./,21.370,31./:X:::TLB Invalidate All | |
2414 | ||
2415 | 0.31,6./,11./,16./,21.566,31./:X:::TLB Sychronize | |
2416 | ||
2417 | ||
2418 | # | |
2419 | # III.A.1.2 External Access Instructions | |
2420 | # | |
2421 | ||
2422 | 0.31,6.RT,11.RA,16.RB,21.310,31./:X:earwax::External Control In Word Indexed | |
2423 | 0.31,6.RS,11.RA,16.RB,21.438,31./:X:earwax::External Control Out Word Indexed |