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* ld-srec/srec.exp: New tests.
[deliverable/binutils-gdb.git] / sim / ppc / ppc-instructions
CommitLineData
c143ef62
MM		 1#
2# This file is part of the program psim.
3#
4# Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au>
5#
6# --
7#
8# The pseudo-code that appears below, translated into C, was copied
9# by Andrew Cagney of Moss Vale, Australia.
10#
11# This pseudo-code is copied by permission from the publication
12# "The PowerPC Architecture: A Specification for A New Family of
13# RISC Processors" (ISBN 1-55860-316-6) copyright 1993, 1994 by
14# International Business Machines Corporation.
15#
16# THIS PERMISSION IS PROVIDED WITHOUT WARRANTY OF ANY KIND, EITHER
17# EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO IMPLIED WARRANTIES
18# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
19#
20# --
21#
22# This program is free software; you can redistribute it and/or modify
23# it under the terms of the GNU General Public License as published by
24# the Free Software Foundation; either version 2 of the License, or
25# (at your option) any later version.
26#
27# This program is distributed in the hope that it will be useful,
28# but WITHOUT ANY WARRANTY; without even the implied warranty of
29# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30# GNU General Public License for more details.
31#
32# You should have received a copy of the GNU General Public License
33# along with this program; if not, write to the Free Software
34# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
35#
36# --
37#
38#
39# Fields:
40#
41# 1 Instruction format as a `start-bit,content' pairs.
42# the content is one of a digit, field name or `/' (aka.0)
43#
44# 2 Format specifier
45#
46# 3 Flags: 64 - 64bit only
47# f - floating point enabled required
48#
49# 4 short name
50#
51# 5 Description
52#
28816f45
MM		 53#
54# For flags marked 'model', the fields are interpreted as follows:
55#
56# 1 Not used
57#
58# 2 Not used
59#
60# 3 "macro"
61#
62# 4 String name for model
63#
64# 5 Specific CPU model, must be an identifier
65#
66# 6 Comma separated list of functional units
67
68# Flags for model.h
69::model-macro:::#define PPC_LOAD 0x00000001
70::model-macro:::#define PPC_STORE 0x00000002
71::model-macro:::#define PPC_SERIALIZE 0x00000004
72
73# PowerPC models
74::model:604:PPC604:SCIU=2 single cycle integer,MCIU=1 multiple cycle integer,FPU=1 floating point,LSU=1 memory,BPU=1 branch
75::model:603e:PPC603e:IU=1 integer,FPU=1 floating point,LSU=1 memory,SRU=1 system register,BPU=1 branch
76::model:603:PPC603:IU=1 integer,FPU=1 floating point,LSU=1 memory,SRU=1 system register,BPU=1 branch
77
eb4ef197
MM		 78void::model-function::model_init:void
79void::model-function::model_halt:void
80void::model-function::model_print_info:void
c143ef62
MM		 81
82# The following (illegal) instruction is `known' by gen and is
83# called when ever an illegal instruction is encountered
84::internal::illegal
85 program_interrupt(processor, cia,
86 illegal_instruction_program_interrupt);
87 return 0;
88
89
90# The following (floating point unavailable) instruction is `known' by gen
91# and is called when ever an a floating point instruction is to be
92# executed but floating point is make unavailable by the MSR
93::internal::floating_point_unavailable
94 floating_point_unavailable_interrupt(processor, cia);
95 return 0;
96
97
98#
99# Floating point support functions
100#
101
102# Convert 32bit single to 64bit double
103unsigned64::function::DOUBLE:unsigned32 WORD
104 unsigned64 FRT;
105 if (EXTRACTED32(WORD, 1, 8) > 0
106 && EXTRACTED32(WORD, 1, 8) < 255) {
107 /* normalized operand */
108 int not_word_1_1 = !EXTRACTED32(WORD, 1, 1); /*2.6.3 bug*/
109 FRT = (INSERTED64(EXTRACTED32(WORD, 0, 1), 0, 1)
110 | INSERTED64(not_word_1_1, 2, 2)
111 | INSERTED64(not_word_1_1, 3, 3)
112 | INSERTED64(not_word_1_1, 4, 4)
113 | INSERTED64(EXTRACTED32(WORD, 2, 31), 5, (63 - 29)));
114 }
115 else if (EXTRACTED32(WORD, 1, 8) == 0
116 && EXTRACTED32(WORD, 9, 31) != 0) {
117 /* denormalized operand */
118 int sign = EXTRACTED32(WORD, 0, 0);
119 int exp = -126;
120 unsigned64 frac = INSERTED64(EXTRACTED32(WORD, 9, 31), 1, (52 - 29));
121 /* normalize the operand */
122 while (MASKED64(frac, 0, 0) == 0) {
123 frac <<= 1;
124 exp -= 1;
125 }
126 FRT = (INSERTED64(sign, 0, 0)
127 | INSERTED64(exp + 1023, 1, 11)
128 | INSERTED64(EXTRACTED64(frac, 1, 52), 12, 63));
129 }
130 else if (EXTRACTED32(WORD, 1, 8) == 255
131 || EXTRACTED32(WORD, 1, 31) == 0) {
132 FRT = (INSERTED64(EXTRACTED32(WORD, 0, 1), 0, 1)
133 | INSERTED64(EXTRACTED32(WORD, 1, 1), 2, 2)
134 | INSERTED64(EXTRACTED32(WORD, 1, 1), 3, 3)
135 | INSERTED64(EXTRACTED32(WORD, 1, 1), 4, 4)
136 | INSERTED64(EXTRACTED32(WORD, 2, 31), 5, (63 - 29)));
137 }
138 else {
139 error("DOUBLE - unknown case\n");
140 FRT = 0;
141 }
142 return FRT;
143
144# Convert 64bit single to 32bit double
145unsigned32::function::SINGLE:unsigned64 FRS
146 unsigned32 WORD;
147 if (EXTRACTED64(FRS, 1, 11) > 896
148 || EXTRACTED64(FRS, 1, 63) == 0) {
149 /* no denormalization required (includes Zero/Infinity/NaN) */
150 WORD = (INSERTED32(EXTRACTED64(FRS, 0, 1), 0, 1)
151 | INSERTED32(EXTRACTED64(FRS, 5, 34), 2, 31));
152 }
153 else if (874 <= EXTRACTED64(FRS, 1, 11)
154 && EXTRACTED64(FRS, 1, 11) <= 896) {
155 /* denormalization required */
156 int sign = EXTRACTED64(FRS, 0, 0);
157 int exp = EXTRACTED64(FRS, 1, 11) - 1023;
158 unsigned64 frac = (BIT64(0)
159 | INSERTED64(EXTRACTED64(FRS, 12, 63), 1, 52));
160 /* denormalize the operand */
161 while (exp < -126) {
162 frac = INSERTED64(EXTRACTED64(frac, 0, 62), 1, 63);
163 exp += 1;
164 }
165 WORD = (INSERTED32(sign, 0, 0)
166 | INSERTED32(0x00, 1, 8)
167 | INSERTED32(EXTRACTED64(frac, 1, 23), 9, 31));
168 }
169 else {
170 WORD = 0x0; /* ??? */
171 }
172 return WORD;
173
174
175# round 64bit double to 64bit but single
176void::function::Round_Single:cpu *processor, int sign, int *exp, unsigned64 *frac_grx
177 /* comparisons ignore u bits */
178 unsigned64 out;
179 int inc = 0;
180 int lsb = EXTRACTED64(*frac_grx, 23, 23);
181 int gbit = EXTRACTED64(*frac_grx, 24, 24);
182 int rbit = EXTRACTED64(*frac_grx, 25, 25);
183 int xbit = EXTRACTED64(*frac_grx, 26, 55) != 0;
184 if ((FPSCR & fpscr_rn) == fpscr_rn_round_to_nearest) {
185 if (lsb == 1 && gbit == 1) inc = 1;
186 if (lsb == 0 && gbit == 1 && rbit == 1) inc = 1;
187 if (lsb == 0 && gbit == 1 && xbit == 1) inc = 1;
188 }
189 if ((FPSCR & fpscr_rn) == fpscr_rn_round_towards_pos_infinity) {
190 if (sign == 0 && gbit == 1) inc = 1;
191 if (sign == 0 && rbit == 1) inc = 1;
192 if (sign == 0 && xbit == 1) inc = 1;
193 }
194 if ((FPSCR & fpscr_rn) == fpscr_rn_round_towards_neg_infinity) {
195 if (sign == 1 && gbit == 1) inc = 1;
196 if (sign == 1 && rbit == 1) inc = 1;
197 if (sign == 1 && xbit == 1) inc = 1;
198 }
199 /* work out addition in low 25 bits of out */
200 out = EXTRACTED64(*frac_grx, 0, 23) + inc;
201 *frac_grx = INSERTED64(out, 0, 23);
202 if (out & BIT64(64 - 23 - 1 - 1)) {
203 *frac_grx = (BIT64(0) |
204 INSERTED64(EXTRACTED64(*frac_grx, 0, 22), 1, 23));
205 *exp = *exp + 1;
206 }
207 /* frac_grx[24:52] = 0 already */
208 FPSCR_SET_FR(inc);
209 FPSCR_SET_FI(gbit || rbit || xbit);
210
211
212#
213void::function::Round_Integer:cpu *processor, int sign, unsigned64 *frac, int *frac64, int gbit, int rbit, int xbit, fpscreg round_mode
214 int inc = 0;
215 if (round_mode == fpscr_rn_round_to_nearest) {
216 if (*frac64 == 1 && gbit == 1) inc = 1;
217 if (*frac64 == 0 && gbit == 1 && rbit == 1) inc = 1;
218 if (*frac64 == 0 && gbit == 1 && xbit == 1) inc = 1;
219 }
220 if (round_mode == fpscr_rn_round_towards_pos_infinity) {
221 if (sign == 0 && gbit == 1) inc = 1;
222 if (sign == 0 && rbit == 1) inc = 1;
223 if (sign == 0 && xbit == 1) inc = 1;
224 }
225 if (round_mode == fpscr_rn_round_towards_neg_infinity) {
226 if (sign == 1 && gbit == 1) inc = 1;
227 if (sign == 1 && rbit == 1) inc = 1;
228 if (sign == 1 && xbit == 1) inc = 1;
229 }
230 /* frac[0:64] = frac[0:64} + inc */
231 *frac += (*frac64 && inc ? 1 : 0);
232 *frac64 = (*frac64 + inc) & 0x1;
233 FPSCR_SET_FR(inc);
234 FPSCR_SET_FI(gbit | rbit | xbit);
235
236
237void::function::Round_Float:cpu *processor, int sign, int *exp, unsigned64 *frac, fpscreg round_mode
238 int carry_out;
239 int inc = 0;
240 int lsb = EXTRACTED64(*frac, 52, 52);
241 int gbit = EXTRACTED64(*frac, 53, 53);
242 int rbit = EXTRACTED64(*frac, 54, 54);
243 int xbit = EXTRACTED64(*frac, 55, 55);
244 if (round_mode == fpscr_rn_round_to_nearest) {
245 if (lsb == 1 && gbit == 1) inc = 1;
246 if (lsb == 0 && gbit == 1 && rbit == 1) inc = 1;
247 if (lsb == 0 && gbit == 1 && xbit == 1) inc = 1;
248 }
249 if (round_mode == fpscr_rn_round_towards_pos_infinity) {
250 if (sign == 0 && gbit == 1) inc = 1;
251 if (sign == 0 && rbit == 1) inc = 1;
252 if (sign == 0 && xbit == 1) inc = 1;
253 }
254 if (round_mode == fpscr_rn_round_towards_neg_infinity) {
255 if (sign == 1 && gbit == 1) inc = 1;
256 if (sign == 1 && rbit == 1) inc = 1;
257 if (sign == 1 && xbit == 1) inc = 1;
258 }
259 /* frac//carry_out = frac + inc */
260 *frac = (*frac >> 1) + (INSERTED64(inc, 52, 52) >> 1);
261 carry_out = EXTRACTED64(*frac, 0, 0);
262 *frac <<= 1;
263 if (carry_out == 1) *exp = *exp + 1;
264 FPSCR_SET_FR(inc);
265 FPSCR_SET_FI(gbit | rbit | xbit);
266 FPSCR_SET_XX(FPSCR & fpscr_fi);
267
268
269# conversion of FP to integer
270void::function::convert_to_integer:cpu *processor, unsigned_word cia, unsigned64 *frt, unsigned64 frb, fpscreg round_mode, int tgt_precision
271 int i;
272 int exp = 0;
273 unsigned64 frac = 0;
274 int frac64 = 0;
275 int gbit = 0;
276 int rbit = 0;
277 int xbit = 0;
278 int sign = EXTRACTED64(frb, 0, 0);
279 if (EXTRACTED64(frb, 1, 11) == 2047 && EXTRACTED64(frb, 12, 63) == 0)
280 goto Infinity_Operand;
281 if (EXTRACTED64(frb, 1, 11) == 2047 && EXTRACTED64(frb, 12, 12) == 0)
282 goto SNaN_Operand;
283 if (EXTRACTED64(frb, 1, 11) == 2047 && EXTRACTED64(frb, 12, 12) == 1)
284 goto QNaN_Operand;
285 if (EXTRACTED64(frb, 1, 11) > 1086) goto Large_Operand;
286 if (EXTRACTED64(frb, 1, 11) > 0) exp = EXTRACTED64(frb, 1, 11) - 1023;
287 if (EXTRACTED64(frb, 1, 11) == 0) exp = -1022;
288 if (EXTRACTED64(frb, 1, 11) > 0) { /* normal */
289 frac = BIT64(1) | INSERTED64(EXTRACTED64(frb, 12, 63), 2, 53);
290 frac64 = 0;
291 }
292 if (EXTRACTED64(frb, 1, 11) == 0) { /* denorm */
293 frac = INSERTED64(EXTRACTED64(frb, 12, 63), 2, 53);
294 frac64 = 0;
295 }
296 gbit = 0, rbit = 0, xbit = 0;
297 for (i = 1; i <= 63 - exp; i++) {
298 xbit = rbit | xbit;
299 rbit = gbit;
300 gbit = frac64;
301 frac64 = EXTRACTED64(frac, 63, 63);
302 frac = INSERTED64(EXTRACTED64(frac, 0, 62), 1, 63);
303 }
304 Round_Integer(processor, sign, &frac, &frac64, gbit, rbit, xbit, round_mode);
305 if (sign == 1) { /* frac[0:64] = ~frac[0:64] + 1 */
306 frac = ~frac;
307 frac64 ^= 1;
308 frac += (frac64 ? 1 : 0);
309 frac64 = (frac64 + 1) & 0x1;
310 }
311 if (tgt_precision == 32 /* can ignore frac64 in compare */
312 && (signed64)frac > (signed64)MASK64(33+1, 63)/*2^31-1 >>1*/)
313 goto Large_Operand;
314 if (tgt_precision == 64 /* can ignore frac64 in compare */
315 && (signed64)frac > (signed64)MASK64(1+1, 63)/*2^63-1 >>1*/)
316 goto Large_Operand;
317 if (tgt_precision == 32 /* can ignore frac64 in compare */
318 && (signed64)frac < (signed64)MASK64(0, 32+1)/*-2^31 >>1*/)
319 goto Large_Operand;
320 if (tgt_precision == 64 /* can ignore frac64 in compare */
321 && (signed64)frac < (signed64)MASK64(0, 0+1)/*-2^63 >>1*/)
322 goto Large_Operand;
323 FPSCR_SET_XX(FPSCR & fpscr_fi);
324 if (tgt_precision == 32)
325 *frt = MASKED64(*frt, 0, 31) | (EXTRACTED64(frac, 33, 63) << 1) | frac64;
326 if (tgt_precision == 64)
327 *frt = (EXTRACTED64(frac, 1, 63) << 1) | frac64;
328 /*FPSCR[fprf] = undefined */
329 goto Done;
330 /**/
331 Infinity_Operand:
332 FPSCR_SET_FR(0);
333 FPSCR_SET_FI(0);
334 FPSCR_OR_VX(fpscr_vxcvi);
335 if ((FPSCR & fpscr_ve) == 0) {
336 if (tgt_precision == 32) {
337 if (sign == 0) *frt = MASKED64(*frt, 0, 31) | 0x7FFFFFFF;
338 if (sign == 1) *frt = MASKED64(*frt, 0, 31) | 0x80000000;
339 }
340 else {
341 if (sign == 0) *frt = MASK64(1, 63); /*0x7FFF_FFFF_FFFF_FFFF*/
342 if (sign == 1) *frt = BIT64(0); /*0x8000_0000_0000_0000*/
343 }
344 /* FPSCR[FPRF] = undefined */
345 }
346 goto Done;
347 /**/
348 SNaN_Operand:
349 FPSCR_SET_FR(0);
350 FPSCR_SET_FI(0);
351 FPSCR_OR_VX(fpscr_vxsnan | fpscr_vxcvi);
352 if ((FPSCR & fpscr_ve) == 0) {
353 if (tgt_precision == 32) *frt = MASKED64(*frt, 0, 31) | 0x80000000;
354 if (tgt_precision == 64) *frt = BIT64(0); /*0x8000_0000_0000_0000*/
355 /* FPSCR[fprf] = undefined */
356 }
357 goto Done;
358 /**/
359 QNaN_Operand:
360 FPSCR_SET_FR(0);
361 FPSCR_SET_FI(0);
362 FPSCR_OR_VX(fpscr_vxcvi);
363 if ((FPSCR & fpscr_ve) == 0) {
364 if (tgt_precision == 32) *frt = MASKED64(*frt, 0, 31) | 0x80000000;
365 if (tgt_precision == 64) *frt = BIT64(0);/*0x8000_0000_0000_0000*/
366 /* FPSCR[fprf] = undefined */
367 }
368 goto Done;
369 /**/
370 Large_Operand:
371 FPSCR_SET_FR(0);
372 FPSCR_SET_FI(0);
373 FPSCR_OR_VX(fpscr_vxcvi);
374 if ((FPSCR & fpscr_ve) == 0) {
375 if (tgt_precision == 32) {
376 if (sign == 0) *frt = MASKED64(*frt, 0, 31) | 0x7fffffff;
377 if (sign == 1) *frt = MASKED64(*frt, 0, 31) | 0x80000000;
378 }
379 else {
380 if (sign == 0) *frt = MASK64(1, 63); /*0x7FFF_FFFF_FFFF_FFFF*/
381 if (sign == 1) *frt = BIT64(0); /*0x8000_0000_0000_0000*/
382 }
383 /* FPSCR[fprf] = undefined */
384 }
385 /**/
386 Done:
387
388
389# extract out raw fields of a FP number
390int::function::sign:unsigned64 FRS
391 return (MASKED64(FRS, 0, 0)
392 ? -1
393 : 1);
394int::function::biased_exp:unsigned64 frs, int single
395 if (single)
396 return EXTRACTED64(frs, 1, 8);
397 else
398 return EXTRACTED64(frs, 1, 11);
399unsigned64::function::fraction:unsigned64 frs, int single
400 if (single)
401 return EXTRACTED64(frs, 9, 31);
402 else
403 return EXTRACTED64(frs, 12, 63);
404
405# a number?, each of the below return +1 or -1 (based on sign bit)
406# if true.
407int::function::is_nor:unsigned64 frs, int single
408 int exp = biased_exp(frs, single);
409 return (exp >= 1
410 && exp <= (single ? 254 : 2046));
411int::function::is_zero:unsigned64 FRS
412 return (MASKED64(FRS, 1, 63) == 0
413 ? sign(FRS)
414 : 0);
415int::function::is_den:unsigned64 frs, int single
416 int exp = biased_exp(frs, single);
417 unsigned64 frac = fraction(frs, single);
418 return (exp == 0 && frac != 0
419 ? sign(frs)
420 : 0);
421int::function::is_inf:unsigned64 frs, int single
422 int exp = biased_exp(frs, single);
423 int frac = fraction(frs, single);
424 return (exp == (single ? 255 : 2047) && frac == 0
425 ? sign(frs)
426 : 0);
427int::function::is_NaN:unsigned64 frs, int single
428 int exp = biased_exp(frs, single);
429 int frac = fraction(frs, single);
430 return (exp == (single ? 255 : 2047) && frac != 0
431 ? sign(frs)
432 : 0);
433int::function::is_SNaN:unsigned64 frs, int single
434 return (is_NaN(frs, single)
435 && !(frs & (single ? MASK64(9, 9) : MASK64(12, 12)))
436 ? sign(frs)
437 : 0);
438int::function::is_QNaN:unsigned64 frs, int single
439 return (is_NaN(frs, single) && !is_SNaN(frs, single));
440int::function::is_less_than:unsigned64 *fra, unsigned64 *frb
441 return *(double*)fra < *(double*)frb;
442int::function::is_greater_than:unsigned64 *fra, unsigned64 *frb
443 return *(double*)fra > *(double*)frb;
444int::function::is_equan_to:unsigned64 *fra, unsigned64 *frb
445 return *(double*)fra == *(double*)frb;
446
447
448# which quiet nan should become the result
449unsigned64::function::select_qnan:unsigned64 fra, unsigned64 frb, unsigned64 frc, int instruction_is_frsp, int generate_qnan, int single
450 unsigned64 frt = 0;
451 if (is_NaN(fra, single))
452 frt = fra;
453 else if (is_NaN(frb, single))
454 if (instruction_is_frsp)
455 frt = MASKED64(frb, 0, 34);
456 else
457 frt = frb;
458 else if (is_NaN(frc, single))
459 frt = frc;
460 else if (generate_qnan)
461 frt = MASK64(1, 12); /* 0x7FF8_0000_0000_0000 */
462 else
463 error("select_qnan - default reached\n");
464 return frt;
465
466
467# detect invalid operation
468int::function::is_invalid_operation:cpu *processor, unsigned_word cia, unsigned64 fra, unsigned64 frb, fpscreg check, int single, int negate
469 int fail = 0;
470 if ((check & fpscr_vxsnan)
471 && (is_SNaN(fra, single) || is_SNaN(frb, single))) {
472 FPSCR_OR_VX(fpscr_vxsnan);
473 fail = 1;
474 }
475 if ((check & fpscr_vxisi)
476 && (is_inf(fra, single) && is_inf(frb, single))
477 && ((negate && sign(fra) != sign(frb))
478 || (!negate && sign(fra) == sign(frb)))) {
479 /*FIXME: don't handle inf-inf VS inf+-inf */
480 FPSCR_OR_VX(fpscr_vxisi);
481 fail = 1;
482 }
483 if ((check & fpscr_vxidi)
484 && (is_inf(fra, single) && is_inf(frb, single))) {
485 FPSCR_OR_VX(fpscr_vxidi);
486 fail = 1;
487 }
488 if ((check & fpscr_vxzdz)
489 && (is_zero(fra) && is_zero(frb))) {
490 FPSCR_OR_VX(fpscr_vxzdz);
491 fail = 1;
492 }
493 if ((check & fpscr_vximz)
494 && (is_zero(fra) && is_inf(frb, single))) {
495 FPSCR_OR_VX(fpscr_vximz);
496 fail = 1;
497 }
498 if ((check & fpscr_vxvc)
499 && (is_NaN(fra, single) || is_NaN(frb, single))) {
500 FPSCR_OR_VX(fpscr_vxvc);
501 fail = 1;
502 }
503 if ((check & fpscr_vxsoft)) {
504 FPSCR_OR_VX(fpscr_vxsoft);
505 fail = 1;
506 }
507 if ((check & fpscr_vxsqrt)
508 && sign(fra) < 0) {
509 FPSCR_OR_VX(fpscr_vxsqrt);
510 fail = 1;
511 }
512 /* if ((check && fpscr_vxcvi) {
513 && (is_inf(fra, single) || is_NaN(fra, single) || is_large(fra, single)))
514 FPSCR_OR_VX(fpscr_vxcvi);
515 fail = 1;
516 }
517 */
518 return fail;
519
520
521
522
523
524# handle case of invalid operation
525void::function::invalid_arithemetic_operation:cpu *processor, unsigned_word cia, unsigned64 *frt, unsigned64 fra, unsigned64 frb, unsigned64 frc, int instruction_is_frsp, int instruction_is_convert_to_64bit, int instruction_is_convert_to_32bit, int single
526 if (FPSCR & fpscr_ve) {
527 /* invalid operation exception enabled */
528 /* FRT unchaged */
529 FPSCR_SET_FR(0);
530 FPSCR_SET_FI(0);
531 /* fpscr_FPRF unchanged */
532 }
533 else {
534 /* invalid operation exception disabled */
535 if (instruction_is_convert_to_64bit) {
536 error("oopsi");
537 }
538 else if (instruction_is_convert_to_32bit) {
539 error("oopsi");
540 }
541 else { /* arrith, frsp */
542 *frt = select_qnan(fra, frb, frc,
543 instruction_is_frsp, 0/*generate*/, single);
544 FPSCR_SET_FR(0);
545 FPSCR_SET_FI(0);
546 FPSCR_SET_FPRF(fpscr_rf_quiet_nan);
547 }
548 }
549
550
551
552
553#
554# I.2.4.1 Branch Instructions
555#
5560.18,6.LI,30.AA,31.LK:I:t::Branch
28816f45
MM		 557*PPC603:PPC603_BPU:1:1:0
558*PPC603e:PPC603_BPU:1:1:0
559*PPC604:PPC603_BPU:1:1:0
c143ef62
MM		 560 if (AA) NIA = IEA(EXTS(LI_0b00));
561 else NIA = IEA(CIA + EXTS(LI_0b00));
562 if (LK) LR = (spreg)CIA+4;
5630.16,6.BO,11.BI,16.BD,30.AA,31.LK:B:t::Branch Conditional
28816f45
MM		 564*PPC603:PPC603_BPU:1:1:0
565*PPC603e:PPC603_BPU:1:1:0
566*PPC604:PPC603_BPU:1:1:0
c143ef62
MM		 567 int M, ctr_ok, cond_ok;
568 if (is_64bit_implementation && is_64bit_mode) M = 0;
569 else M = 32;
570 if (!BO{2}) CTR = CTR - 1;
571 ctr_ok = BO{2} || ((MASKED(CTR, M, 63) != 0) != (BO{3}));
572 cond_ok = BO{0} || ((CR{BI}) == (BO{1}));
573 if (ctr_ok && cond_ok)
574 if (AA) NIA = IEA(EXTS(BD_0b00));
575 else NIA = IEA(CIA + EXTS(BD_0b00));
576 if (LK) LR = (spreg)IEA(CIA + 4);
5770.19,6.BO,11.BI,16./,21.16,31.LK:XL:t::Branch Conditional to Link Register
28816f45
MM		 578*PPC603:PPC603_BPU:1:1:0
579*PPC603e:PPC603_BPU:1:1:0
580*PPC604:PPC603_BPU:1:1:0
c143ef62
MM		 581 int M, ctr_ok, cond_ok;
582 if (is_64bit_implementation && is_64bit_mode) M = 0;
583 else M = 32;
584 if (!BO{2}) CTR = CTR - 1;
585 ctr_ok = BO{2} || ((MASKED(CTR, M, 63) != 0) != BO{3});
586 cond_ok = BO{0} || (CR{BI} == BO{1});
587 if (ctr_ok && cond_ok) NIA = IEA(LR_0b00);
588 if (LK) LR = (spreg)IEA(CIA + 4);
5890.19,6.BO,11.BI,16./,21.528,31.LK:XL:t::Branch Conditional to Count Register
28816f45
MM		 590*PPC603:PPC603_BPU:1:1:0
591*PPC603e:PPC603_BPU:1:1:0
592*PPC604:PPC603_BPU:1:1:0
c143ef62
MM		 593 int cond_ok;
594 cond_ok = BO{0} || (CR{BI} == BO{1});
595 if (cond_ok) NIA = IEA(CTR_0b00);
596 if (LK) LR = (spreg)IEA(CIA + 4);
597
598#
599# I.2.4.2 System Call Instruction
600#
6010.17,6./,11./,16./,30.1,31./:SC:t::System Call
602 system_call_interrupt(processor, cia);
603
604#
605# I.2.4.3 Condition Register Logical Instructions
606#
6070.19,6.BT,11.BA,16.BB,21.257,31./:XL::crand:Condition Register AND
608 BLIT32(CR, BT, CR{BA} && CR{BB});
6090.19,6.BT,11.BA,16.BB,21.449,31./:XL::cror:Condition Register OR
610 BLIT32(CR, BT, CR{BA} || CR{BB});
6110.19,6.BT,11.BA,16.BB,21.193,31./:XL::crxor:Condition Register XOR
612 BLIT32(CR, BT, CR{BA} != CR{BB});
6130.19,6.BT,11.BA,16.BB,21.225,31./:XL::crnand:Condition Register NAND
614 BLIT32(CR, BT, !(CR{BA} && CR{BB}));
6150.19,6.BT,11.BA,16.BB,21.33,31./:XL::crnor:Condition Register NOR
616 BLIT32(CR, BT, !(CR{BA} || CR{BB}));
6170.19,6.BT,11.BA,16.BB,21.289,31./:XL::creqv:Condition Register Equivalent
618 BLIT32(CR, BT, CR{BA} == CR{BB});
6190.19,6.BT,11.BA,16.BB,21.129,31./:XL::crandc:Condition Register AND with Complement
620 BLIT32(CR, BT, CR{BA} && !CR{BB});
6210.19,6.BT,11.BA,16.BB,21.417,31./:XL::crorc:Condition Register OR with Complement
622 BLIT32(CR, BT, CR{BA} || !CR{BB});
623
624#
625# I.2.4.4 Condition Register Field Instruction
626#
6270.19,6.BF,9./,11.BFA,14./,16./,21.0,31./:XL:::Move Condition Register Field
628 MBLIT32(CR, 4*BF, 4*BF+3, EXTRACTED32(CR, 4*BFA, 4*BFA+3));
629
630
631#
632# I.3.3.2 Fixed-Point Load Instructions
633#
634
6350.34,6.RT,11.RA,16.D:D:::Load Byte and Zero
636 unsigned_word b;
637 unsigned_word EA;
638 if (RA == 0) b = 0;
639 else b = *rA;
640 EA = b + EXTS(D);
641 *rT = MEM(unsigned, EA, 1);
6420.31,6.RT,11.RA,16.RB,21.87,31./:X:::Load Byte and Zero Indexed
643 unsigned_word b;
644 unsigned_word EA;
645 if (RA == 0) b = 0;
646 else b = *rA;
647 EA = b + *rB;
648 *rT = MEM(unsigned, EA, 1);
6490.35,6.RT,11.RA,16.D:D:::Load Byte and Zero with Update
650 unsigned_word EA;
651 if (RA == 0 || RA == RT)
652 program_interrupt(processor, cia,
653 illegal_instruction_program_interrupt);
654 EA = *rA + EXTS(D);
655 *rT = MEM(unsigned, EA, 1);
656 *rA = EA;
6570.31,6.RT,11.RA,16.RB,21.119,31./:X:::Load Byte and Zero with Update Indexed
658 unsigned_word EA;
659 if (RA == 0 || RA == RT)
660 program_interrupt(processor, cia,
661 illegal_instruction_program_interrupt);
662 EA = *rA + *rB;
663 *rT = MEM(unsigned, EA, 1);
664 *rA = EA;
665
6660.40,6.RT,11.RA,16.D:D:::Load Halfword and Zero
667 unsigned_word b;
668 unsigned_word EA;
669 if (RA == 0) b = 0;
670 else b = *rA;
671 EA = b + EXTS(D);
672 *rT = MEM(unsigned, EA, 2);
6730.31,6.RT,11.RA,16.RB,21.279,31./:X:::Load Halfword and Zero Indexed
674 unsigned_word b;
675 unsigned_word EA;
676 if (RA == 0) b = 0;
677 else b = *rA;
678 EA = b + *rB;
679 *rT = MEM(unsigned, EA, 2);
6800.41,6.RT,11.RA,16.D:D:::Load Halfword and Zero with Update
681 unsigned_word EA;
682 if (RA == 0 || RA == RT)
683 program_interrupt(processor, cia,
684 illegal_instruction_program_interrupt);
685 EA = *rA + EXTS(D);
686 *rT = MEM(unsigned, EA, 2);
687 *rA = EA;
6880.31,6.RT,11.RA,16.RB,21.311,31./:X:::Load Halfword and Zero with Update Indexed
689 unsigned_word EA;
690 if (RA == 0 || RA == RT)
691 program_interrupt(processor, cia,
692 illegal_instruction_program_interrupt);
693 EA = *rA + *rB;
694 *rT = MEM(unsigned, EA, 2);
695 *rA = EA;
696
6970.42,6.RT,11.RA,16.D:D:::Load Halfword Algebraic
698 unsigned_word b;
699 unsigned_word EA;
700 if (RA == 0) b = 0;
701 else b = *rA;
702 EA = b + EXTS(D);
703 *rT = MEM(signed, EA, 2);
7040.31,6.RT,11.RA,16.RB,21.343,31./:X:::Load Halfword Algebraic Indexed
705 unsigned_word b;
706 unsigned_word EA;
707 if (RA == 0) b = 0;
708 else b = *rA;
709 EA = b + *rB;
710 *rT = MEM(signed, EA, 2);
7110.43,6.RT,11.RA,16.D:D:::Load Halfword Algebraic with Update
712 unsigned_word EA;
713 if (RA == 0 || RA == RT)
714 program_interrupt(processor, cia,
715 illegal_instruction_program_interrupt);
716 EA = *rA + EXTS(D);
717 *rT = MEM(signed, EA, 2);
7180.31,6.RT,11.RA,16.RB,21.375,31./:X:::Load Halfword Algebraic with Update Indexed
719 unsigned_word EA;
720 if (RA == 0 || RA == RT)
721 program_interrupt(processor, cia,
722 illegal_instruction_program_interrupt);
723 EA = *rA + *rB;
724 *rT = MEM(signed, EA, 2);
725 *rA = EA;
726
7270.32,6.RT,11.RA,16.D:D:::Load Word and Zero
728 unsigned_word b;
729 unsigned_word EA;
730 if (RA == 0) b = 0;
731 else b = *rA;
732 EA = b + EXTS(D);
733 *rT = MEM(unsigned, EA, 4);
7340.31,6.RT,11.RA,16.RB,21.23,31./:X:::Load Word and Zero Indexed
735 unsigned_word b;
736 unsigned_word EA;
737 if (RA == 0) b = 0;
738 else b = *rA;
739 EA = b + *rB;
740 *rT = MEM(unsigned, EA, 4);
7410.33,6.RT,11.RA,16.D:D:::Load Word and Zero with Update
742 unsigned_word EA;
743 if (RA == 0 || RA == RT)
744 program_interrupt(processor, cia,
745 illegal_instruction_program_interrupt);
746 EA = *rA + EXTS(D);
747 *rT = MEM(unsigned, EA, 4);
748 *rA = EA;
7490.31,6.RT,11.RA,16.RB,21.55,31./:X:::Load Word and Zero with Update Indexed
750 unsigned_word EA;
751 if (RA == 0 || RA == RT)
752 program_interrupt(processor, cia,
753 illegal_instruction_program_interrupt);
754 EA = *rA + *rB;
755 *rT = MEM(unsigned, EA, 4);
756 *rA = EA;
757
7580.58,6.RT,11.RA,16.DS,30.2:DS:64::Load Word Algebraic
759# unsigned_word b;
760# unsigned_word EA;
761# if (RA == 0) b = 0;
762# else b = *rA;
763# EA = b + EXTS(DS_0b00);
764# *rT = MEM(signed, EA, 4);
7650.31,6.RT,11.RA,16.RB,21.341,31./:X:64::Load Word Algebraic Indexed
766# unsigned_word b;
767# unsigned_word EA;
768# if (RA == 0) b = 0;
769# else b = *rA;
770# EA = b + *rB;;
771# *rT = MEM(signed, EA, 4);
7720.31,6.RT,11.RA,16.RB,21.373,31./:X:64::Load Word Algebraic with Update Indexed
773# unsigned_word EA;
774# if (RA == 0 || RA == RT)
775# program_interrupt(processor, cia
776# illegal_instruction_program_interrupt);
777# EA = *rA + *rB;
778# *rT = MEM(signed, EA, 4);
779# *rA = EA;
780
7810.58,6.RT,11.RA,16.DS,30.0:DS:64::Load Doubleword
782# unsigned_word b;
783# unsigned_word EA;
784# if (RA == 0) b = 0;
785# else b = *rA;
786# EA = b + EXTS(DS_0b00);
787# *rT = MEM(unsigned, EA, 8);
7880.31,6.RT,11.RA,16.RB,21.21,31./:X:64::Load Doubleword Indexed
789# unsigned_word b;
790# unsigned_word EA;
791# if (RA == 0) b = 0;
792# else b = *rA;
793# EA = b + *rB;
794# *rT = MEM(unsigned, EA, 8);
7950.58,6.RT,11.RA,16.DS,30.1:DS:64::Load Doubleword with Update
796# unsigned_word EA;
797# if (RA == 0 || RA == RT)
798# program_interrupt(processor, cia
799# illegal_instruction_program_interrupt);
800# EA = *rA + EXTS(DS_0b00);
801# *rT = MEM(unsigned, EA, 8);
802# *rA = EA;
8030.31,6.RT,11.RA,16.RB,21.53,31./:DS:64::Load Doubleword with Update Indexed
804# unsigned_word EA;
805# if (RA == 0 || RA == RT)
806# program_interrupt(processor, cia
807# illegal_instruction_program_interrupt);
808# EA = *rA + *rB;
809# *rT = MEM(unsigned, EA, 8);
810# *rA = EA;
811
812
813
814#
815# I.3.3.3 Fixed-Point Store Instructions
816#
817
8180.38,6.RS,11.RA,16.D:D:::Store Byte
819 unsigned_word b;
820 unsigned_word EA;
821 if (RA == 0) b = 0;
822 else b = *rA;
823 EA = b + EXTS(D);
824 STORE(EA, 1, *rS);
8250.31,6.RS,11.RA,16.RB,21.215,31./:X:::Store Byte Indexed
826 unsigned_word b;
827 unsigned_word EA;
828 if (RA == 0) b = 0;
829 else b = *rA;
830 EA = b + *rB;
831 STORE(EA, 1, *rS);
8320.39,6.RS,11.RA,16.D:D:::Store Byte with Update
833 unsigned_word EA;
834 if (RA == 0)
835 program_interrupt(processor, cia,
836 illegal_instruction_program_interrupt);
837 EA = *rA + EXTS(D);
838 STORE(EA, 1, *rS);
839 *rA = EA;
8400.31,6.RS,11.RA,16.RB,21.247,31./:X:::Store Byte with Update Indexed
841 unsigned_word EA;
842 if (RA == 0)
843 program_interrupt(processor, cia,
844 illegal_instruction_program_interrupt);
845 EA = *rA + *rB;
846 STORE(EA, 1, *rS);
847 *rA = EA;
848
8490.44,6.RS,11.RA,16.D:D:::Store Half Word
850 unsigned_word b;
851 unsigned_word EA;
852 if (RA == 0) b = 0;
853 else b = *rA;
854 EA = b + EXTS(D);
855 STORE(EA, 2, *rS);
8560.31,6.RS,11.RA,16.RB,21.407,31./:X:::Store Half Word Indexed
857 unsigned_word b;
858 unsigned_word EA;
859 if (RA == 0) b = 0;
860 else b = *rA;
861 EA = b + *rB;
862 STORE(EA, 2, *rS);
8630.45,6.RS,11.RA,16.D:D:::Store Half Word with Update
864 unsigned_word EA;
865 if (RA == 0)
866 program_interrupt(processor, cia,
867 illegal_instruction_program_interrupt);
868 EA = *rA + EXTS(D);
869 STORE(EA, 2, *rS);
870 *rA = EA;
8710.31,6.RS,11.RA,16.RB,21.439,31./:X:::Store Half Word with Update Indexed
872 unsigned_word EA;
873 if (RA == 0)
874 program_interrupt(processor, cia,
875 illegal_instruction_program_interrupt);
876 EA = *rA + *rB;
877 STORE(EA, 2, *rS);
878 *rA = EA;
879
8800.36,6.RS,11.RA,16.D:D:::Store Word
881 unsigned_word b;
882 unsigned_word EA;
883 if (RA == 0) b = 0;
884 else b = *rA;
885 EA = b + EXTS(D);
886 STORE(EA, 4, *rS);
8870.31,6.RS,11.RA,16.RB,21.151,31./:X:::Store Word Indexed
888 unsigned_word b;
889 unsigned_word EA;
890 if (RA == 0) b = 0;
891 else b = *rA;
892 EA = b + *rB;
893 STORE(EA, 4, *rS);
8940.37,6.RS,11.RA,16.D:D:::Store Word with Update
895 unsigned_word EA;
896 if (RA == 0)
897 program_interrupt(processor, cia,
898 illegal_instruction_program_interrupt);
899 EA = *rA + EXTS(D);
900 STORE(EA, 4, *rS);
901 *rA = EA;
9020.31,6.RS,11.RA,16.RB,21.183,31./:X:::Store Word with Update Indexed
903 unsigned_word EA;
904 if (RA == 0)
905 program_interrupt(processor, cia,
906 illegal_instruction_program_interrupt);
907 EA = *rA + *rB;
908 STORE(EA, 4, *rS);
909 *rA = EA;
910
9110.62,6.RS,11.RA,16.DS,30.0:DS:64::Store Doubleword
912# unsigned_word b;
913# unsigned_word EA;
914# if (RA == 0) b = 0;
915# else b = *rA;
916# EA = b + EXTS(DS_0b00);
917# STORE(EA, 8, *rS);
9180.31,6.RS,11.RA,16.RB,21.149,31./:X:64::Store Doubleword Indexed
919# unsigned_word b;
920# unsigned_word EA;
921# if (RA == 0) b = 0;
922# else b = *rA;
923# EA = b + *rB;
924# STORE(EA, 8, *rS);
9250.62,6.RS,11.RA,16.DS,30.1:DS:64::Store Doubleword with Update
926# unsigned_word EA;
927# if (RA == 0)
928# program_interrupt(processor, cia
929# illegal_instruction_program_interrupt);
930# EA = *rA + EXTS(DS_0b00);
931# STORE(EA, 8, *rS);
932# *rA = EA;
9330.31,6.RS,11.RA,16.RB,21.181,31./:X:64::Store Doubleword with Update Indexed
934# unsigned_word EA;
935# if (RA == 0)
936# program_interrupt(processor, cia
937# illegal_instruction_program_interrupt);
938# EA = *rA + *rB;
939# STORE(EA, 8, *rS);
940# *rA = EA;
941
942
943#
944# I.3.3.4 Fixed-Point Load and Store with Byte Reversal Instructions
945#
946
9470.31,6.RT,11.RA,16.RB,21.790,31./:X:::Load Halfword Byte-Reverse Indexed
73c4941b
MM		 948 unsigned_word b;
949 unsigned_word EA;
950 if (RA == 0) b = 0;
951 else b = *rA;
952 EA = b + *rB;
953 *rT = SWAP_2(MEM(unsigned, EA, 2));
c143ef62 9540.31,6.RT,11.RA,16.RB,21.534,31./:X:::Load Word Byte-Reverse Indexed
73c4941b
MM		 955 unsigned_word b;
956 unsigned_word EA;
957 if (RA == 0) b = 0;
958 else b = *rA;
959 EA = b + *rB;
960 *rT = SWAP_4(MEM(unsigned, EA, 4));
c143ef62
MM		 961
9620.31,6.RS,11.RA,16.RB,21.918,31./:X:::Store Half Word Byte-Reversed Indexed
73c4941b
MM		 963 unsigned_word b;
964 unsigned_word EA;
965 if (RA == 0) b = 0;
966 else b = *rA;
967 EA = b + *rB;
968 STORE(EA, 2, SWAP_2(*rS));
c143ef62 9690.31,6.RS,11.RA,16.RB,21.662,31./:X:::Store Word Byte-Reversed Indexed
73c4941b
MM		 970 unsigned_word b;
971 unsigned_word EA;
972 if (RA == 0) b = 0;
973 else b = *rA;
974 EA = b + *rB;
975 STORE(EA, 4, SWAP_4(*rS));
c143ef62
MM		 976
977
978#
979# I.3.3.5 Fixed-Point Load and Store Multiple Instrctions
980#
981
9820.46,6.RT,11.RA,16.D:D:be::Load Multiple Word
9830.47,6.RS,11.RA,16.D:D:be::Store Multiple Word
984
985
986#
987# I.3.3.6 Fixed-Point Move Assist Instructions
988#
989
9900.31,6.RT,11.RA,16.NB,21.597,31./:X:be::Load String Word Immediate
9910.31,6.RT,11.RA,16.RB,21.533,31./:X:be::Load String Word Indexed
992
9930.31,6.RS,11.RA,16.NB,21.725,31./:X:be::Store String Word Immedate
9940.31,6.RS,11.RA,16.RB,21.661,31./:X:be::Store String Word Indexed
995
996
997#
998# I.3.3.7 Storage Synchronization Instructions
999#
1000# HACK: Rather than monitor addresses looking for a reason
1001# to cancel a reservation. This code instead keeps
1002# a copy of the data read from memory. Before performing
1003# a store, the memory area is checked to see if it has
1004# been changed.
10050.31,6.RT,11.RA,16.RB,21.20,31./:X:::Load Word And Reserve Indexed
1006 unsigned_word b;
1007 unsigned_word EA;
1008 if (RA == 0) b = 0;
1009 else b = *rA;
1010 EA = b + *rB;
1011 RESERVE = 1;
1012 RESERVE_ADDR = real_addr(EA, 1/*is-read?*/);
1013 RESERVE_DATA = MEM(unsigned, EA, 4);
1014 *rT = RESERVE_DATA;
10150.31,6.RT,11.RA,16.RB,21.84,31./:X:64::Load Doubleword And Reserve Indexed
1016 unsigned_word b;
1017 unsigned_word EA;
1018 if (RA == 0) b = 0;
1019 else b = *rA;
1020 EA = b + *rB;
1021 RESERVE = 1;
1022 RESERVE_ADDR = real_addr(EA, 1/*is-read?*/);
1023 RESERVE_DATA = MEM(unsigned, EA, 8);
1024 *rT = RESERVE_DATA;
1025
10260.31,6.RS,11.RA,16.RB,21.150,31.1:X:::Store Word Conditional Indexed
1027 unsigned_word b;
1028 unsigned_word EA;
1029 if (RA == 0) b = 0;
1030 else b = *rA;
1031 EA = b + *rB;
1032 if (RESERVE) {
1033 if (RESERVE_ADDR == real_addr(EA, 0/*is-read?*/)
1034 && /*HACK*/ RESERVE_DATA == MEM(unsigned, EA, 4)) {
1035 STORE(EA, 4, *rS);
1036 CR_SET_XER_SO(0, cr_i_zero);
1037 }
1038 else {
1039 /* ment to randomly to store, we never do! */
1040 CR_SET_XER_SO(0, 0);
1041 }
1042 RESERVE = 0;
1043 }
1044 else {
1045 CR_SET_XER_SO(0, 0);
1046 }
10470.31,6.RS,11.RA,16.RB,21.214,31.1:X:64::Store Doubleword Conditional Indexed
1048 unsigned_word b;
1049 unsigned_word EA;
1050 if (RA == 0) b = 0;
1051 else b = *rA;
1052 EA = b + *rB;
1053 if (RESERVE) {
1054 if (RESERVE_ADDR == real_addr(EA, 0/*is-read?*/)
1055 && /*HACK*/ RESERVE_DATA == MEM(unsigned, EA, 8)) {
1056 STORE(EA, 8, *rS);
1057 CR_SET_XER_SO(0, cr_i_zero);
1058 }
1059 else {
1060 /* ment to randomly to store, we never do */
1061 CR_SET_XER_SO(0, 0);
1062 }
1063 RESERVE = 0;
1064 }
1065 else {
1066 CR_SET_XER_SO(0, 0);
1067 }
1068
10690.31,6./,11./,16./,21.598,31./:X::sync:Synchronize
1070 /* do nothing */
1071
1072
1073#
1074# I.3.3.9 Fixed-Point Arithmetic Instructions
1075#
1076
10770.14,6.RT,11.RA,16.SI:D:T::Add Immediate
28816f45
MM		 1078*PPC603:PPC603_IU:1:1:0
1079*PPC603e:PPC603e_IU|PPC603e_SRU:1:1:0
1080*PPC604:PPC604_SCIU:1:1:0
c143ef62
MM		 1081 if (RA_is_0) *rT = EXTS(SI);
1082 else *rT = *rA + EXTS(SI);
10830.15,6.RT,11.RA,16.SI:D:::Add Immediate Shifted
1084 if (RA_is_0) *rT = EXTS(SI) << 16;
1085 else *rT = *rA + (EXTS(SI) << 16);
10860.31,6.RT,11.RA,16.RB,21.OE,22.266,31.Rc:XO:::Add
1087 ALU_BEGIN(*rA);
1088 ALU_ADD(*rB);
1089 ALU_END(*rT, 0/*CA*/, OE, Rc);
10900.31,6.RT,11.RA,16.RB,21.OE,22.40,31.Rc:XO:::Subtract From
1091 ALU_BEGIN(*rA);
1092 ALU_NOT;
1093 ALU_ADD(*rB);
1094 ALU_ADD(1);
1095 ALU_END(*rT, 0/*CA*/, OE, Rc);
10960.12,6.RT,11.RA,16.SI:D:::Add Immediate Carrying
1097 ALU_BEGIN(*rA);
1098 ALU_ADD(EXTS(SI));
1099 ALU_END(*rT, 1/*CA*/, 0/*OE*/, 0/*Rc*/);
11000.13,6.RT,11.RA,16.SI:D:::Add Immediate Carrying and Record
1101 ALU_BEGIN(*rA);
1102 ALU_ADD(EXTS(SI));
1103 ALU_END(*rT, 1/*CA*/, 0/*OE*/, 1/*Rc*/);
11040.8,6.RT,11.RA,16.SI:D:::Subtract From Immediate Carrying
1105 ALU_BEGIN(*rA);
1106 ALU_NOT;
1107 ALU_ADD(EXTS(SI));
1108 ALU_ADD(1);
1109 ALU_END(*rT, 1/*CA*/, 0/*OE*/, 0/*Rc*/);
11100.31,6.RT,11.RA,16.RB,21.OE,22.10,31.Rc:XO:::Add Carrying
1111 ALU_BEGIN(*rA);
1112 ALU_ADD(*rB);
1113 ALU_END(*rT, 1/*CA*/, OE, Rc);
11140.31,6.RT,11.RA,16.RB,21.OE,22.8,31.Rc:XO:::Subtract From Carrying
1115 /* RT <- ~RA + RB + 1 === RT <- RB - RA */
1116 ALU_BEGIN(*rA);
1117 ALU_NOT;
1118 ALU_ADD(*rB);
1119 ALU_ADD(1);
1120 ALU_END(*rT, 1/*CA*/, OE, Rc);
11210.31,6.RT,11.RA,16.RB,21.OE,22.138,31.Rc:XO:::Add Extended
1122 ALU_BEGIN(*rA);
1123 ALU_ADD(*rB);
1124 ALU_ADD_CA;
1125 ALU_END(*rT, 1/*CA*/, OE, Rc);
11260.31,6.RT,11.RA,16.RB,21.OE,22.136,31.Rc:XO:::Subtract From Extended
1127 ALU_BEGIN(*rA);
1128 ALU_NOT;
1129 ALU_ADD(*rB);
1130 ALU_ADD_CA;
1131 ALU_END(*rT, 1/*CA*/, OE, Rc);
11320.31,6.RT,11.RA,16./,21.OE,22.234,31.Rc:XO:::Add to Minus One Extended
1133# ALU_BEGIN(*rA);
1134# ALU_ADD_CA;
1135# ALU_SUB(1);
1136# ALU_END(*rT, 1/*CA*/, OE, Rc);
11370.31,6.RT,11.RA,16./,21.OE,22.232,31.Rc:XO:::Subtract From Minus One Extended
1138# ALU_BEGIN(*rA);
1139# ALU_NOT;
1140# ALU_ADD_CA;
1141# ALU_SUB(1);
1142# ALU_END(*rT, 1/*CA*/, OE, Rc);
11430.31,6.RT,11.RA,16./,21.OE,22.202,31.Rc:XO::addze:Add to Zero Extended
1144 ALU_BEGIN(*rA);
1145 ALU_ADD_CA;
1146 ALU_END(*rT, 1/*CA*/, OE, Rc);
11470.31,6.RT,11.RA,16./,21.OE,22.200,31.Rc:XO:::Subtract from Zero Extended
1148 ALU_BEGIN(*rA);
1149 ALU_NOT;
1150 ALU_ADD_CA;
1151 ALU_END(*rT, 1/*CA*/, OE, Rc);
11520.31,6.RT,11.RA,16./,21.OE,22.104,31.Rc:XO:::Negate
1153 ALU_BEGIN(*rA);
1154 ALU_NOT;
1155 ALU_ADD(1);
1156 ALU_END(*rT,0/*CA*/,OE,Rc);
11570.7,6.RT,11.RA,16.SI:D::mulli:Multiply Low Immediate
1158 signed_word prod = *rA * EXTS(SI);
1159 *rT = prod;
11600.31,6.RT,11.RA,16.RB,21.OE,22.233,31.Rc:D:64::Multiply Low Doubleword
11610.31,6.RT,11.RA,16.RB,21.OE,22.235,31.Rc:XO::mullw:Multiply Low Word
1162 signed64 a = (signed32)(*rA);
1163 signed64 b = (signed32)(*rB);
1164 signed64 prod = a * b;
1165 signed_word t = prod;
1166 *rT = *rA * *rB;
1167 if (t != prod && OE)
1168 XER |= (xer_overflow | xer_summary_overflow);
1169 CR0_COMPARE(t, 0, Rc);
11700.31,6.RT,11.RA,16.RB,21./,22.73,31.Rc:XO:64::Multiply High Doubleword
11710.31,6.RT,11.RA,16.RB,21./,22.75,31.Rc:XO::mulhw:Multiply High Word
1172 signed64 a = (signed32)(*rA);
1173 signed64 b = (signed32)(*rB);
1174 signed64 prod = a * b;
1175 signed_word t = EXTRACTED64(prod, 0, 31);
1176 *rT = t;
1177 CR0_COMPARE(t, 0, Rc);
11780.31,6.RT,11.RA,16.RB,21./,22.9,31.Rc:XO:64::Multiply High Doubleword Unsigned
11790.31,6.RT,11.RA,16.RB,21./,22.11,31.Rc:XO::milhwu:Multiply High Word Unsigned
1180 unsigned64 a = (unsigned32)(*rA);
1181 unsigned64 b = (unsigned32)(*rB);
1182 unsigned64 prod = a * b;
1183 signed_word t = EXTRACTED64(prod, 0, 31);
1184 *rT = t;
1185 CR0_COMPARE(t, 0, Rc);
11860.31,6.RT,11.RA,16.RB,21.OE,22.489,31.Rc:XO:64::Divide Doubleword
11870.31,6.RT,11.RA,16.RB,21.OE,22.491,31.Rc:XO::divw:Divide Word
1188 signed64 dividend = (signed32)(*rA);
1189 signed64 divisor = (signed32)(*rB);
1190 if (divisor == 0 /* nb 0x8000..0 is sign extended */
1191 || (dividend == 0x80000000 && divisor == -1)) {
1192 if (OE)
1193 XER |= (xer_overflow | xer_summary_overflow);
1194 CR0_COMPARE(0, 0, Rc);
1195 }
1196 else {
1197 signed64 quotent = dividend / divisor;
1198 *rT = quotent;
1199 CR0_COMPARE((signed_word)quotent, 0, Rc);
1200 }
12010.31,6.RT,11.RA,16.RB,21.OE,22.457,31.Rc:XO:64::Divide Doubleword Unsigned
12020.31,6.RT,11.RA,16.RB,21.OE,22.459,31.Rc:XO::divwu:Divide Word Unsigned
1203 unsigned64 dividend = (unsigned32)(*rA);
1204 unsigned64 divisor = (unsigned32)(*rB);
1205 if (divisor == 0) {
1206 if (OE)
1207 XER |= (xer_overflow | xer_summary_overflow);
1208 CR0_COMPARE(0, 0, Rc);
1209 }
1210 else {
1211 unsigned64 quotent = dividend / divisor;
1212 *rT = quotent;
1213 CR0_COMPARE((signed_word)quotent, 0, Rc);
1214 }
1215
1216
1217#
1218# I.3.3.10 Fixed-Point Compare Instructions
1219#
1220
12210.11,6.BF,9./,10.L,11.RA,16.SI:D:::Compare Immediate
1222 if (!is_64bit_mode && L)
1223 program_interrupt(processor, cia,
1224 illegal_instruction_program_interrupt);
1225 else {
1226 signed_word a;
1227 signed_word b = EXTS(SI);
1228 if (L == 0)
1229 a = EXTENDED(*rA);
1230 else
1231 a = *rA;
1232 CR_COMPARE(BF, a, b);
1233 }
12340.31,6.BF,9./,10.L,11.RA,16.RB,21.0,31./:X:::Compare
1235 if (!is_64bit_mode && L)
1236 program_interrupt(processor, cia,
1237 illegal_instruction_program_interrupt);
1238 else {
1239 signed_word a;
1240 signed_word b;
1241 if (L == 0) {
1242 a = EXTENDED(*rA);
1243 b = EXTENDED(*rB);
1244 }
1245 else {
1246 a = *rA;
1247 b = *rB;
1248 }
1249 CR_COMPARE(BF, a, b);
1250 }
12510.10,6.BF,9./,10.L,11.RA,16.UI:D:::Compare Logical Immediate
1252 if (!is_64bit_mode && L)
1253 program_interrupt(processor, cia,
1254 illegal_instruction_program_interrupt);
1255 else {
1256 unsigned_word a;
1257 unsigned_word b = UI;
1258 if (L == 0)
1259 a = MASKED(*rA, 32, 63);
1260 else
1261 a = *rA;
1262 CR_COMPARE(BF, a, b);
1263 }
12640.31,6.BF,9./,10.L,11.RA,16.RB,21.32,31./:X:::Compare Logical
1265 if (!is_64bit_mode && L)
1266 program_interrupt(processor, cia,
1267 illegal_instruction_program_interrupt);
1268 else {
1269 unsigned_word a;
1270 unsigned_word b;
1271 if (L == 0) {
1272 a = MASKED(*rA, 32, 63);
1273 b = MASKED(*rB, 32, 63);
1274 }
1275 else {
1276 a = *rA;
1277 b = *rB;
1278 }
1279 CR_COMPARE(BF, a, b);
1280 }
1281
1282
1283#
1284# I.3.3.11 Fixed-Point Trap Instructions
1285#
1286
12870.2,6.TO,11.RA,16.SI:D:64::Trap Doubleword Immediate
1288 if (!is_64bit_mode)
1289 program_interrupt(processor, cia,
1290 illegal_instruction_program_interrupt);
1291 else {
1292 signed_word a = *rA;
1293 signed_word b = EXTS(SI);
1294 if ((a < b && TO{0})
1295 || (a > b && TO{1})
1296 || (a == b && TO{2})
1297 || ((unsigned_word)a < (unsigned_word)b && TO{3})
1298 || ((unsigned_word)a > (unsigned_word)b && TO{4})
1299 )
1300 program_interrupt(processor, cia,
1301 trap_program_interrupt);
1302 }
13030.3,6.TO,11.RA,16.SI:D:::Trap Word Immediate
1304 signed_word a = EXTENDED(*rA);
1305 signed_word b = EXTS(SI);
1306 if ((a < b && TO{0})
1307 || (a > b && TO{1})
1308 || (a == b && TO{2})
1309 || ((unsigned_word)a < (unsigned_word)b && TO{3})
1310 || ((unsigned_word)a > (unsigned_word)b && TO{4})
1311 )
1312 program_interrupt(processor, cia,
1313 trap_program_interrupt);
13140.31,6.TO,11.RA,16.RB,21.68,31./:X:64::Trap Doubleword
1315 if (!is_64bit_mode)
1316 program_interrupt(processor, cia,
1317 illegal_instruction_program_interrupt);
1318 else {
1319 signed_word a = *rA;
1320 signed_word b = *rB;
1321 if ((a < b && TO{0})
1322 || (a > b && TO{1})
1323 || (a == b && TO{2})
1324 || ((unsigned_word)a < (unsigned_word)b && TO{3})
1325 || ((unsigned_word)a > (unsigned_word)b && TO{4})
1326 )
1327 program_interrupt(processor, cia,
1328 trap_program_interrupt);
1329 }
13300.31,6.TO,11.RA,16.RB,21.4,31./:X:::Trap Word
1331 signed_word a = EXTENDED(*rA);
1332 signed_word b = EXTENDED(*rB);
1333 if (TO == 12 && rA == rB) {
1334 ITRACE(trace_breakpoint, ("breakpoint\n"));
1335 cpu_halt(processor, cia, was_trap, 0);
1336 }
1337 else if ((a < b && TO{0})
1338 || (a > b && TO{1})
1339 || (a == b && TO{2})
1340 || ((unsigned_word)a < (unsigned_word)b && TO{3})
1341 || ((unsigned_word)a > (unsigned_word)b && TO{4})
1342 )
1343 program_interrupt(processor, cia,
1344 trap_program_interrupt);
1345
1346#
1347# I.3.3.12 Fixed-Point Logical Instructions
1348#
1349
13500.28,6.RS,11.RA,16.UI:D:::AND Immediate
1351 *rA = *rS & UI;
1352 CR0_COMPARE(*rA, 0, 1/*Rc*/);
13530.29,6.RS,11.RA,16.UI:D:::AND Immediate Shifted
1354 *rA = *rS & (UI << 16);
1355 CR0_COMPARE(*rA, 0, 1/*Rc*/);
13560.24,6.RS,11.RA,16.UI:D:::OR Immediate
1357 *rA = *rS | UI;
13580.25,6.RS,11.RA,16.UI:D:::OR Immediate Shifted
1359 *rA = *rS | (UI << 16);
13600.26,6.RS,11.RA,16.UI:D:::XOR Immediate
1361 *rA = *rS ^ UI;
13620.27,6.RS,11.RA,16.UI:D:::XOR Immediate Shifted
1363 *rA = *rS ^ (UI << 16);
13640.31,6.RS,11.RA,16.RB,21.28,31.Rc:X:::AND
1365 *rA = *rS & *rB;
1366 CR0_COMPARE(*rA, 0, Rc);
13670.31,6.RS,11.RA,16.RB,21.444,31.Rc:X:::OR
1368 *rA = *rS | *rB;
1369 CR0_COMPARE(*rA, 0, Rc);
13700.31,6.RS,11.RA,16.RB,21.316,31.Rc:X:::XOR
1371 *rA = *rS ^ *rB;
1372 CR0_COMPARE(*rA, 0, Rc);
13730.31,6.RS,11.RA,16.RB,21.476,31.Rc:X:::NAND
1374 *rA = ~(*rS & *rB);
1375 CR0_COMPARE(*rA, 0, Rc);
13760.31,6.RS,11.RA,16.RB,21.124,31.Rc:X:::NOR
1377 *rA = ~(*rS | *rB);
1378 CR0_COMPARE(*rA, 0, Rc);
13790.31,6.RS,11.RA,16.RB,21.284,31.Rc:X:::Equivalent
1380# *rA = ~(*rS ^ *rB); /* A === B */
1381# CR0_COMPARE(*rA, 0, Rc);
13820.31,6.RS,11.RA,16.RB,21.60,31.Rc:X:::AND with Complement
1383 *rA = *rS & ~*rB;
1384 CR0_COMPARE(*rA, 0, Rc);
13850.31,6.RS,11.RA,16.RB,21.412,31.Rc:X:::OR with Complement
1386 *rA = *rS | ~*rB;
1387 CR0_COMPARE(*rA, 0, Rc);
13880.31,6.RS,11.RA,16./,21.954,31.Rc:X::extsb:Extend Sign Byte
1389 *rA = (signed_word)(signed8)*rS;
1390 CR0_COMPARE(*rA, 0, Rc);
13910.31,6.RS,11.RA,16./,21.922,31.Rc:X::extsh:Extend Sign Half Word
1392 *rA = (signed_word)(signed16)*rS;
1393 CR0_COMPARE(*rA, 0, Rc);
13940.31,6.RS,11.RA,16./,21.986,31.Rc:X:64::Extend Sign Word
1395# *rA = (signed_word)(signed32)*rS;
1396# CR0_COMPARE(*rA, 0, Rc);
13970.31,6.RS,11.RA,16./,21.58,31.Rc:X:64::Count Leading Zeros Doubleword
1398# int count = 0;
1399# unsigned64 mask = BIT64(0);
1400# unsigned64 source = *rS;
1401# while (!(source & mask) && mask != 0) {
1402# mask >>= 1;
1403# count++;
1404# }
1405# *rA = count;
1406# CR0_COMPARE(count, 0, Rc); /* FIXME - is this correct */
14070.31,6.RS,11.RA,16./,21.26,31.Rc:X:::Count Leading Zeros Word
1408 int count = 0;
1409 unsigned32 mask = BIT32(0);
1410 unsigned32 source = *rS;
1411 while (!(source & mask) && mask != 0) {
1412 mask >>= 1;
1413 count++;
1414 }
1415 *rA = count;
1416 CR0_COMPARE(count, 0, Rc); /* FIXME - is this correct */
1417
1418
1419#
1420# I.3.3.13 Fixed-Point Rotate and Shift Instructions
1421#
1422
14230.30,6.RS,11.RA,16.sh_0_4,21.mb,27.0,30.sh_5,31.Rc:MD:64::Rotate Left Doubleword Immediate then Clear Left
1424# long n = (sh_5 << 4) | sh_0_4;
1425# unsigned_word r = ROTL64(*rS, n);
1426# long b = (mb_5 << 4) | mb_0_4;
1427# unsigned_word m = MASK(b, 63);
1428# signed_word result = r & m;
1429# *rA = result;
1430# CR0_COMPARE(result, 0, Rc); /* FIXME - is this correct */
14310.30,6.RS,11.RA,16.sh_0_4,21.me,27.1,30.sh_5,31.Rc:MD:64::Rotate Left Doubleword Immediate then Clear Right
1432# long n = (sh_5 << 4) | sh_0_4;
1433# unsigned_word r = ROTL64(*rS, n);
1434# long e = (me_5 << 4) | me_0_4;
1435# unsigned_word m = MASK(0, e);
1436# signed_word result = r & m;
1437# *rA = result;
1438# CR0_COMPARE(result, 0, Rc); /* FIXME - is this correct */
14390.30,6.RS,11.RA,16.sh_0_4,21.mb,27.2,30.sh_5,31.Rc:MD:64::Rotate Left Doubleword Immediate then Clear
1440# long n = (sh_5 << 4) | sh_0_4;
1441# unsigned_word r = ROTL64(*rS, n);
1442# long b = (mb_5 << 4) | mb_0_4;
1443# unsigned_word m = MASK(0, (64-n));
1444# signed_word result = r & m;
1445# *rA = result;
1446# CR0_COMPARE(result, 0, Rc); /* FIXME - is this correct */
1447
14480.21,6.RS,11.RA,16.SH,21.MB,26.ME,31.Rc:M:::Rotate Left Word Immediate then AND with Mask
1449 long n = SH;
1450 unsigned32 s = *rS;
1451 unsigned32 r = ROTL32(s, n);
1452 unsigned32 m = MASK(MB+32, ME+32);
1453 signed_word result = r & m;
1454 *rA = result;
1455 CR0_COMPARE(result, 0, Rc);
1456 ITRACE(trace_alu,
1457 ("n=%d, s=0x%x, r=0x%x, m=0x%x, result=0x%x, cr=0x%x\n",
1458 n, s, r, m, result, CR));
1459
14600.30,6.RS,11.RA,16.RB,21.mb,27.8,31.Rc:MDS:64::Rotate Left Doubleword then Clear Left
1461# long n = MASKED(*rB, 58, 63);
1462# unsigned_word r = ROTL64(*rS, n);
1463# long b = (mb_5 << 4) | mb_0_4;
1464# unsigned_word m = MASK(b, 63);
1465# signed_word result = r & m;
1466# *rA = result;
1467# CR0_COMPARE(result, 0, Rc);
14680.30,6.RS,11.RA,16.RB,21.me,27.9,31.Rc:MDS:64::Rotate Left Doubleword then Clear Right
1469# long n = MASKED(*rB, 58, 63);
1470# unsigned_word r = ROTL64(*rS, n);
1471# long e = (me_5 << 4) | me_0_4;
1472# unsigned_word m = MASK(0, e);
1473# signed_word result = r & m;
1474# *rA = result;
1475# CR0_COMPARE(result, 0, Rc);
1476
14770.23,6.RS,11.RA,16.RB,21.MB,26.ME,31.Rc:M:::Rotate Left Word then AND with Mask
1478# long n = MASKED(*rB, 59, 63);
1479# unsigned32 r = ROTL32(*rS, n);
1480# unsigned32 m = MASK(MB+32, ME+32);
1481# signed_word result = r & m;
1482# *rA = result;
1483# CR0_COMPARE(result, 0, Rc);
14840.30,6.RS,11.RA,16.sh_0_4,21.mb,27.3,30.sh_5,31.Rc:MD:64::Rotate Left Doubleword Immediate then Mask Insert
1485# long n = (sh_5 << 4) | sh_0_4;
1486# unsigned_word r = ROTL64(*rS, n);
1487# long b = (mb_5 << 4) | mb_0_4;
1488# unsigned_word m = MASK(b, (64-n));
1489# signed_word result = (r & m) | (*rA & ~m)
1490# *rA = result;
1491# CR0_COMPARE(result, 0, Rc);
14920.20,6.RS,11.RA,16.SH,21.MB,26.ME,31.Rc:M::rlwimi:Rotate Left Word Immediate then Mask Insert
1493 long n = SH;
1494 unsigned32 r = ROTL32(*rS, n);
1495 unsigned32 m = MASK(MB+32, ME+32);
1496 signed_word result = (r & m) | (*rA & ~m);
1497 *rA = result;
1498 ITRACE(trace_alu, (": n=%d *rS=0x%x r=0x%x m=0x%x result=0x%x\n",
1499 n, *rS, r, m, result));
1500 CR0_COMPARE(result, 0, Rc);
1501
1502
15030.31,6.RS,11.RA,16.RB,21.27,31.Rc:X:64::Shift Left Doubleword
15040.31,6.RS,11.RA,16.RB,21.24,31.Rc:X:::Shift Left Word
1505 int n = MASKED(*rB, 59, 63);
1506 unsigned32 source = *rS;
1507 signed_word shifted;
1508 if (n < 32)
1509 shifted = (source << n);
1510 else
1511 shifted = 0;
1512 *rA = shifted;
1513 CR0_COMPARE(shifted, 0, Rc);
1514 ITRACE(trace_alu,
1515 ("n=%d, source=0x%x, shifted=0x%x\n",
1516 n, source, shifted));
15170.31,6.RS,11.RA,16.RB,21.539,31.Rc:X:64::Shift Right Doubleword
15180.31,6.RS,11.RA,16.RB,21.536,31.Rc:X:::Shift Right Word
1519 int n = MASKED(*rB, 59, 63);
1520 unsigned32 source = *rS;
1521 signed_word shifted;
1522 if (n < 32)
1523 shifted = (source >> n);
1524 else
1525 shifted = 0;
1526 *rA = shifted;
1527 CR0_COMPARE(shifted, 0, Rc);
1528 ITRACE(trace_alu, \
1529 ("n=%d, source=0x%x, shifted=0x%x\n",
1530 n, source, shifted));
1531
15320.31,6.RS,11.RA,16.sh_0_4,21.413,30.sh_5,31.Rc:XS:64::Shift Right Algebraic Doubleword Immediate
15330.31,6.RS,11.RA,16.SH,21.824,31.Rc:X:::Shift Right Algebraic Word Immediate
1534 int n = SH;
1535 signed_word r = ROTL32(*rS, /*64*/32-n);
1536 signed_word m = MASK(n+32, 63);
1537 int S = MASKED(*rS, 32, 32);
1538 signed_word shifted = (r & m) | (S ? ~m : 0);
1539 *rA = shifted;
1540 if (S && ((r & ~m) & MASK(32, 63)) != 0)
1541 XER |= xer_carry;
1542 else
1543 XER &= ~xer_carry;
1544 CR0_COMPARE(shifted, 0, Rc);
15450.31,6.RS,11.RA,16.RB,21.794,31.Rc:X:64::Shift Right Algebraic Doubleword
15460.31,6.RS,11.RA,16.RB,21.792,31.Rc:X:::Shift Right Algebraic Word
1547 int n = MASKED(*rB, 58, 63);
1548 int shift = (n >= 31 ? 31 : n);
1549 signed32 source = (signed32)*rS; /* signed to keep sign bit */
1550 signed32 shifted = source >> shift;
1551 unsigned32 mask = ((unsigned32)-1) >> (31-shift);
1552 *rA = (signed_word)shifted; /* if 64bit will sign extend */
1553 if (source < 0 && (source & mask))
1554 XER |= xer_carry;
1555 else
1556 XER &= ~xer_carry;
1557 CR0_COMPARE(shifted, 0, Rc);
1558
1559
1560#
1561# I.3.3.14 Move to/from System Register Instructions
1562#
1563
15640.31,6.RS,11.spr,21.467,31./:XFX:::Move to Special Purpose Register
1565 int n = (spr{5:9} << 5) | spr{0:4};
1566 if (spr{0} && IS_PROBLEM_STATE(processor))
1567 program_interrupt(processor, cia,
1568 privileged_instruction_program_interrupt);
1569 else if (!spr_is_valid(n)
1570 || spr_is_readonly(n))
1571 program_interrupt(processor, cia,
1572 illegal_instruction_program_interrupt);
1573 else {
1574 spreg new_val = (spr_length(n) == 64
1575 ? *rS
1576 : MASKED(*rS, 32, 63));
1577 /* HACK - time base registers need to be updated immediatly */
1578 if (WITH_TIME_BASE) {
1579 signed64 time_base;
1580 switch (n) {
1581 case spr_tbu:
1582 cpu_set_time_base(processor,
1583 (MASKED64(cpu_get_time_base(processor),
1584 32, 63)
1585 | ((signed64)new_val << 32)));
1586 break;
1587 case spr_tbl:
1588 cpu_set_time_base(processor,
1589 (MASKED64(cpu_get_time_base(processor),
1590 32, 63)
1591 | ((signed64)new_val << 32)));
1592 break;
1593 case spr_dec:
1594 cpu_set_decrementer(processor, new_val);
1595 break;
1596 default:
1597 SPREG(n) = new_val;
1598 break;
1599 }
1600 }
1601 else {
1602 SPREG(n) = new_val;
1603 }
1604 }
16050.31,6.RT,11.spr,21.339,31./:XFX:uea::Move from Special Purpose Register
1606 int n = (spr{5:9} << 5) | spr{0:4};
1607 if (spr{0} && IS_PROBLEM_STATE(processor))
1608 program_interrupt(processor, cia,
1609 privileged_instruction_program_interrupt);
1610 else if (!spr_is_valid(n))
1611 program_interrupt(processor, cia,
1612 illegal_instruction_program_interrupt);
1613 else {
1614 /* HACK - some SPR's need to get their value extracted specially */
1615 *rT = SPREG(n);
1616 }
16170.31,6.RS,11./,12.FXM,20./,21.144,31./:XFX::mtfcr:Move to Condition Register Fields
1618 if (FXM == 0xff) {
1619 CR = *rS;
1620 }
1621 else {
1622 unsigned_word mask = 0;
1623 unsigned_word f;
1624 for (f = 0; f < 8; f++) {
1625 if (FXM & (0x80 >> f))
1626 mask |= (0xf << 4*(7-f));
1627 }
1628 CR = (MASKED(*rS, 32, 63) & mask) | (CR & ~mask);
1629 }
16300.31,6.BF,9./,11./,16./,21.512,31./:X:::Move to Condition Register from XER
16310.31,6.RT,11./,16./,21.19,31./:X:::Move From Condition Register
1632 *rT = (unsigned32)CR;
1633
1634#
1635# I.4.6.2 Floating-Point Load Instructions
1636#
1637
16380.48,6.FRT,11.RA,16.D:D:f:lfs:Load Floating-Point Single
1639 unsigned_word b;
1640 unsigned_word EA;
1641 if (RA == 0) b = 0;
1642 else b = *rA;
1643 EA = b + EXTS(D);
1644 *frT = DOUBLE(MEM(unsigned, EA, 4));
16450.31,6.FRT,11.RA,16.RB,21.535,31./:X:f::Load Floating-Point Single Indexed
1646 unsigned_word b;
1647 unsigned_word EA;
1648 if (RA == 0) b = 0;
1649 else b = *rA;
1650 EA = b + *rB;
1651 *frT = DOUBLE(MEM(unsigned, EA, 4));
16520.49,6.FRT,11.RA,16.D:D:f::Load Floating-Point Single with Update
1653 unsigned_word EA;
1654 if (RA == 0)
1655 program_interrupt(processor, cia,
1656 illegal_instruction_program_interrupt);
1657 EA = *rA + EXTS(D);
1658 *frT = DOUBLE(MEM(unsigned, EA, 4));
1659 *rA = EA;
16600.31,6.FRT,11.RA,16.RB,21.576,31./:X:f::Load Floating-Point Single with Update Indexed
1661 unsigned_word EA;
1662 if (RA == 0)
1663 program_interrupt(processor, cia,
1664 illegal_instruction_program_interrupt);
1665 EA = *rA + *rB;
1666 *frT = DOUBLE(MEM(unsigned, EA, 4));
1667 *rA = EA;
1668
16690.50,6.FRT,11.RA,16.D:D:f::Load Floating-Point Double
1670 unsigned_word b;
1671 unsigned_word EA;
1672 if (RA == 0) b = 0;
1673 else b = *rA;
1674 EA = b + EXTS(D);
1675 *frT = MEM(unsigned, EA, 8);
16760.31,6.FRT,11.RA,16.RB,21.599,31./:X:f::Load Floating-Point Double Indexed
1677 unsigned_word b;
1678 unsigned_word EA;
1679 if (RA == 0) b = 0;
1680 else b = *rA;
1681 EA = b + *rB;
1682 *frT = MEM(unsigned, EA, 8);
16830.51,6.FRT,11.RA,16.D:D:f::Load Floating-Point Double with Update
1684 unsigned_word EA;
1685 if (RA == 0)
1686 program_interrupt(processor, cia,
1687 illegal_instruction_program_interrupt);
1688 EA = *rA + EXTS(D);
1689 *frT = MEM(unsigned, EA, 8);
1690 *rA = EA;
16910.31,6.FRT,11.RA,16.RB,21.631,31./:X:f::Load Floating-Point Double with Update Indexed
1692 unsigned_word EA;
1693 if (RA == 0)
1694 program_interrupt(processor, cia,
1695 illegal_instruction_program_interrupt);
1696 EA = *rA + *rB;
1697 *frT = MEM(unsigned, EA, 8);
1698 *rA = EA;
1699
1700
1701#
1702# I.4.6.3 Floating-Point Store Instructions
1703#
1704
17050.52,6.FRS,11.RA,16.D:D:f::Store Floating-Point Single
1706 unsigned_word b;
1707 unsigned_word EA;
1708 if (RA == 0) b = 0;
1709 else b = *rA;
1710 EA = b + EXTS(D);
1711 STORE(EA, 4, SINGLE(*frS));
17120.31,6.FRS,11.RA,16.RB,21.663,31./:X:f::Store Floating-Point Single Indexed
1713 unsigned_word b;
1714 unsigned_word EA;
1715 if (RA == 0) b = 0;
1716 else b = *rA;
1717 EA = b + *rB;
1718 STORE(EA, 4, SINGLE(*frS));
17190.53,6.FRS,11.RA,16.D:D:f::Store Floating-Point Single with Update
1720 unsigned_word EA;
1721 if (RA == 0)
1722 program_interrupt(processor, cia,
1723 illegal_instruction_program_interrupt);
1724 EA = *rA + EXTS(D);
1725 STORE(EA, 4, SINGLE(*frS));
1726 *rA = EA;
17270.31,6.FRS,11.RA,16.RB,21.695,31./:X:f::Store Floating-Point Single with Update Indexed
1728 unsigned_word EA;
1729 if (RA == 0)
1730 program_interrupt(processor, cia,
1731 illegal_instruction_program_interrupt);
1732 EA = *rA + *rB;
1733 STORE(EA, 4, SINGLE(*frS));
1734 *rA = EA;
1735
17360.54,6.FRS,11.RA,16.D:D:f::Store Floating-Point Double
1737 unsigned_word b;
1738 unsigned_word EA;
1739 if (RA == 0) b = 0;
1740 else b = *rA;
1741 EA = b + EXTS(D);
1742 STORE(EA, 8, *frS);
17430.31,6.FRS,11.RA,16.RB,21.727,31./:X:f::Store Floating-Point Double Indexed
1744 unsigned_word b;
1745 unsigned_word EA;
1746 if (RA == 0) b = 0;
1747 else b = *rA;
1748 EA = b + *rB;
1749 STORE(EA, 8, *frS);
17500.55,6.FRS,11.RA,16.D:D:f::Store Floating-Point Double with Update
1751 unsigned_word EA;
1752 if (RA == 0)
1753 program_interrupt(processor, cia,
1754 illegal_instruction_program_interrupt);
1755 EA = *rA + EXTS(D);
1756 STORE(EA, 8, *frS);
1757 *rA = EA;
17580.31,6.FRS,11.RA,16.RB,21.759,31./:X:f::Store Floating-Point Double with Update Indexed
1759 unsigned_word EA;
1760 if (RA == 0)
1761 program_interrupt(processor, cia,
1762 illegal_instruction_program_interrupt);
1763 EA = *rA + *rB;
1764 STORE(EA, 8, *frS);
1765 *rA = EA;
1766
1767
1768#
1769# I.4.6.4 Floating-Point Move Instructions
1770#
1771
17720.63,6.FRT,11./,16.FRB,21.72,31.Rc:X:f::Floating Move Register
1773 *frT = *frB;
1774 CR1_UPDATE(Rc);
17750.63,6.FRT,11./,16.FRB,21.40,31.Rc:X:f::Floating Negate
1776 *frT = *frB ^ BIT64(0);
1777 CR1_UPDATE(Rc);
17780.63,6.FRT,11./,16.FRB,21.264,31.Rc:X:f::Floating Absolute Value
1779 *frT = *frB & ~BIT64(0);
1780 CR1_UPDATE(Rc);
17810.63,6.FRT,11./,16.FRB,21.136,31.Rc:X:f::Floating Negative Absolute Value
1782 *frT = *frB | BIT64(0);
1783 CR1_UPDATE(Rc);
1784
1785
1786
1787#
1788# I.4.6.5 Floating-Point Arithmetic Instructions
1789#
1790
17910.63,6.FRT,11.FRA,16.FRB,21./,26.21,31.Rc:A:f:fadd:Floating Add
1792 FPSCR_BEGIN;
1793 if (is_invalid_operation(processor, cia,
1794 *frA, *frB,
1795 fpscr_vxsnan | fpscr_vxisi,
1796 0, /*single?*/
1797 0) /*negate?*/) {
1798 invalid_arithemetic_operation(processor, cia,
1799 frT, *frA, *frB, 0,
1800 0, /*instruction_is_frsp*/
1801 0, /*instruction_is_convert_to_64bit*/
1802 0, /*instruction_is_convert_to_32bit*/
1803 0); /*single-precision*/
1804 }
1805 else {
1806 /*HACK!*/
1807 double s = *(double*)frA + *(double*)frB;
1808 *(double*)frT = s;
1809 }
1810 FPSCR_END(Rc);
18110.59,6.FRT,11.FRA,16.FRB,21./,26.21,31.Rc:A:f:fadds:Floating Add Single
1812 FPSCR_BEGIN;
1813 if (is_invalid_operation(processor, cia,
1814 *frA, *frB,
1815 fpscr_vxsnan | fpscr_vxisi,
1816 1, /*single?*/
1817 0) /*negate?*/) {
1818 invalid_arithemetic_operation(processor, cia,
1819 frT, *frA, *frB, 0,
1820 0, /*instruction_is_frsp*/
1821 0, /*instruction_is_convert_to_64bit*/
1822 0, /*instruction_is_convert_to_32bit*/
1823 1); /*single-precision*/
1824 }
1825 else {
1826 /*HACK!*/
1827 float s = *(double*)frA + *(double*)frB;
1828 *(double*)frT = s;
1829 }
1830 FPSCR_END(Rc);
1831
18320.63,6.FRT,11.FRA,16.FRB,21./,26.20,31.Rc:A:f:fsub:Floating Subtract
1833 FPSCR_BEGIN;
1834 if (is_invalid_operation(processor, cia,
1835 *frA, *frB,
1836 fpscr_vxsnan | fpscr_vxisi,
1837 0, /*single?*/
1838 1) /*negate?*/) {
1839 invalid_arithemetic_operation(processor, cia,
1840 frT, *frA, *frB, 0,
1841 0, /*instruction_is_frsp*/
1842 0, /*instruction_is_convert_to_64bit*/
1843 0, /*instruction_is_convert_to_32bit*/
1844 0); /*single-precision*/
1845 }
1846 else {
1847 /*HACK!*/
1848 double s = *(double*)frA - *(double*)frB;
1849 *(double*)frT = s;
1850 }
1851 FPSCR_END(Rc);
18520.59,6.FRT,11.FRA,16.FRB,21./,26.20,31.Rc:A:f:fsubs:Floating Subtract Single
1853 FPSCR_BEGIN;
1854 if (is_invalid_operation(processor, cia,
1855 *frA, *frB,
1856 fpscr_vxsnan | fpscr_vxisi,
1857 1, /*single?*/
1858 1) /*negate?*/) {
1859 invalid_arithemetic_operation(processor, cia,
1860 frT, *frA, *frB, 0,
1861 0, /*instruction_is_frsp*/
1862 0, /*instruction_is_convert_to_64bit*/
1863 0, /*instruction_is_convert_to_32bit*/
1864 1); /*single-precision*/
1865 }
1866 else {
1867 /*HACK!*/
1868 float s = *(double*)frA - *(double*)frB;
1869 *(double*)frT = s;
1870 }
1871 FPSCR_END(Rc);
1872
18730.63,6.FRT,11.FRA,16./,21.FRC,26.25,31.Rc:A:f:fmul:Floating Multiply
1874 FPSCR_BEGIN;
1875 if (is_invalid_operation(processor, cia,
1876 *frA, *frC,
1877 fpscr_vxsnan | fpscr_vximz,
1878 0, /*single?*/
1879 0) /*negate?*/) {
1880 invalid_arithemetic_operation(processor, cia,
1881 frT, *frA, 0, *frC,
1882 0, /*instruction_is_frsp*/
1883 0, /*instruction_is_convert_to_64bit*/
1884 0, /*instruction_is_convert_to_32bit*/
1885 0); /*single-precision*/
1886 }
1887 else {
1888 /*HACK!*/
1889 double s = *(double*)frA * *(double*)frC;
1890 *(double*)frT = s;
1891 }
1892 FPSCR_END(Rc);
18930.59,6.FRT,11.FRA,16./,21.FRC,26.25,31.Rc:A:f:fmuls:Floating Multiply Single
1894 FPSCR_BEGIN;
1895 if (is_invalid_operation(processor, cia,
1896 *frA, *frC,
1897 fpscr_vxsnan | fpscr_vximz,
1898 1, /*single?*/
1899 0) /*negate?*/) {
1900 invalid_arithemetic_operation(processor, cia,
1901 frT, *frA, 0, *frC,
1902 0, /*instruction_is_frsp*/
1903 0, /*instruction_is_convert_to_64bit*/
1904 0, /*instruction_is_convert_to_32bit*/
1905 1); /*single-precision*/
1906 }
1907 else {
1908 /*HACK!*/
1909 float s = *(double*)frA * *(double*)frC;
1910 *(double*)frT = s;
1911 }
1912 FPSCR_END(Rc);
1913
19140.63,6.FRT,11.FRA,16.FRB,21./,26.18,31.Rc:A:f:fdiv:Floating Divide
1915 FPSCR_BEGIN;
1916 if (is_invalid_operation(processor, cia,
1917 *frA, *frB,
1918 fpscr_vxsnan | fpscr_vxzdz,
1919 0, /*single?*/
1920 0) /*negate?*/) {
1921 invalid_arithemetic_operation(processor, cia,
1922 frT, *frA, *frB, 0,
1923 0, /*instruction_is_frsp*/
1924 0, /*instruction_is_convert_to_64bit*/
1925 0, /*instruction_is_convert_to_32bit*/
1926 0); /*single-precision*/
1927 }
1928 else {
1929 /*HACK!*/
1930 double s = *(double*)frA / *(double*)frB;
1931 *(double*)frT = s;
1932 }
1933 FPSCR_END(Rc);
19340.59,6.FRT,11.FRA,16.FRB,21./,26.18,31.Rc:A:f:fdivs:Floating Divide Single
1935 FPSCR_BEGIN;
1936 if (is_invalid_operation(processor, cia,
1937 *frA, *frB,
1938 fpscr_vxsnan | fpscr_vxzdz,
1939 1, /*single?*/
1940 0) /*negate?*/) {
1941 invalid_arithemetic_operation(processor, cia,
1942 frT, *frA, *frB, 0,
1943 0, /*instruction_is_frsp*/
1944 0, /*instruction_is_convert_to_64bit*/
1945 0, /*instruction_is_convert_to_32bit*/
1946 1); /*single-precision*/
1947 }
1948 else {
1949 /*HACK!*/
1950 float s = *(double*)frA / *(double*)frB;
1951 *(double*)frT = s;
1952 }
1953 FPSCR_END(Rc);
1954
19550.63,6.FRT,11.FRA,16.FRB,21.FRC,26.29,31.Rc:A:f:fmadd:Floating Multiply-Add
1956 FPSCR_BEGIN;
1957 double product; /*HACK! - incorrectly loosing precision ... */
1958 /* compute the multiply */
1959 if (is_invalid_operation(processor, cia,
1960 *frA, *frC,
1961 fpscr_vxsnan | fpscr_vximz,
1962 0, /*single?*/
1963 0) /*negate?*/) {
1964 invalid_arithemetic_operation(processor, cia,
1965 (unsigned64*)&product, *frA, 0, *frC,
1966 0, /*instruction_is_frsp*/
1967 0, /*instruction_is_convert_to_64bit*/
1968 0, /*instruction_is_convert_to_32bit*/
1969 0); /*single-precision*/
1970 }
1971 else {
1972 /*HACK!*/
1973 product = *(double*)frA * *(double*)frC;
1974 }
1975 /* compute the add */
1976 if (is_invalid_operation(processor, cia,
1977 product, *frB,
1978 fpscr_vxsnan | fpscr_vxisi,
1979 0, /*single?*/
1980 0) /*negate?*/) {
1981 invalid_arithemetic_operation(processor, cia,
1982 frT, product, *frB, 0,
1983 0, /*instruction_is_frsp*/
1984 0, /*instruction_is_convert_to_64bit*/
1985 0, /*instruction_is_convert_to_32bit*/
1986 0); /*single-precision*/
1987 }
1988 else {
1989 /*HACK!*/
1990 double s = product + *(double*)frB;
1991 *(double*)frT = s;
1992 }
1993 FPSCR_END(Rc);
19940.59,6.FRT,11.FRA,16.FRB,21.FRC,26.29,31.Rc:A:f::Floating Multiply-Add Single
1995
19960.63,6.FRT,11.FRA,16.FRB,21.FRC,26.28,31.Rc:A:f::Floating Multiply-Subtract
19970.59,6.FRT,11.FRA,16.FRB,21.FRC,26.28,31.Rc:A:f::Floating Multiply-Subtract Single
1998
19990.63,6.FRT,11.FRA,16.FRB,21.FRC,26.31,31.Rc:A:f::Floating Negative Multiply-Add
20000.59,6.FRT,11.FRA,16.FRB,21.FRC,26.31,31.Rc:A:f::Floating Negative Multiply-Add Single
2001
20020.63,6.FRT,11.FRA,16.FRB,21.FRC,26.30,31.Rc:A:f::Floating Negative Multiply-Subtract
20030.59,6.FRT,11.FRA,16.FRB,21.FRC,26.30,31.Rc:A:f::Floating Negative Multiply-Subtract Single
2004
2005
2006#
2007# I.4.6.6 Floating-Point Rounding and Conversion Instructions
2008#
2009
20100.63,6.FRT,11./,16.FRB,21.12,31.Rc:X:f::Floating Round to Single-Precision
2011 int sign;
2012 int exp;
2013 unsigned64 frac_grx;
2014 /* split off cases for what to do */
2015 if (EXTRACTED64(*frB, 1, 11) < 897
2016 && EXTRACTED64(*frB, 1, 63) > 0) {
2017 if ((FPSCR & fpscr_ue) == 0) goto Disabled_Exponent_Underflow;
2018 if ((FPSCR & fpscr_ue) != 0) goto Enabled_Exponent_Underflow;
2019 }
2020 if (EXTRACTED64(*frB, 1, 11) > 1150
2021 && EXTRACTED64(*frB, 1, 11) < 2047) {
2022 if ((FPSCR & fpscr_oe) == 0) goto Disabled_Exponent_Overflow;
2023 if ((FPSCR & fpscr_oe) != 0) goto Enabled_Exponent_Overflow;
2024 }
2025 if (EXTRACTED64(*frB, 1, 11) > 896
2026 && EXTRACTED64(*frB, 1, 11) < 1151) goto Normal_Operand;
2027 if (EXTRACTED64(*frB, 1, 63) == 0) goto Zero_Operand;
2028 if (EXTRACTED64(*frB, 1, 11) == 2047) {
2029 if (EXTRACTED64(*frB, 12, 63) == 0) goto Infinity_Operand;
2030 if (EXTRACTED64(*frB, 12, 12) == 1) goto QNaN_Operand;
2031 if (EXTRACTED64(*frB, 12, 12) == 0
2032 && EXTRACTED64(*frB, 13, 63) > 0) goto SNaN_Operand;
2033 }
2034 /* handle them */
2035 Disabled_Exponent_Underflow:
2036 sign = EXTRACTED64(*frB, 0, 0);
2037 if (EXTRACTED64(*frB, 1, 11) == 0) {
2038 exp = -1022;
2039 frac_grx = INSERTED64(EXTRACTED64(*frB, 12, 63), 1, 52);
2040 }
2041 if (EXTRACTED64(*frB, 1, 11) > 0) {
2042 exp = EXTRACTED64(*frB, 1, 11) - 1023;
2043 frac_grx = BIT64(0) | INSERTED64(EXTRACTED64(*frB, 12, 63), 1, 52);
2044 }
2045 Denormalize_Operand:
2046 /* G|R|X == zero from above */
2047 while (exp < -126) {
2048 exp = exp - 1;
2049 frac_grx = (INSERTED64(EXTRACTED64(frac_grx, 0, 54), 1, 55)
2050 | MASKED64(frac_grx, 55, 55));
2051 }
2052 FPSCR_SET_UX(EXTRACTED64(frac_grx, 24, 55) > 0);
2053 Round_Single(processor, sign, &exp, &frac_grx);
2054 FPSCR_SET_XX(FPSCR & fpscr_fi);
2055 if (EXTRACTED64(frac_grx, 0, 52) == 0) {
2056 *frT = INSERTED64(sign, 0, 0);
2057 if (sign == 0) FPSCR_SET_FPRF(fpscr_rf_pos_zero);
2058 if (sign == 1) FPSCR_SET_FPRF(fpscr_rf_neg_zero);
2059 }
2060 if (EXTRACTED64(frac_grx, 0, 52) > 0) {
2061 if (EXTRACTED64(frac_grx, 0, 0) == 1) {
2062 if (sign == 0) FPSCR_SET_FPRF(fpscr_rf_pos_normal_number);
2063 if (sign == 1) FPSCR_SET_FPRF(fpscr_rf_neg_normal_number);
2064 }
2065 if (EXTRACTED64(frac_grx, 0, 0) == 0) {
2066 if (sign == 0) FPSCR_SET_FPRF(fpscr_rf_pos_denormalized_number);
2067 if (sign == 1) FPSCR_SET_FPRF(fpscr_rf_neg_denormalized_number);
2068 }
2069 /*Normalize_Operand:*/
2070 while (EXTRACTED64(frac_grx, 0, 0) == 0) {
2071 exp = exp - 1;
2072 frac_grx = INSERTED64(EXTRACTED64(frac_grx, 1, 52), 0, 51);
2073 }
2074 *frT = (INSERTED64(sign, 0, 0)
2075 | INSERTED64(exp + 1023, 1, 11)
2076 | INSERTED64(EXTRACTED64(frac_grx, 1, 52), 12, 63));
2077 }
2078 goto Done;
2079 Enabled_Exponent_Underflow:
2080 FPSCR_SET_UX(1);
2081 sign = EXTRACTED64(*frB, 0, 0);
2082 if (EXTRACTED64(*frB, 1, 11) == 0) {
2083 exp = -1022;
2084 frac_grx = INSERTED64(EXTRACTED64(*frB, 12, 63), 1, 52);
2085 }
2086 if (EXTRACTED64(*frB, 1, 11) > 0) {
2087 exp = EXTRACTED64(*frB, 1, 11) - 1023;
2088 frac_grx = (BIT64(0) |
2089 INSERTED64(EXTRACTED64(*frB, 12, 63), 1, 52));
2090 }
2091 /*Normalize_Operand:*/
2092 while (EXTRACTED64(frac_grx, 0, 0) == 0) {
2093 exp = exp - 1;
2094 frac_grx = INSERTED64(EXTRACTED64(frac_grx, 1, 52), 0, 51);
2095 }
2096 Round_Single(processor, sign, &exp, &frac_grx);
2097 FPSCR_SET_XX(FPSCR & fpscr_fi);
2098 exp = exp + 192;
2099 *frT = (INSERTED64(sign, 0, 0)
2100 | INSERTED64(exp + 1023, 1, 11)
2101 | INSERTED64(EXTRACTED64(frac_grx, 1, 52), 12, 63));
2102 if (sign == 0) FPSCR_SET_FPRF(fpscr_rf_pos_normal_number);
2103 if (sign == 1) FPSCR_SET_FPRF(fpscr_rf_neg_normal_number);
2104 goto Done;
2105 Disabled_Exponent_Overflow:
2106 FPSCR_SET_OX(1);
2107 if ((FPSCR & fpscr_rn) == fpscr_rn_round_to_nearest) {
2108 if (EXTRACTED64(*frB, 0, 0) == 0) {
2109 *frT = INSERTED64(0x7FF00000, 0, 31) | 0x00000000;
2110 FPSCR_SET_FPRF(fpscr_rf_pos_infinity);
2111 }
2112 if (EXTRACTED64(*frB, 0, 0) == 1) {
2113 *frT = INSERTED64(0xFFF00000, 0, 31) | 0x00000000;
2114 FPSCR_SET_FPRF(fpscr_rf_neg_infinity);
2115 }
2116 }
2117 if ((FPSCR & fpscr_rn) == fpscr_rn_round_towards_zero) {
2118 if (EXTRACTED64(*frB, 0, 0) == 0) {
2119 *frT = INSERTED64(0x47EFFFFF, 0, 31) | 0xE0000000;
2120 FPSCR_SET_FPRF(fpscr_rf_pos_normal_number);
2121 }
2122 if (EXTRACTED64(*frB, 0, 0) == 1) {
2123 *frT = INSERTED64(0xC7EFFFFF, 0, 31) | 0xE0000000;
2124 FPSCR_SET_FPRF(fpscr_rf_neg_normal_number);
2125 }
2126 }
2127 if ((FPSCR & fpscr_rn) == fpscr_rn_round_towards_pos_infinity) {
2128 if (EXTRACTED64(*frB, 0, 0) == 0) {
2129 *frT = INSERTED64(0x7FF00000, 0, 31) | 0x00000000;
2130 FPSCR_SET_FPRF(fpscr_rf_pos_infinity);
2131 }
2132 if (EXTRACTED64(*frB, 0, 0) == 1) {
2133 *frT = INSERTED64(0xC7EFFFFF, 0, 31) | 0xE0000000;
2134 FPSCR_SET_FPRF(fpscr_rf_neg_normal_number);
2135 }
2136 }
2137 if ((FPSCR & fpscr_rn) == fpscr_rn_round_towards_neg_infinity) {
2138 if (EXTRACTED64(*frB, 0, 0) == 0) {
2139 *frT = INSERTED64(0x47EFFFFF, 0, 31) | 0xE0000000;
2140 FPSCR_SET_FPRF(fpscr_rf_pos_normal_number);
2141 }
2142 if (EXTRACTED64(*frB, 0, 0) == 1) {
2143 *frT = INSERTED64(0xFFF00000, 0, 31) | 0x00000000;
2144 FPSCR_SET_FPRF(fpscr_rf_neg_infinity);
2145 }
2146 }
2147 /* FPSCR[FR] <- undefined */
2148 FPSCR_SET_FI(1);
2149 FPSCR_SET_XX(1);
2150 goto Done;
2151 Enabled_Exponent_Overflow:
2152 sign = EXTRACTED64(*frB, 0, 0);
2153 exp = EXTRACTED64(*frB, 1, 11) - 1023;
2154 frac_grx = BIT64(0) | INSERTED64(EXTRACTED64(*frB, 12, 63), 1, 52);
2155 Round_Single(processor, sign, &exp, &frac_grx);
2156 FPSCR_SET_XX(FPSCR & fpscr_fi);
2157 Enabled_Overflow:
2158 FPSCR_SET_OX(1);
2159 exp = exp - 192;
2160 *frT = (INSERTED64(sign, 0, 0)
2161 | INSERTED64(exp + 1023, 1, 11)
2162 | INSERTED64(EXTRACTED64(frac_grx, 1, 52), 12, 63));
2163 if (sign == 0) FPSCR_SET_FPRF(fpscr_rf_pos_normal_number);
2164 if (sign == 1) FPSCR_SET_FPRF(fpscr_rf_neg_normal_number);
2165 goto Done;
2166 Zero_Operand:
2167 *frT = *frB;
2168 if (EXTRACTED64(*frB, 0, 0) == 0) FPSCR_SET_FPRF(fpscr_rf_pos_zero);
2169 if (EXTRACTED64(*frB, 0, 0) == 1) FPSCR_SET_FPRF(fpscr_rf_neg_zero);
2170 FPSCR_SET_FR(0);
2171 FPSCR_SET_FI(0);
2172 goto Done;
2173 Infinity_Operand:
2174 *frT = *frB;
2175 if (EXTRACTED64(*frB, 0, 0) == 0) FPSCR_SET_FPRF(fpscr_rf_pos_infinity);
2176 if (EXTRACTED64(*frB, 0, 0) == 1) FPSCR_SET_FPRF(fpscr_rf_neg_infinity);
2177 FPSCR_SET_FR(0);
2178 FPSCR_SET_FI(0);
2179 goto Done;
2180 QNaN_Operand:
2181 *frT = INSERTED64(EXTRACTED64(*frB, 0, 34), 0, 34);
2182 FPSCR_SET_FPRF(fpscr_rf_quiet_nan);
2183 FPSCR_SET_FR(0);
2184 FPSCR_SET_FI(0);
2185 goto Done;
2186 SNaN_Operand:
2187 FPSCR_OR_VX(fpscr_vxsnan);
2188 if ((FPSCR & fpscr_ve) == 0) {
2189 *frT = (MASKED64(*frB, 0, 11)
2190 | BIT64(12)
2191 | MASKED64(*frB, 13, 34));
2192 FPSCR_SET_FPRF(fpscr_rf_quiet_nan);
2193 }
2194 FPSCR_SET_FR(0);
2195 FPSCR_SET_FI(0);
2196 goto Done;
2197 Normal_Operand:
2198 sign = EXTRACTED64(*frB, 0, 0);
2199 exp = EXTRACTED64(*frB, 1, 11) - 1023;
2200 frac_grx = BIT64(0) | INSERTED64(EXTRACTED64(*frB, 12, 63), 1, 52);
2201 Round_Single(processor, sign, &exp, &frac_grx);
2202 FPSCR_SET_XX(FPSCR & fpscr_fi);
2203 if (exp > 127 && (FPSCR & fpscr_oe) == 0) goto Disabled_Exponent_Overflow;
2204 if (exp > 127 && (FPSCR & fpscr_oe) != 0) goto Enabled_Overflow;
2205 *frT = (INSERTED64(sign, 0, 0)
2206 | INSERTED64(exp + 1023, 1, 11)
2207 | INSERTED64(EXTRACTED64(frac_grx, 1, 52), 12, 63));
2208 if (sign == 0) FPSCR_SET_FPRF(fpscr_rf_pos_normal_number);
2209 if (sign == 1) FPSCR_SET_FPRF(fpscr_rf_neg_normal_number);
2210 goto Done;
2211 Done:
22120.63,6.FRT,11./,16.FRB,21.814,31.Rc:X:64,f::Floating Convert To Integer Doubleword
22130.63,6.FRT,11./,16.FRB,21.815,31.Rc:X:64,f::Floating Convert To Integer Doubleword with round towards Zero
22140.63,6.FRT,11./,16.FRB,21.14,31.Rc:X:f::Floating Convert To Integer Word
22150.63,6.FRT,11./,16.FRB,21.15,31.Rc:X:f:fctiwz:Floating Convert To Integer Word with round towards Zero
2216 FPSCR_BEGIN;
2217 convert_to_integer(processor, cia,
2218 frT, *frB,
2219 fpscr_rn_round_towards_zero, 32);
2220 FPSCR_END(Rc);
22210.63,6.FRT,11./,16.FRB,21.846,31.Rc:X:64,f::Floating Convert from Integer Doubleword
2222 int sign = EXTRACTED64(*frB, 0, 0);
2223 int exp = 63;
2224 unsigned64 frac = *frB;
2225 if (frac == 0) goto Zero_Operand;
2226 if (sign == 1) frac = ~frac + 1;
2227 while (EXTRACTED64(frac, 0, 0) == 0) {
2228 /*??? do the loop 0 times if (FRB) = max negative integer */
2229 frac = INSERTED64(EXTRACTED64(frac, 1, 63), 0, 62);
2230 exp = exp - 1;
2231 }
2232 Round_Float(processor, sign, &exp, &frac, FPSCR & fpscr_rn);
2233 if (sign == 0) FPSCR_SET_FPRF(fpscr_rf_pos_normal_number);
2234 if (sign == 1) FPSCR_SET_FPRF(fpscr_rf_pos_normal_number);
2235 *frT = (INSERTED64(sign, 0, 0)
2236 | INSERTED64(exp + 1023, 1, 11)
2237 | INSERTED64(EXTRACTED64(frac, 1, 52), 12, 63));
2238 goto Done;
2239 /**/
2240 Zero_Operand:
2241 FPSCR_SET_FR(0);
2242 FPSCR_SET_FI(0);
2243 FPSCR_SET_FPRF(fpscr_rf_pos_zero);
2244 *frT = 0;
2245 goto Done;
2246 /**/
2247 Done:
2248
2249#
2250# I.4.6.7 Floating-Point Compare Instructions
2251#
2252
22530.63,6.BF,9./,11.FRA,16.FRB,21.0,31./:X:f:fcmpu:Floating Compare Unordered
2254 FPSCR_BEGIN;
2255 unsigned c;
2256 if (is_NaN(*frA, 0) || is_NaN(*frB, 0))
2257 c = cr_i_summary_overflow; /* 0b0001 - (FRA) ? (FRB) */
2258 else if (is_less_than(frA, frB))
2259 c = cr_i_negative; /* 0b1000 - (FRA) < (FRB) */
2260 else if (is_greater_than(frA, frB))
2261 c = cr_i_positive; /* 0b0100 - (FRA) > (FRB) */
2262 else
2263 c = cr_i_zero; /* 0b0010 - (FRA) = (FRB) */
2264 FPSCR_SET_FPCC(c);
2265 CR_SET(BF, c); /* CR[4*BF..4*BF+3] = c */
2266 if (is_SNaN(*frA, 0) || is_SNaN(*frB, 0))
2267 FPSCR_OR_VX(fpscr_vxsnan);
2268 FPSCR_END(0);
22690.63,6.BF,9./,11.FRA,16.FRB,21.32,31./:X:f:fcmpo:Floating Compare Ordered
2270 FPSCR_BEGIN;
2271 unsigned c;
2272 if (is_NaN(*frA, 0) || is_NaN(*frB, 0))
2273 c = cr_i_summary_overflow; /* 0b0001 - (FRA) ? (FRB) */
2274 else if (is_less_than(frA, frB))
2275 c = cr_i_negative; /* 0b1000 - (FRA) < (FRB) */
2276 else if (is_greater_than(frA, frB))
2277 c = cr_i_positive; /* 0b0100 - (FRA) > (FRB) */
2278 else
2279 c = cr_i_zero; /* 0b0010 - (FRA) = (FRB) */
2280 FPSCR_SET_FPCC(c);
2281 CR_SET(BF, c); /* CR[4*BF..4*BF+3] = c */
2282 if (is_SNaN(*frA, 0) || is_SNaN(*frB, 0)) {
2283 FPSCR_OR_VX(fpscr_vxsnan);
2284 if ((FPSCR & fpscr_ve) == 0)
2285 FPSCR_OR_VX(fpscr_vxvc);
2286 }
2287 else if (is_QNaN(*frA, 0) || is_QNaN(*frB, 0)) {
2288 FPSCR_OR_VX(fpscr_vxvc);
2289 }
2290 FPSCR_END(0);
2291
2292
2293#
2294# I.4.6.8 Floating-Point Status and Control Register Instructions
2295#
2296
22970.63,6.FRT,11./,16./,21.583,31.Rc:X:f::Move From FPSCR
22980.63,6.BF,9./,11.BFA,14./,16./,21.64,31./:X:f::Move to Condition Register from FPSCR
22990.64,6.BF,9./,11./,16.U,20./,21.134,31.Rc:X:f::Move To FPSCR Field Immediate
23000.63,6./,7.FLM,15./,16.FRB,21.711,31.Rc:XFL:f::Move To FPSCR Fields
23010.63,6.BT,11./,16./,21.70,31.Rc:X:f::Move To FPSCR Bit 0
23020.63,6.BT,11./,16./,21.38,31.Rc:X:f::Move To FPSCR Bit 1
2303
2304
2305#
2306# I.A.1.1 Floating-Point Store Instruction
2307#
23080.31,6.FRS,11.RA,16.RB,21.983,31./:X:f::Store Floating-Point as Integer Word Indexed
2309
2310#
2311# I.A.1.2 Floating-Point Arithmetic Instructions
2312#
2313
23140.63,6.FRT,11./,16.FRB,21./,26.22,31.Rc:A:f::Floating Square Root
23150.59,6.FRT,11./,16.FRB,21./,26.22,31.Rc:A:f::Floating Square Root Single
2316
23170.59,6.FRT,11./,16.FRB,21./,26.24,31.Rc:A:f::Floating Reciprocal Estimate Single
23180.63,6.FRT,11./,16.FRB,21./,26.26,31.Rc:A:f::Floating Reciprocal Square Root Estimate
2319
2320#
2321# I.A.1.3 Floating-Point Select Instruction
2322#
2323
23240.63,6.FRT,11.FRA,16.FRB,21.FRC,26.23,31.Rc:A:f::Floating Select
2325
2326
2327#
2328# II.3.2 Cache Management Instructions
2329#
2330
23310.31,6./,11.RA,16.RB,21.982,31./:X::icbi:Instruction Cache Block Invalidate
2332 ; /* nop for now */
2333
23340.19,6./,11./,16./,21.150,31./:XL::isync:Instruction Synchronize
2335 cpu_synchronize_context(processor);
2336
2337
2338#
2339# II.3.2.2 Data Cache Instructions
2340#
2341
23420.31,6./,11.RA,16.RB,21.278,31./:X:::Data Cache Block Touch
056e975c
MM		 2343 ; /* nop for now */
2344
c143ef62 23450.31,6./,11.RA,16.RB,21.246,31./:X:::Data Cache Block Touch for Store
056e975c
MM		 2346 ; /* nop for now */
2347
c143ef62 23480.31,6./,11.RA,16.RB,21.1014,31./:X:::Data Cache Block set to Zero
056e975c
MM		 2349 ; /* nop for now */
2350
c143ef62 23510.31,6./,11.RA,16.RB,21.54,31./:X:::Data Cache Block Store
056e975c
MM		 2352 ; /* nop for now */
2353
c143ef62 23540.31,6./,11.RA,16.RB,21.86,31./:X:::Data Cache Block Flush
056e975c 2355 ; /* nop for now */
c143ef62
MM		 2356
2357#
2358# II.3.3 Envorce In-order Execution of I/O Instruction
2359#
2360
23610.31,6./,11./,16./,21.854,31./:X::eieio:Enforce In-order Execution of I/O
2362 /* Since this model has no instruction overlap
2363 this instruction need do nothing */
2364
2365#
2366# II.4.1 Time Base Instructions
2367#
2368
23690.31,6.RT,11.tbr,21.371,31./:XFX::mftb:Move From Time Base
2370 int n = (tbr{5:9} << 5) | tbr{0:4};
2371 if (n == 268) {
2372 if (is_64bit_implementation) *rT = TB;
2373 else *rT = EXTRACTED64(TB, 32, 63);
2374 }
2375 else if (n == 269) {
2376 if (is_64bit_implementation) *rT = EXTRACTED64(TB, 0, 31);
2377 else *rT = EXTRACTED64(TB, 0, 31);
2378 }
2379 else
2380 program_interrupt(processor, cia,
2381 illegal_instruction_program_interrupt);
2382
2383
2384#
2385# III.2.3.1 System Linkage Instructions
2386#
2387
2388#0.17,6./,11./,16./,30.1,31./:SC:::System Call
23890.19,6./,11./,16./,21.50,31./:XL:::Return From Interrupt
2390
2391#
2392# III.3.4.1 Move to/from System Register Instructions
2393#
2394
2395#0.31,6.RS,11.spr,21.467,31./:XFX:::Move To Special Purpose Register
2396#0.31,6.RT,11.spr,21.339,31./:XFX:::Move From Special Purpose Register
23970.31,6.RS,11./,16./,21.146,31./:X:::Move To Machine State Register
2398 if (IS_PROBLEM_STATE(processor))
2399 program_interrupt(processor, cia,
2400 privileged_instruction_program_interrupt);
2401 else
2402 MSR = *rS;
24030.31,6.RT,11./,16./,21.83,31./:X:::Move From Machine State Register
2404 if (IS_PROBLEM_STATE(processor))
2405 program_interrupt(processor, cia,
2406 privileged_instruction_program_interrupt);
2407 else
2408 *rT = MSR;
2409
2410
2411#
2412# III.4.11.1 Cache Management Instructions
2413#
2414
24150.31,6./,11.RA,16.RB,21.470,31./:X::dcbi:Data Cache Block Invalidate
2416 ; /* nop for now */
2417
2418#
2419# III.4.11.2 Segment Register Manipulation Instructions
2420#
2421
24220.31,6.RS,11./,12.SR,16./,21.210,31./:X:32:mtsr %SR,%RS:Move To Segment Register
2423 if (IS_PROBLEM_STATE(processor))
2424 program_interrupt(processor, cia,
2425 privileged_instruction_program_interrupt);
2426 else
2427 SEGREG(SR) = *rS;
24280.31,6.RS,11./,16.RB,21.242,31./:X:32:mtsrin %RS,%RB:Move To Segment Register Indirect
2429 if (IS_PROBLEM_STATE(processor))
2430 program_interrupt(processor, cia,
2431 privileged_instruction_program_interrupt);
2432 else
2433 SEGREG(EXTRACTED32(*rB, 0, 3)) = *rS;
24340.31,6.RT,11./,12.SR,16./,21.595,31./:X:32:mfsr %RT,%RS:Move From Segment Register
2435 if (IS_PROBLEM_STATE(processor))
2436 program_interrupt(processor, cia,
2437 privileged_instruction_program_interrupt);
2438 else
2439 *rT = SEGREG(SR);
24400.31,6.RT,11./,16.RB,21.659,31./:X:32:mfsrin %RT,%RB:Move From Segment Register Indirect
2441 if (IS_PROBLEM_STATE(processor))
2442 program_interrupt(processor, cia,
2443 privileged_instruction_program_interrupt);
2444 else
2445 *rT = SEGREG(EXTRACTED32(*rB, 0, 3));
2446
2447
2448#
2449# III.4.11.3 Lookaside Buffer Management Instructions (Optional)
2450#
2451
24520.31,6./,11./,16.RB,21.434,31./:X:64::SLB Invalidate Entry
24530.31,6./,11./,16./,21.498,31./:X:64::SLB Invalidate All
2454
24550.31,6./,11./,16.RB,21.306,31./:X:::TLB Invalidate Entry
24560.31,6./,11./,16./,21.370,31./:X:::TLB Invalidate All
2457
24580.31,6./,11./,16./,21.566,31./:X:::TLB Sychronize
2459
2460
2461#
2462# III.A.1.2 External Access Instructions
2463#
2464
24650.31,6.RT,11.RA,16.RB,21.310,31./:X:earwax::External Control In Word Indexed
24660.31,6.RS,11.RA,16.RB,21.438,31./:X:earwax::External Control Out Word Indexed
GDB Binutils - Deliverables
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