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3666a048 | 1 | /* Copyright 2016-2021 Free Software Foundation, Inc. |
ddd44b70 DD |
2 | Contributed by Dimitar Dimitrov <dimitar@dinux.eu> |
3 | ||
4 | This file is part of the PRU simulator. | |
5 | ||
6 | This library is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 3 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, see <http://www.gnu.org/licenses/>. */ | |
18 | ||
19 | #ifndef PRU_SIM_MAIN | |
20 | #define PRU_SIM_MAIN | |
21 | ||
f4146441 MF |
22 | #include "config.h" |
23 | ||
ddd44b70 DD |
24 | #include <stdint.h> |
25 | #include <stddef.h> | |
26 | #include "pru.h" | |
27 | #include "sim-basics.h" | |
28 | ||
29 | #include "sim-base.h" | |
30 | ||
31 | /* The machine state. | |
32 | This state is maintained in host byte order. The | |
33 | fetch/store register functions must translate between host | |
34 | byte order and the target processor byte order. | |
35 | Keeping this data in target byte order simplifies the register | |
36 | read/write functions. Keeping this data in host order improves | |
37 | the performance of the simulator. Simulation speed is deemed more | |
38 | important. */ | |
39 | ||
40 | /* For clarity, please keep the same relative order in this enum as in the | |
41 | corresponding group of GP registers. | |
42 | ||
43 | In PRU ISA, Multiplier-Accumulator-Unit's registers are like "shadows" of | |
44 | the GP registers. MAC registers are implicitly addressed when executing | |
45 | the XIN/XOUT instructions to access them. Transfer to/from a MAC register | |
46 | can happen only from/to its corresponding GP peer register. */ | |
47 | ||
48 | enum pru_macreg_id { | |
49 | /* MAC register CPU GP register Description. */ | |
50 | PRU_MACREG_MODE, /* r25 */ /* Mode (MUL/MAC). */ | |
51 | PRU_MACREG_PROD_L, /* r26 */ /* Lower 32 bits of product. */ | |
52 | PRU_MACREG_PROD_H, /* r27 */ /* Higher 32 bits of product. */ | |
53 | PRU_MACREG_OP_0, /* r28 */ /* First operand. */ | |
54 | PRU_MACREG_OP_1, /* r29 */ /* Second operand. */ | |
55 | PRU_MACREG_ACC_L, /* N/A */ /* Accumulator (not exposed) */ | |
56 | PRU_MACREG_ACC_H, /* N/A */ /* Higher 32 bits of MAC | |
57 | accumulator. */ | |
58 | PRU_MAC_NREGS | |
59 | }; | |
60 | ||
61 | struct pru_regset | |
62 | { | |
63 | uint32_t regs[32]; /* Primary registers. */ | |
64 | uint16_t pc; /* IMEM _word_ address. */ | |
65 | uint32_t pc_addr_space_marker; /* IMEM virtual linker offset. This | |
66 | is the artificial offset that | |
67 | we invent in order to "separate" | |
68 | the DMEM and IMEM memory spaces. */ | |
69 | unsigned int carry : 1; | |
70 | uint32_t ctable[32]; /* Constant offsets table for xBCO. */ | |
71 | uint32_t macregs[PRU_MAC_NREGS]; | |
72 | uint32_t scratchpads[XFRID_MAX + 1][32]; | |
73 | struct { | |
74 | uint16_t looptop; /* LOOP top (PC of loop instr). */ | |
75 | uint16_t loopend; /* LOOP end (PC of loop end label). */ | |
76 | int loop_in_progress; /* Whether to check for PC==loopend. */ | |
77 | uint32_t loop_counter; /* LOOP counter. */ | |
78 | } loop; | |
79 | int cycles; | |
80 | int insts; | |
81 | }; | |
82 | ||
83 | struct _sim_cpu { | |
84 | struct pru_regset pru_cpu; | |
85 | sim_cpu_base base; | |
86 | }; | |
87 | ||
88 | struct sim_state { | |
89 | sim_cpu *cpu[MAX_NR_PROCESSORS]; | |
90 | ||
91 | sim_state_base base; | |
92 | }; | |
93 | #endif /* PRU_SIM_MAIN */ |