[deliverable/binutils-gdb.git] / sim / riscv / configure.ac

dnl Process this file with autoconf to produce a configure script.
AC_INIT(Makefile.in)
sinclude(../common/acinclude.m4)

SIM_AC_COMMON

SIM_AC_OPTION_ENDIAN(LITTLE)
SIM_AC_OPTION_ALIGNMENT(NONSTRICT_ALIGNMENT)
SIM_AC_OPTION_ENVIRONMENT
SIM_AC_OPTION_WARNINGS

# Select the default model for the target.
riscv_model=
case "${target}" in
riscv32*) riscv_model="RV32G" ;;
riscv*) riscv_model="RV64G" ;;
esac
SIM_AC_OPTION_DEFAULT_MODEL(${riscv_model})

# Select the bitsize of the target.
riscv_addr_bitsize=
case "${target}" in
riscv32*) riscv_addr_bitsize=32 ;;
riscv*) riscv_addr_bitsize=64 ;;
esac
SIM_AC_OPTION_BITSIZE($riscv_addr_bitsize)

SIM_AC_OUTPUT
Commit	Line	Data
b9249c46 MF	1	dnl Process this file with autoconf to produce a configure script.
	2	AC_INIT(Makefile.in)
	3	sinclude(../common/acinclude.m4)
	4
	5	SIM_AC_COMMON
	6
	7	SIM_AC_OPTION_ENDIAN(LITTLE)
	8	SIM_AC_OPTION_ALIGNMENT(NONSTRICT_ALIGNMENT)
	9	SIM_AC_OPTION_ENVIRONMENT
	10	SIM_AC_OPTION_WARNINGS
	11
	12	# Select the default model for the target.
	13	riscv_model=
	14	case "${target}" in
	15	riscv32*) riscv_model="RV32G" ;;
	16	riscv*) riscv_model="RV64G" ;;
	17	esac
	18	SIM_AC_OPTION_DEFAULT_MODEL(${riscv_model})
	19
	20	# Select the bitsize of the target.
	21	riscv_addr_bitsize=
	22	case "${target}" in
	23	riscv32*) riscv_addr_bitsize=32 ;;
	24	riscv*) riscv_addr_bitsize=64 ;;
	25	esac
	26	SIM_AC_OPTION_BITSIZE($riscv_addr_bitsize)
	27
	28	SIM_AC_OUTPUT