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594266fc SC |
1 | #define MSIZE (256*1024) |
2 | #define MMASKL ((MSIZE -1) & ~3) | |
3 | #define MMASKW ((MSIZE -1) & ~1) | |
4 | #define MMASKB ((MSIZE -1) & ~0) | |
5 | /* Simulator for the Hitachi SH architecture. | |
6 | ||
7 | Written by Steve Chamberlain of Cygnus Support. | |
8 | sac@cygnus.com | |
9 | ||
10 | This file is part of SH sim | |
11 | ||
12 | ||
13 | THIS SOFTWARE IS NOT COPYRIGHTED | |
14 | ||
15 | Cygnus offers the following for use in the public domain. Cygnus | |
16 | makes no warranty with regard to the software or it's performance | |
17 | and the user accepts the software "AS IS" with all faults. | |
18 | ||
19 | CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO | |
20 | THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. | |
22 | ||
23 | */ | |
24 | ||
25 | #include <signal.h> | |
26 | #include <sys/times.h> | |
27 | #include <sys/param.h> | |
28 | ||
29 | #define O_RECOMPILE 85 | |
30 | #define DEFINE_TABLE | |
31 | ||
32 | #define DISASSEMBLER_TABLE | |
33 | ||
34 | #define SBIT(x) ((x)&sbit) | |
35 | #define R0 saved_state.asregs.regs[0] | |
36 | #define Rn saved_state.asregs.regs[n] | |
37 | #define Rm saved_state.asregs.regs[m] | |
38 | ||
39 | #define UR0 (unsigned long)(saved_state.asregs.regs[0]) | |
40 | #define UR (unsigned long)R | |
41 | #define UR (unsigned long)R | |
42 | ||
43 | #define SR0 saved_state.asregs.regs[0] | |
44 | ||
45 | #define GBR saved_state.asregs.gbr | |
46 | #define VBR saved_state.asregs.vbr | |
47 | #define MACH saved_state.asregs.mach | |
48 | #define MACL saved_state.asregs.macl | |
49 | #define GET_SR() (saved_state.asregs.sr.bits.t = T, saved_state.asregs.sr.word) | |
50 | #define SET_SR(x) {saved_state.asregs.sr.word = (x); T =saved_state.asregs.sr.bits.t;} | |
51 | ||
52 | #define PC pc | |
53 | #define C cycles | |
54 | ||
55 | #define LMEM(x) *((long *)(memory+(x&maskl))) | |
56 | #define BMEM(x) *((char *)(memory+(x&maskb))) | |
57 | #define UWMEM(x) *((unsigned short *)(memory+(x&maskw))) | |
58 | #define SWMEM(x) *((short *)(memory+(x&maskw))) | |
59 | #define WLAT(x,value) (LMEM(x) = value) | |
60 | #define RLAT(x) (LMEM(x)) | |
61 | ||
62 | #define WWAT(x,value) (UWMEM(x) = value) | |
63 | #define RSWAT(x) (SWMEM(x)) | |
64 | #define RUWAT(x) (UWMEM(x)) | |
65 | ||
66 | #define WBAT(x,value) (BMEM(x) = value) | |
67 | #define RBAT(x) (BMEM(x)) | |
68 | ||
69 | #define SEXT(x) ((int)((char)x)) | |
70 | #define SEXTW(y) ((int)((short)y)) | |
71 | #define M saved_state.asregs.sr.bits.m | |
72 | #define Q saved_state.asregs.sr.bits.q | |
73 | #define SL(TEMPPC) iword= RUWAT(TEMPPC); goto top; | |
74 | int debug; | |
75 | typedef union | |
76 | { | |
77 | ||
78 | struct | |
79 | { | |
80 | ||
81 | int regs[16]; | |
82 | int pc; | |
83 | int pr; | |
84 | ||
85 | int gbr; | |
86 | int vbr; | |
87 | int mach; | |
88 | int macl; | |
89 | ||
90 | ||
91 | union | |
92 | { | |
93 | struct | |
94 | { | |
95 | int d0:22; | |
96 | int m:1; | |
97 | int q:1; | |
98 | int i:4; | |
99 | int d1:2; | |
100 | int s:1; | |
101 | int t:1; | |
102 | } | |
103 | bits; | |
104 | int word; | |
105 | } | |
106 | sr; | |
107 | int ticks; | |
108 | int cycles; | |
109 | int insts; | |
110 | unsigned char *memory; | |
111 | int exception; | |
112 | ||
113 | } | |
114 | asregs; | |
115 | int asints[25]; | |
116 | ||
117 | } | |
118 | ||
119 | saved_state_type; | |
120 | ||
121 | ||
122 | ||
123 | saved_state_type saved_state; | |
124 | ||
125 | ||
126 | ||
127 | /*#include "../opcodes/sh-opc.h"*/ | |
128 | ||
129 | ||
130 | static int | |
131 | get_now () | |
132 | { | |
133 | struct tms b; | |
134 | times (&b); | |
135 | return b.tms_utime + b.tms_stime; | |
136 | } | |
137 | ||
138 | static int | |
139 | now_persec () | |
140 | { | |
141 | return HZ; | |
142 | } | |
143 | ||
144 | /* simulate a monitor trap */ | |
145 | trap (i, regs) | |
146 | int *regs; | |
147 | { | |
148 | switch (i) | |
149 | { | |
150 | case 1: | |
151 | printf ("%c", regs[0]); | |
152 | break; | |
153 | case 2: | |
154 | saved_state.asregs.exception = SIGQUIT; | |
155 | break; | |
156 | case 255: | |
157 | saved_state.asregs.exception = SIGILL; | |
158 | break; | |
159 | } | |
160 | ||
161 | } | |
162 | void | |
163 | control_c (sig, code, scp, addr) | |
164 | int sig; | |
165 | int code; | |
166 | char *scp; | |
167 | char *addr; | |
168 | { | |
169 | saved_state.asregs.exception = SIGINT; | |
170 | } | |
171 | ||
172 | ||
173 | int div1(R,m,n,T) | |
174 | int *R; | |
175 | int m; | |
176 | int n; | |
177 | int T; | |
178 | { | |
179 | unsigned long tmp0; | |
180 | unsigned char old_q, tmp1; | |
181 | ||
182 | old_q = Q; | |
183 | Q= R[n] <0; | |
184 | ||
185 | R[n] <<=1; | |
186 | R[n] |= T; | |
187 | ||
188 | switch (old_q) | |
189 | { | |
190 | case 0: | |
191 | switch (M) | |
192 | { | |
193 | case 0: | |
194 | tmp0 = R[n]; | |
195 | R[n] -= R[m]; | |
196 | tmp1 = (R[n] > tmp0) != Q; | |
197 | break; | |
198 | case 1: | |
199 | tmp0 = R[n]; | |
200 | R[n] += R[m]; | |
201 | tmp1 = (R[n] < tmp0) == Q; | |
202 | break; | |
203 | } | |
204 | break; | |
205 | case 1: | |
206 | switch (M) | |
207 | { | |
208 | case 0: | |
209 | tmp0 = R[n]; | |
210 | R[n] += R[m]; | |
211 | tmp1 = (R[n] < tmp0) != Q; | |
212 | break; | |
213 | case 1: | |
214 | tmp0 = R[n]; | |
215 | R[n] -= R[m]; | |
216 | tmp1 = (R[n] > tmp0) == Q; | |
217 | break; | |
218 | } | |
219 | break; | |
220 | ||
221 | } | |
222 | ||
223 | T=(Q==M); | |
224 | return T; | |
225 | ||
226 | } | |
227 | ||
228 | ||
229 | int | |
230 | sim_resume (step) | |
231 | { | |
232 | static int init1; | |
233 | int pc; | |
234 | register int cycles = 0; | |
235 | register int insts = 0; | |
236 | int tick_start = get_now (); | |
237 | void (*prev) (); | |
238 | extern unsigned char sh_jump_table0[]; | |
239 | ||
240 | register unsigned char *jump_table = sh_jump_table0; | |
241 | ||
242 | register int *R = &(saved_state.asregs.regs[0]); | |
243 | register int T; | |
244 | register int PR; | |
245 | ||
246 | register int maskb = MMASKB; | |
247 | register int maskw = MMASKW; | |
248 | register int maskl = MMASKL; | |
249 | register unsigned char *memory = saved_state.asregs.memory; | |
250 | register int sbit = (1<<31); | |
251 | ||
252 | prev = signal (SIGINT, control_c); | |
253 | ||
254 | if (step) | |
255 | { | |
256 | saved_state.asregs.exception = SIGTRAP; | |
257 | } | |
258 | else | |
259 | { | |
260 | saved_state.asregs.exception = 0; | |
261 | } | |
262 | ||
263 | pc = saved_state.asregs.pc; | |
264 | PR = saved_state.asregs.pr; | |
265 | T = saved_state.asregs.sr.bits.t; | |
266 | ||
267 | do | |
268 | { | |
269 | unsigned int iword = RUWAT (pc); | |
270 | unsigned long ult; | |
271 | ||
272 | insts++; | |
273 | top: | |
274 | ||
275 | #include "code.c" | |
276 | ||
277 | pc += 2; | |
278 | cycles++; | |
279 | } | |
280 | while (!saved_state.asregs.exception); | |
281 | ||
282 | if (saved_state.asregs.exception == SIGILL) | |
283 | { | |
284 | pc-=2; | |
285 | } | |
286 | ||
287 | saved_state.asregs.ticks += get_now () - tick_start; | |
288 | saved_state.asregs.cycles += cycles; | |
289 | saved_state.asregs.insts += insts; | |
290 | saved_state.asregs.pc = pc; | |
291 | saved_state.asregs.sr.bits.t = T; | |
292 | saved_state.asregs.pr = PR; | |
293 | ||
294 | signal (SIGINT, prev); | |
295 | } | |
296 | ||
297 | ||
298 | ||
299 | void | |
300 | sim_write (addr, buffer, size) | |
301 | long int addr; | |
302 | unsigned char *buffer; | |
303 | int size; | |
304 | { | |
305 | int i; | |
306 | init_pointers (); | |
307 | ||
308 | for (i = 0; i < size; i++) | |
309 | { | |
310 | saved_state.asregs.memory[MMASKB & (addr + i)] = buffer[i]; | |
311 | } | |
312 | } | |
313 | ||
314 | void | |
315 | sim_read (addr, buffer, size) | |
316 | long int addr; | |
317 | char *buffer; | |
318 | int size; | |
319 | { | |
320 | int i; | |
321 | ||
322 | init_pointers (); | |
323 | ||
324 | for (i = 0; i < size; i++) | |
325 | { | |
326 | buffer[i] = saved_state.asregs.memory[MMASKB & (addr + i)]; | |
327 | } | |
328 | } | |
329 | ||
330 | ||
331 | sim_store_register (rn, value) | |
332 | int rn; | |
333 | int value; | |
334 | { | |
335 | saved_state.asregs.regs[rn] = value; | |
336 | } | |
337 | ||
338 | sim_fetch_register (rn, buf) | |
339 | int rn; | |
340 | char *buf; | |
341 | { | |
342 | ||
343 | int value = ((int *) (&saved_state))[rn]; | |
344 | ||
345 | buf[0] = value >> 24; | |
346 | buf[1] = value >> 16; | |
347 | buf[2] = value >> 8; | |
348 | buf[3] = value >> 0; | |
349 | ||
350 | } | |
351 | ||
352 | int | |
353 | sim_trace () | |
354 | { | |
355 | ||
356 | int i; | |
357 | return 0; | |
358 | ||
359 | } | |
360 | ||
361 | sim_stop_signal () | |
362 | { | |
363 | return saved_state.asregs.exception; | |
364 | } | |
365 | ||
366 | sim_set_pc (x) | |
367 | { | |
368 | saved_state.asregs.pc = x; | |
369 | } | |
370 | ||
371 | ||
372 | ||
373 | sim_info () | |
374 | { | |
375 | double timetaken = (double) saved_state.asregs.ticks / (double) now_persec (); | |
376 | double virttime = saved_state.asregs.cycles / 10.0e6; | |
377 | ||
378 | printf ("\n\ninstructions executed %10d\n", saved_state.asregs.insts); | |
379 | printf ("cycles %10d\n", saved_state.asregs.cycles); | |
380 | printf ("real time taken %10.4f\n", timetaken); | |
381 | printf ("cycles/second %10d\n", (int)(saved_state.asregs.cycles/timetaken)); | |
382 | printf ("virtual time taked %10.4f\n", virttime); | |
383 | printf ("simulation ratio %10.4f\n", virttime / timetaken); | |
384 | } | |
385 | ||
386 | init_pointers () | |
387 | { | |
388 | if (!saved_state.asregs.memory) | |
389 | { | |
390 | saved_state.asregs.memory = (unsigned char *) (calloc (64, MSIZE / 64)); | |
391 | } | |
392 | } |