[deliverable/binutils-gdb.git] / sim / sh64 / cpu.h

/* CPU family header for sh64.

THIS FILE IS MACHINE GENERATED WITH CGEN.

Copyright 1996-2009 Free Software Foundation, Inc.

This file is part of the GNU simulators.

   This file is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   It is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.

   You should have received a copy of the GNU General Public License along
   with this program; if not, write to the Free Software Foundation, Inc.,
   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.

*/

#ifndef CPU_SH64_H
#define CPU_SH64_H

/* Maximum number of instructions that are fetched at a time.
   This is for LIW type instructions sets (e.g. m32r).  */
#define MAX_LIW_INSNS 1

/* Maximum number of instructions that can be executed in parallel.  */
#define MAX_PARALLEL_INSNS 1

/* CPU state information.  */
typedef struct {
  /* Hardware elements.  */
  struct {
  /* Program counter */
  UDI h_pc;
#define GET_H_PC() CPU (h_pc)
#define SET_H_PC(x) \
do { \
{\
CPU (h_ism) = ANDDI ((x), 1);\
CPU (h_pc) = ANDDI ((x), INVDI (1));\
}\
;} while (0)
  /* General purpose integer registers */
  DI h_gr[64];
#define GET_H_GR(index) ((((index) == (63))) ? (MAKEDI (0, 0)) : (CPU (h_gr[index])))
#define SET_H_GR(index, x) \
do { \
if ((((index)) != (63))) {\
CPU (h_gr[(index)]) = (x);\
} else {\
((void) 0); /*nop*/\
}\
;} while (0)
  /* Control registers */
  DI h_cr[64];
#define GET_H_CR(index) ((((index) == (0))) ? (ZEXTSIDI (CPU (h_sr))) : (CPU (h_cr[index])))
#define SET_H_CR(index, x) \
do { \
if ((((index)) == (0))) {\
CPU (h_sr) = (x);\
} else {\
CPU (h_cr[(index)]) = (x);\
}\
;} while (0)
  /* Status register */
  SI h_sr;
#define GET_H_SR() CPU (h_sr)
#define SET_H_SR(x) (CPU (h_sr) = (x))
  /* Floating point status and control register */
  SI h_fpscr;
#define GET_H_FPSCR() CPU (h_fpscr)
#define SET_H_FPSCR(x) (CPU (h_fpscr) = (x))
  /* Single precision floating point registers */
  SF h_fr[64];
#define GET_H_FR(a1) CPU (h_fr)[a1]
#define SET_H_FR(a1, x) (CPU (h_fr)[a1] = (x))
  /* Single/Double precision floating point registers */
  DF h_fsd[16];
#define GET_H_FSD(index) ((GET_H_PRBIT ()) ? (GET_H_DRC (index)) : (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), CPU (h_fr[index]))))
#define SET_H_FSD(index, x) \
do { \
if (GET_H_PRBIT ()) {\
SET_H_DRC ((index), (x));\
} else {\
SET_H_FRC ((index), CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), (x)));\
}\
;} while (0)
  /* floating point registers for fmov */
  DF h_fmov[16];
#define GET_H_FMOV(index) ((NOTBI (GET_H_SZBIT ())) ? (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), GET_H_FRC (index))) : (((((((index) & (1))) == (1))) ? (GET_H_XD (((index) & ((~ (1)))))) : (GET_H_DR (index)))))
#define SET_H_FMOV(index, x) \
do { \
if (NOTBI (GET_H_SZBIT ())) {\
SET_H_FRC ((index), CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), (x)));\
} else {\
if ((((((index)) & (1))) == (1))) {\
SET_H_XD ((((index)) & ((~ (1)))), (x));\
} else {\
SET_H_DR ((index), (x));\
}\
}\
;} while (0)
  /* Branch target registers */
  DI h_tr[8];
#define GET_H_TR(a1) CPU (h_tr)[a1]
#define SET_H_TR(a1, x) (CPU (h_tr)[a1] = (x))
  /* Current instruction set mode */
  BI h_ism;
#define GET_H_ISM() CPU (h_ism)
#define SET_H_ISM(x) \
do { \
cgen_rtx_error (current_cpu, "cannot set ism directly");\
;} while (0)
  } hardware;
#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
} SH64_CPU_DATA;

/* Virtual regs.  */

#define GET_H_GRC(index) ANDDI (CPU (h_gr[index]), ZEXTSIDI (0xffffffff))
#define SET_H_GRC(index, x) \
do { \
CPU (h_gr[(index)]) = EXTSIDI ((x));\
;} while (0)
#define GET_H_FRBIT() ANDSI (SRLSI (CPU (h_fpscr), 21), 1)
#define SET_H_FRBIT(x) \
do { \
CPU (h_fpscr) = ORSI (ANDSI (CPU (h_fpscr), (~ (((1) << (21))))), SLLSI ((x), 21));\
;} while (0)
#define GET_H_SZBIT() ANDSI (SRLSI (CPU (h_fpscr), 20), 1)
#define SET_H_SZBIT(x) \
do { \
CPU (h_fpscr) = ORSI (ANDSI (CPU (h_fpscr), (~ (((1) << (20))))), SLLSI ((x), 20));\
;} while (0)
#define GET_H_PRBIT() ANDSI (SRLSI (CPU (h_fpscr), 19), 1)
#define SET_H_PRBIT(x) \
do { \
CPU (h_fpscr) = ORSI (ANDSI (CPU (h_fpscr), (~ (((1) << (19))))), SLLSI ((x), 19));\
;} while (0)
#define GET_H_SBIT() ANDSI (SRLSI (CPU (h_sr), 1), 1)
#define SET_H_SBIT(x) \
do { \
CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (2))), SLLSI ((x), 1));\
;} while (0)
#define GET_H_MBIT() ANDSI (SRLSI (CPU (h_sr), 9), 1)
#define SET_H_MBIT(x) \
do { \
CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (9))))), SLLSI ((x), 9));\
;} while (0)
#define GET_H_QBIT() ANDSI (SRLSI (CPU (h_sr), 8), 1)
#define SET_H_QBIT(x) \
do { \
CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (8))))), SLLSI ((x), 8));\
;} while (0)
#define GET_H_FP(index) CPU (h_fr[index])
#define SET_H_FP(index, x) \
do { \
CPU (h_fr[(index)]) = (x);\
;} while (0)
#define GET_H_FV(index) CPU (h_fr[index])
#define SET_H_FV(index, x) \
do { \
CPU (h_fr[(index)]) = (x);\
;} while (0)
#define GET_H_FMTX(index) CPU (h_fr[index])
#define SET_H_FMTX(index, x) \
do { \
CPU (h_fr[(index)]) = (x);\
;} while (0)
#define GET_H_DR(index) SUBWORDDIDF (ORDI (SLLDI (ZEXTSIDI (SUBWORDSFSI (CPU (h_fr[index]))), 32), ZEXTSIDI (SUBWORDSFSI (CPU (h_fr[((index) + (1))])))))
#define SET_H_DR(index, x) \
do { \
{\
CPU (h_fr[(index)]) = SUBWORDSISF (SUBWORDDFSI ((x), 0));\
CPU (h_fr[(((index)) + (1))]) = SUBWORDSISF (SUBWORDDFSI ((x), 1));\
}\
;} while (0)
#define GET_H_ENDIAN() sh64_endian (current_cpu)
#define SET_H_ENDIAN(x) \
do { \
cgen_rtx_error (current_cpu, "cannot alter target byte order mid-program");\
;} while (0)
#define GET_H_FRC(index) CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + (index))])
#define SET_H_FRC(index, x) \
do { \
CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + ((index)))]) = (x);\
;} while (0)
#define GET_H_DRC(index) GET_H_DR (((((16) * (GET_H_FRBIT ()))) + (index)))
#define SET_H_DRC(index, x) \
do { \
SET_H_DR (((((16) * (GET_H_FRBIT ()))) + ((index))), (x));\
;} while (0)
#define GET_H_XF(index) CPU (h_fr[((((16) * (NOTBI (GET_H_FRBIT ())))) + (index))])
#define SET_H_XF(index, x) \
do { \
CPU (h_fr[((((16) * (NOTBI (GET_H_FRBIT ())))) + ((index)))]) = (x);\
;} while (0)
#define GET_H_XD(index) GET_H_DR (((((16) * (NOTBI (GET_H_FRBIT ())))) + (index)))
#define SET_H_XD(index, x) \
do { \
SET_H_DR (((((16) * (NOTBI (GET_H_FRBIT ())))) + ((index))), (x));\
;} while (0)
#define GET_H_FVC(index) CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + (index))])
#define SET_H_FVC(index, x) \
do { \
CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + ((index)))]) = (x);\
;} while (0)
#define GET_H_GBR() SUBWORDDISI (CPU (h_gr[((UINT) 16)]), 1)
#define SET_H_GBR(x) \
do { \
CPU (h_gr[((UINT) 16)]) = EXTSIDI ((x));\
;} while (0)
#define GET_H_VBR() SUBWORDDISI (CPU (h_gr[((UINT) 20)]), 1)
#define SET_H_VBR(x) \
do { \
CPU (h_gr[((UINT) 20)]) = EXTSIDI ((x));\
;} while (0)
#define GET_H_PR() SUBWORDDISI (CPU (h_gr[((UINT) 18)]), 1)
#define SET_H_PR(x) \
do { \
CPU (h_gr[((UINT) 18)]) = EXTSIDI ((x));\
;} while (0)
#define GET_H_MACL() SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 1)
#define SET_H_MACL(x) \
do { \
CPU (h_gr[((UINT) 17)]) = ORDI (SLLDI (ZEXTSIDI (SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 0)), 32), ZEXTSIDI ((x)));\
;} while (0)
#define GET_H_MACH() SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 0)
#define SET_H_MACH(x) \
do { \
CPU (h_gr[((UINT) 17)]) = ORDI (SLLDI (ZEXTSIDI ((x)), 32), ZEXTSIDI (SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 1)));\
;} while (0)
#define GET_H_TBIT() ANDBI (CPU (h_gr[((UINT) 19)]), 1)
#define SET_H_TBIT(x) \
do { \
CPU (h_gr[((UINT) 19)]) = ORDI (ANDDI (CPU (h_gr[((UINT) 19)]), INVDI (1)), ZEXTBIDI ((x)));\
;} while (0)

/* Cover fns for register access.  */
UDI sh64_h_pc_get (SIM_CPU *);
void sh64_h_pc_set (SIM_CPU *, UDI);
DI sh64_h_gr_get (SIM_CPU *, UINT);
void sh64_h_gr_set (SIM_CPU *, UINT, DI);
SI sh64_h_grc_get (SIM_CPU *, UINT);
void sh64_h_grc_set (SIM_CPU *, UINT, SI);
DI sh64_h_cr_get (SIM_CPU *, UINT);
void sh64_h_cr_set (SIM_CPU *, UINT, DI);
SI sh64_h_sr_get (SIM_CPU *);
void sh64_h_sr_set (SIM_CPU *, SI);
SI sh64_h_fpscr_get (SIM_CPU *);
void sh64_h_fpscr_set (SIM_CPU *, SI);
BI sh64_h_frbit_get (SIM_CPU *);
void sh64_h_frbit_set (SIM_CPU *, BI);
BI sh64_h_szbit_get (SIM_CPU *);
void sh64_h_szbit_set (SIM_CPU *, BI);
BI sh64_h_prbit_get (SIM_CPU *);
void sh64_h_prbit_set (SIM_CPU *, BI);
BI sh64_h_sbit_get (SIM_CPU *);
void sh64_h_sbit_set (SIM_CPU *, BI);
BI sh64_h_mbit_get (SIM_CPU *);
void sh64_h_mbit_set (SIM_CPU *, BI);
BI sh64_h_qbit_get (SIM_CPU *);
void sh64_h_qbit_set (SIM_CPU *, BI);
SF sh64_h_fr_get (SIM_CPU *, UINT);
void sh64_h_fr_set (SIM_CPU *, UINT, SF);
SF sh64_h_fp_get (SIM_CPU *, UINT);
void sh64_h_fp_set (SIM_CPU *, UINT, SF);
SF sh64_h_fv_get (SIM_CPU *, UINT);
void sh64_h_fv_set (SIM_CPU *, UINT, SF);
SF sh64_h_fmtx_get (SIM_CPU *, UINT);
void sh64_h_fmtx_set (SIM_CPU *, UINT, SF);
DF sh64_h_dr_get (SIM_CPU *, UINT);
void sh64_h_dr_set (SIM_CPU *, UINT, DF);
DF sh64_h_fsd_get (SIM_CPU *, UINT);
void sh64_h_fsd_set (SIM_CPU *, UINT, DF);
DF sh64_h_fmov_get (SIM_CPU *, UINT);
void sh64_h_fmov_set (SIM_CPU *, UINT, DF);
DI sh64_h_tr_get (SIM_CPU *, UINT);
void sh64_h_tr_set (SIM_CPU *, UINT, DI);
BI sh64_h_endian_get (SIM_CPU *);
void sh64_h_endian_set (SIM_CPU *, BI);
BI sh64_h_ism_get (SIM_CPU *);
void sh64_h_ism_set (SIM_CPU *, BI);
SF sh64_h_frc_get (SIM_CPU *, UINT);
void sh64_h_frc_set (SIM_CPU *, UINT, SF);
DF sh64_h_drc_get (SIM_CPU *, UINT);
void sh64_h_drc_set (SIM_CPU *, UINT, DF);
SF sh64_h_xf_get (SIM_CPU *, UINT);
void sh64_h_xf_set (SIM_CPU *, UINT, SF);
DF sh64_h_xd_get (SIM_CPU *, UINT);
void sh64_h_xd_set (SIM_CPU *, UINT, DF);
SF sh64_h_fvc_get (SIM_CPU *, UINT);
void sh64_h_fvc_set (SIM_CPU *, UINT, SF);
SI sh64_h_gbr_get (SIM_CPU *);
void sh64_h_gbr_set (SIM_CPU *, SI);
SI sh64_h_vbr_get (SIM_CPU *);
void sh64_h_vbr_set (SIM_CPU *, SI);
SI sh64_h_pr_get (SIM_CPU *);
void sh64_h_pr_set (SIM_CPU *, SI);
SI sh64_h_macl_get (SIM_CPU *);
void sh64_h_macl_set (SIM_CPU *, SI);
SI sh64_h_mach_get (SIM_CPU *);
void sh64_h_mach_set (SIM_CPU *, SI);
BI sh64_h_tbit_get (SIM_CPU *);
void sh64_h_tbit_set (SIM_CPU *, BI);

/* These must be hand-written.  */
extern CPUREG_FETCH_FN sh64_fetch_register;
extern CPUREG_STORE_FN sh64_store_register;

typedef struct {
  int empty;
} MODEL_SH4_DATA;

typedef struct {
  int empty;
} MODEL_SH5_DATA;

typedef struct {
  int empty;
} MODEL_SH5_MEDIA_DATA;

/* Collection of various things for the trace handler to use.  */

typedef struct trace_record {
  IADDR pc;
  /* FIXME:wip */
} TRACE_RECORD;

#endif /* CPU_SH64_H */
Commit	Line	Data
cbb38b47 BE	1	/* CPU family header for sh64.
	2
	3	THIS FILE IS MACHINE GENERATED WITH CGEN.
	4
fda1c30b	5	Copyright 1996-2009 Free Software Foundation, Inc.
cbb38b47	6
c7e628df	7	This file is part of the GNU simulators.
cbb38b47	8
fda1c30b DE	9	This file is free software; you can redistribute it and/or modify
	10	it under the terms of the GNU General Public License as published by
	11	the Free Software Foundation; either version 3, or (at your option)
	12	any later version.
cbb38b47	13
fda1c30b DE	14	It is distributed in the hope that it will be useful, but WITHOUT
	15	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	16	or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	17	License for more details.
cbb38b47	18
fda1c30b DE	19	You should have received a copy of the GNU General Public License along
	20	with this program; if not, write to the Free Software Foundation, Inc.,
	21	51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
cbb38b47 BE	22
	23	*/
	24
	25	#ifndef CPU_SH64_H
	26	#define CPU_SH64_H
	27
	28	/* Maximum number of instructions that are fetched at a time.
	29	This is for LIW type instructions sets (e.g. m32r). */
	30	#define MAX_LIW_INSNS 1
	31
	32	/* Maximum number of instructions that can be executed in parallel. */
	33	#define MAX_PARALLEL_INSNS 1
	34
	35	/* CPU state information. */
	36	typedef struct {
	37	/* Hardware elements. */
	38	struct {
	39	/* Program counter */
	40	UDI h_pc;
	41	#define GET_H_PC() CPU (h_pc)
	42	#define SET_H_PC(x) \
	43	do { \
	44	{\
	45	CPU (h_ism) = ANDDI ((x), 1);\
	46	CPU (h_pc) = ANDDI ((x), INVDI (1));\
	47	}\
	48	;} while (0)
	49	/* General purpose integer registers */
	50	DI h_gr[64];
fda1c30b	51	#define GET_H_GR(index) ((((index) == (63))) ? (MAKEDI (0, 0)) : (CPU (h_gr[index])))
cbb38b47 BE	52	#define SET_H_GR(index, x) \
	53	do { \
	54	if ((((index)) != (63))) {\
	55	CPU (h_gr[(index)]) = (x);\
	56	} else {\
	57	((void) 0); /nop/\
	58	}\
	59	;} while (0)
	60	/* Control registers */
	61	DI h_cr[64];
	62	#define GET_H_CR(index) ((((index) == (0))) ? (ZEXTSIDI (CPU (h_sr))) : (CPU (h_cr[index])))
	63	#define SET_H_CR(index, x) \
	64	do { \
	65	if ((((index)) == (0))) {\
	66	CPU (h_sr) = (x);\
	67	} else {\
	68	CPU (h_cr[(index)]) = (x);\
	69	}\
	70	;} while (0)
	71	/* Status register */
	72	SI h_sr;
	73	#define GET_H_SR() CPU (h_sr)
	74	#define SET_H_SR(x) (CPU (h_sr) = (x))
	75	/* Floating point status and control register */
	76	SI h_fpscr;
	77	#define GET_H_FPSCR() CPU (h_fpscr)
	78	#define SET_H_FPSCR(x) (CPU (h_fpscr) = (x))
	79	/* Single precision floating point registers */
	80	SF h_fr[64];
	81	#define GET_H_FR(a1) CPU (h_fr)[a1]
	82	#define SET_H_FR(a1, x) (CPU (h_fr)[a1] = (x))
c7e628df DB	83	/* Single/Double precision floating point registers */
	84	DF h_fsd[16];
	85	#define GET_H_FSD(index) ((GET_H_PRBIT ()) ? (GET_H_DRC (index)) : (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), CPU (h_fr[index]))))
	86	#define SET_H_FSD(index, x) \
	87	do { \
	88	if (GET_H_PRBIT ()) {\
	89	SET_H_DRC ((index), (x));\
	90	} else {\
	91	SET_H_FRC ((index), CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), (x)));\
	92	}\
	93	;} while (0)
	94	/* floating point registers for fmov */
	95	DF h_fmov[16];
	96	#define GET_H_FMOV(index) ((NOTBI (GET_H_SZBIT ())) ? (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), GET_H_FRC (index))) : (((((((index) & (1))) == (1))) ? (GET_H_XD (((index) & ((~ (1)))))) : (GET_H_DR (index)))))
	97	#define SET_H_FMOV(index, x) \
	98	do { \
	99	if (NOTBI (GET_H_SZBIT ())) {\
	100	SET_H_FRC ((index), CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), (x)));\
	101	} else {\
	102	if ((((((index)) & (1))) == (1))) {\
	103	SET_H_XD ((((index)) & ((~ (1)))), (x));\
	104	} else {\
	105	SET_H_DR ((index), (x));\
	106	}\
	107	}\
	108	;} while (0)
cbb38b47 BE	109	/* Branch target registers */
	110	DI h_tr[8];
	111	#define GET_H_TR(a1) CPU (h_tr)[a1]
	112	#define SET_H_TR(a1, x) (CPU (h_tr)[a1] = (x))
	113	/* Current instruction set mode */
	114	BI h_ism;
	115	#define GET_H_ISM() CPU (h_ism)
	116	#define SET_H_ISM(x) \
	117	do { \
	118	cgen_rtx_error (current_cpu, "cannot set ism directly");\
	119	;} while (0)
	120	} hardware;
	121	#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
	122	} SH64_CPU_DATA;
	123
	124	/* Virtual regs. */
	125
	126	#define GET_H_GRC(index) ANDDI (CPU (h_gr[index]), ZEXTSIDI (0xffffffff))
	127	#define SET_H_GRC(index, x) \
	128	do { \
	129	CPU (h_gr[(index)]) = EXTSIDI ((x));\
	130	;} while (0)
c7e628df	131	#define GET_H_FRBIT() ANDSI (SRLSI (CPU (h_fpscr), 21), 1)
cbb38b47 BE	132	#define SET_H_FRBIT(x) \
cbb38b47 BE	133	do { \
c7e628df	134	CPU (h_fpscr) = ORSI (ANDSI (CPU (h_fpscr), (~ (((1) << (21))))), SLLSI ((x), 21));\
cbb38b47	135	;} while (0)
c7e628df	136	#define GET_H_SZBIT() ANDSI (SRLSI (CPU (h_fpscr), 20), 1)
cbb38b47 BE	137	#define SET_H_SZBIT(x) \
cbb38b47 BE	138	do { \
c7e628df	139	CPU (h_fpscr) = ORSI (ANDSI (CPU (h_fpscr), (~ (((1) << (20))))), SLLSI ((x), 20));\
cbb38b47	140	;} while (0)
c7e628df	141	#define GET_H_PRBIT() ANDSI (SRLSI (CPU (h_fpscr), 19), 1)
cbb38b47 BE	142	#define SET_H_PRBIT(x) \
cbb38b47 BE	143	do { \
c7e628df	144	CPU (h_fpscr) = ORSI (ANDSI (CPU (h_fpscr), (~ (((1) << (19))))), SLLSI ((x), 19));\
cbb38b47 BE	145	;} while (0)
	146	#define GET_H_SBIT() ANDSI (SRLSI (CPU (h_sr), 1), 1)
	147	#define SET_H_SBIT(x) \
	148	do { \
	149	CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (2))), SLLSI ((x), 1));\
	150	;} while (0)
	151	#define GET_H_MBIT() ANDSI (SRLSI (CPU (h_sr), 9), 1)
	152	#define SET_H_MBIT(x) \
	153	do { \
	154	CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (9))))), SLLSI ((x), 9));\
	155	;} while (0)
	156	#define GET_H_QBIT() ANDSI (SRLSI (CPU (h_sr), 8), 1)
	157	#define SET_H_QBIT(x) \
	158	do { \
	159	CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (8))))), SLLSI ((x), 8));\
	160	;} while (0)
c7e628df DB	161	#define GET_H_FP(index) CPU (h_fr[index])
	162	#define SET_H_FP(index, x) \
	163	do { \
	164	CPU (h_fr[(index)]) = (x);\
	165	;} while (0)
	166	#define GET_H_FV(index) CPU (h_fr[index])
cbb38b47 BE	167	#define SET_H_FV(index, x) \
cbb38b47 BE	168	do { \
c7e628df	169	CPU (h_fr[(index)]) = (x);\
cbb38b47	170	;} while (0)
c7e628df	171	#define GET_H_FMTX(index) CPU (h_fr[index])
cbb38b47 BE	172	#define SET_H_FMTX(index, x) \
cbb38b47 BE	173	do { \
c7e628df	174	CPU (h_fr[(index)]) = (x);\
cbb38b47 BE	175	;} while (0)
	176	#define GET_H_DR(index) SUBWORDDIDF (ORDI (SLLDI (ZEXTSIDI (SUBWORDSFSI (CPU (h_fr[index]))), 32), ZEXTSIDI (SUBWORDSFSI (CPU (h_fr[((index) + (1))])))))
	177	#define SET_H_DR(index, x) \
	178	do { \
	179	{\
	180	CPU (h_fr[(index)]) = SUBWORDSISF (SUBWORDDFSI ((x), 0));\
	181	CPU (h_fr[(((index)) + (1))]) = SUBWORDSISF (SUBWORDDFSI ((x), 1));\
	182	}\
	183	;} while (0)
	184	#define GET_H_ENDIAN() sh64_endian (current_cpu)
	185	#define SET_H_ENDIAN(x) \
	186	do { \
	187	cgen_rtx_error (current_cpu, "cannot alter target byte order mid-program");\
	188	;} while (0)
	189	#define GET_H_FRC(index) CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + (index))])
	190	#define SET_H_FRC(index, x) \
	191	do { \
	192	CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + ((index)))]) = (x);\
	193	;} while (0)
	194	#define GET_H_DRC(index) GET_H_DR (((((16) * (GET_H_FRBIT ()))) + (index)))
	195	#define SET_H_DRC(index, x) \
	196	do { \
	197	SET_H_DR (((((16) * (GET_H_FRBIT ()))) + ((index))), (x));\
	198	;} while (0)
	199	#define GET_H_XF(index) CPU (h_fr[((((16) * (NOTBI (GET_H_FRBIT ())))) + (index))])
	200	#define SET_H_XF(index, x) \
	201	do { \
	202	CPU (h_fr[((((16) * (NOTBI (GET_H_FRBIT ())))) + ((index)))]) = (x);\
	203	;} while (0)
	204	#define GET_H_XD(index) GET_H_DR (((((16) * (NOTBI (GET_H_FRBIT ())))) + (index)))
	205	#define SET_H_XD(index, x) \
	206	do { \
	207	SET_H_DR (((((16) * (NOTBI (GET_H_FRBIT ())))) + ((index))), (x));\
	208	;} while (0)
	209	#define GET_H_FVC(index) CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + (index))])
	210	#define SET_H_FVC(index, x) \
	211	do { \
	212	CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + ((index)))]) = (x);\
	213	;} while (0)
cbb38b47 BE	214	#define GET_H_GBR() SUBWORDDISI (CPU (h_gr[((UINT) 16)]), 1)
	215	#define SET_H_GBR(x) \
	216	do { \
	217	CPU (h_gr[((UINT) 16)]) = EXTSIDI ((x));\
	218	;} while (0)
c7e628df DB	219	#define GET_H_VBR() SUBWORDDISI (CPU (h_gr[((UINT) 20)]), 1)
	220	#define SET_H_VBR(x) \
	221	do { \
	222	CPU (h_gr[((UINT) 20)]) = EXTSIDI ((x));\
	223	;} while (0)
cbb38b47 BE	224	#define GET_H_PR() SUBWORDDISI (CPU (h_gr[((UINT) 18)]), 1)
	225	#define SET_H_PR(x) \
	226	do { \
	227	CPU (h_gr[((UINT) 18)]) = EXTSIDI ((x));\
	228	;} while (0)
	229	#define GET_H_MACL() SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 1)
	230	#define SET_H_MACL(x) \
	231	do { \
	232	CPU (h_gr[((UINT) 17)]) = ORDI (SLLDI (ZEXTSIDI (SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 0)), 32), ZEXTSIDI ((x)));\
	233	;} while (0)
	234	#define GET_H_MACH() SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 0)
	235	#define SET_H_MACH(x) \
	236	do { \
	237	CPU (h_gr[((UINT) 17)]) = ORDI (SLLDI (ZEXTSIDI ((x)), 32), ZEXTSIDI (SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 1)));\
	238	;} while (0)
	239	#define GET_H_TBIT() ANDBI (CPU (h_gr[((UINT) 19)]), 1)
	240	#define SET_H_TBIT(x) \
	241	do { \
	242	CPU (h_gr[((UINT) 19)]) = ORDI (ANDDI (CPU (h_gr[((UINT) 19)]), INVDI (1)), ZEXTBIDI ((x)));\
	243	;} while (0)
	244
	245	/* Cover fns for register access. */
	246	UDI sh64_h_pc_get (SIM_CPU *);
	247	void sh64_h_pc_set (SIM_CPU *, UDI);
	248	DI sh64_h_gr_get (SIM_CPU *, UINT);
	249	void sh64_h_gr_set (SIM_CPU *, UINT, DI);
	250	SI sh64_h_grc_get (SIM_CPU *, UINT);
	251	void sh64_h_grc_set (SIM_CPU *, UINT, SI);
	252	DI sh64_h_cr_get (SIM_CPU *, UINT);
	253	void sh64_h_cr_set (SIM_CPU *, UINT, DI);
	254	SI sh64_h_sr_get (SIM_CPU *);
	255	void sh64_h_sr_set (SIM_CPU *, SI);
	256	SI sh64_h_fpscr_get (SIM_CPU *);
	257	void sh64_h_fpscr_set (SIM_CPU *, SI);
	258	BI sh64_h_frbit_get (SIM_CPU *);
	259	void sh64_h_frbit_set (SIM_CPU *, BI);
	260	BI sh64_h_szbit_get (SIM_CPU *);
	261	void sh64_h_szbit_set (SIM_CPU *, BI);
	262	BI sh64_h_prbit_get (SIM_CPU *);
	263	void sh64_h_prbit_set (SIM_CPU *, BI);
	264	BI sh64_h_sbit_get (SIM_CPU *);
	265	void sh64_h_sbit_set (SIM_CPU *, BI);
	266	BI sh64_h_mbit_get (SIM_CPU *);
	267	void sh64_h_mbit_set (SIM_CPU *, BI);
	268	BI sh64_h_qbit_get (SIM_CPU *);
	269	void sh64_h_qbit_set (SIM_CPU *, BI);
	270	SF sh64_h_fr_get (SIM_CPU *, UINT);
	271	void sh64_h_fr_set (SIM_CPU *, UINT, SF);
c7e628df DB	272	SF sh64_h_fp_get (SIM_CPU *, UINT);
c7e628df DB	273	void sh64_h_fp_set (SIM_CPU *, UINT, SF);
cbb38b47 BE	274	SF sh64_h_fv_get (SIM_CPU *, UINT);
	275	void sh64_h_fv_set (SIM_CPU *, UINT, SF);
	276	SF sh64_h_fmtx_get (SIM_CPU *, UINT);
	277	void sh64_h_fmtx_set (SIM_CPU *, UINT, SF);
	278	DF sh64_h_dr_get (SIM_CPU *, UINT);
	279	void sh64_h_dr_set (SIM_CPU *, UINT, DF);
c7e628df DB	280	DF sh64_h_fsd_get (SIM_CPU *, UINT);
	281	void sh64_h_fsd_set (SIM_CPU *, UINT, DF);
	282	DF sh64_h_fmov_get (SIM_CPU *, UINT);
	283	void sh64_h_fmov_set (SIM_CPU *, UINT, DF);
cbb38b47 BE	284	DI sh64_h_tr_get (SIM_CPU *, UINT);
	285	void sh64_h_tr_set (SIM_CPU *, UINT, DI);
	286	BI sh64_h_endian_get (SIM_CPU *);
	287	void sh64_h_endian_set (SIM_CPU *, BI);
	288	BI sh64_h_ism_get (SIM_CPU *);
	289	void sh64_h_ism_set (SIM_CPU *, BI);
	290	SF sh64_h_frc_get (SIM_CPU *, UINT);
	291	void sh64_h_frc_set (SIM_CPU *, UINT, SF);
	292	DF sh64_h_drc_get (SIM_CPU *, UINT);
	293	void sh64_h_drc_set (SIM_CPU *, UINT, DF);
	294	SF sh64_h_xf_get (SIM_CPU *, UINT);
	295	void sh64_h_xf_set (SIM_CPU *, UINT, SF);
	296	DF sh64_h_xd_get (SIM_CPU *, UINT);
	297	void sh64_h_xd_set (SIM_CPU *, UINT, DF);
	298	SF sh64_h_fvc_get (SIM_CPU *, UINT);
	299	void sh64_h_fvc_set (SIM_CPU *, UINT, SF);
cbb38b47 BE	300	SI sh64_h_gbr_get (SIM_CPU *);
cbb38b47 BE	301	void sh64_h_gbr_set (SIM_CPU *, SI);
c7e628df DB	302	SI sh64_h_vbr_get (SIM_CPU *);
c7e628df DB	303	void sh64_h_vbr_set (SIM_CPU *, SI);
cbb38b47 BE	304	SI sh64_h_pr_get (SIM_CPU *);
	305	void sh64_h_pr_set (SIM_CPU *, SI);
	306	SI sh64_h_macl_get (SIM_CPU *);
	307	void sh64_h_macl_set (SIM_CPU *, SI);
	308	SI sh64_h_mach_get (SIM_CPU *);
	309	void sh64_h_mach_set (SIM_CPU *, SI);
	310	BI sh64_h_tbit_get (SIM_CPU *);
	311	void sh64_h_tbit_set (SIM_CPU *, BI);
	312
	313	/* These must be hand-written. */
	314	extern CPUREG_FETCH_FN sh64_fetch_register;
	315	extern CPUREG_STORE_FN sh64_store_register;
	316
c7e628df DB	317	typedef struct {
	318	int empty;
	319	} MODEL_SH4_DATA;
	320
cbb38b47 BE	321	typedef struct {
	322	int empty;
	323	} MODEL_SH5_DATA;
	324
c7e628df DB	325	typedef struct {
	326	int empty;
	327	} MODEL_SH5_MEDIA_DATA;
	328
cbb38b47 BE	329	/* Collection of various things for the trace handler to use. */
	330
	331	typedef struct trace_record {
	332	IADDR pc;
	333	/* FIXME:wip */
	334	} TRACE_RECORD;
	335
	336	#endif /* CPU_SH64_H */