Commit | Line | Data |
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cbb38b47 BE |
1 | /* Simulator instruction semantics for sh64. |
2 | ||
3 | THIS FILE IS MACHINE GENERATED WITH CGEN. | |
4 | ||
5 | Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. | |
6 | ||
7 | This file is part of the GNU Simulators. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2, or (at your option) | |
12 | any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License along | |
20 | with this program; if not, write to the Free Software Foundation, Inc., | |
21 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
22 | ||
23 | */ | |
24 | ||
25 | #ifdef DEFINE_LABELS | |
26 | ||
27 | /* The labels have the case they have because the enum of insn types | |
28 | is all uppercase and in the non-stdc case the insn symbol is built | |
29 | into the enum name. */ | |
30 | ||
31 | static struct { | |
32 | int index; | |
33 | void *label; | |
34 | } labels[] = { | |
35 | { SH64_COMPACT_INSN_X_INVALID, && case_sem_INSN_X_INVALID }, | |
36 | { SH64_COMPACT_INSN_X_AFTER, && case_sem_INSN_X_AFTER }, | |
37 | { SH64_COMPACT_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE }, | |
38 | { SH64_COMPACT_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN }, | |
39 | { SH64_COMPACT_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN }, | |
40 | { SH64_COMPACT_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN }, | |
41 | { SH64_COMPACT_INSN_ADD_COMPACT, && case_sem_INSN_ADD_COMPACT }, | |
42 | { SH64_COMPACT_INSN_ADDI_COMPACT, && case_sem_INSN_ADDI_COMPACT }, | |
43 | { SH64_COMPACT_INSN_ADDC_COMPACT, && case_sem_INSN_ADDC_COMPACT }, | |
44 | { SH64_COMPACT_INSN_ADDV_COMPACT, && case_sem_INSN_ADDV_COMPACT }, | |
45 | { SH64_COMPACT_INSN_AND_COMPACT, && case_sem_INSN_AND_COMPACT }, | |
46 | { SH64_COMPACT_INSN_ANDI_COMPACT, && case_sem_INSN_ANDI_COMPACT }, | |
47 | { SH64_COMPACT_INSN_ANDB_COMPACT, && case_sem_INSN_ANDB_COMPACT }, | |
48 | { SH64_COMPACT_INSN_BF_COMPACT, && case_sem_INSN_BF_COMPACT }, | |
49 | { SH64_COMPACT_INSN_BFS_COMPACT, && case_sem_INSN_BFS_COMPACT }, | |
50 | { SH64_COMPACT_INSN_BRA_COMPACT, && case_sem_INSN_BRA_COMPACT }, | |
51 | { SH64_COMPACT_INSN_BRAF_COMPACT, && case_sem_INSN_BRAF_COMPACT }, | |
52 | { SH64_COMPACT_INSN_BRK_COMPACT, && case_sem_INSN_BRK_COMPACT }, | |
53 | { SH64_COMPACT_INSN_BSR_COMPACT, && case_sem_INSN_BSR_COMPACT }, | |
54 | { SH64_COMPACT_INSN_BSRF_COMPACT, && case_sem_INSN_BSRF_COMPACT }, | |
55 | { SH64_COMPACT_INSN_BT_COMPACT, && case_sem_INSN_BT_COMPACT }, | |
56 | { SH64_COMPACT_INSN_BTS_COMPACT, && case_sem_INSN_BTS_COMPACT }, | |
57 | { SH64_COMPACT_INSN_CLRMAC_COMPACT, && case_sem_INSN_CLRMAC_COMPACT }, | |
58 | { SH64_COMPACT_INSN_CLRS_COMPACT, && case_sem_INSN_CLRS_COMPACT }, | |
59 | { SH64_COMPACT_INSN_CLRT_COMPACT, && case_sem_INSN_CLRT_COMPACT }, | |
60 | { SH64_COMPACT_INSN_CMPEQ_COMPACT, && case_sem_INSN_CMPEQ_COMPACT }, | |
61 | { SH64_COMPACT_INSN_CMPEQI_COMPACT, && case_sem_INSN_CMPEQI_COMPACT }, | |
62 | { SH64_COMPACT_INSN_CMPGE_COMPACT, && case_sem_INSN_CMPGE_COMPACT }, | |
63 | { SH64_COMPACT_INSN_CMPGT_COMPACT, && case_sem_INSN_CMPGT_COMPACT }, | |
64 | { SH64_COMPACT_INSN_CMPHI_COMPACT, && case_sem_INSN_CMPHI_COMPACT }, | |
65 | { SH64_COMPACT_INSN_CMPHS_COMPACT, && case_sem_INSN_CMPHS_COMPACT }, | |
66 | { SH64_COMPACT_INSN_CMPPL_COMPACT, && case_sem_INSN_CMPPL_COMPACT }, | |
67 | { SH64_COMPACT_INSN_CMPPZ_COMPACT, && case_sem_INSN_CMPPZ_COMPACT }, | |
68 | { SH64_COMPACT_INSN_CMPSTR_COMPACT, && case_sem_INSN_CMPSTR_COMPACT }, | |
69 | { SH64_COMPACT_INSN_DIV0S_COMPACT, && case_sem_INSN_DIV0S_COMPACT }, | |
70 | { SH64_COMPACT_INSN_DIV0U_COMPACT, && case_sem_INSN_DIV0U_COMPACT }, | |
71 | { SH64_COMPACT_INSN_DIV1_COMPACT, && case_sem_INSN_DIV1_COMPACT }, | |
72 | { SH64_COMPACT_INSN_DMULSL_COMPACT, && case_sem_INSN_DMULSL_COMPACT }, | |
73 | { SH64_COMPACT_INSN_DMULUL_COMPACT, && case_sem_INSN_DMULUL_COMPACT }, | |
74 | { SH64_COMPACT_INSN_DT_COMPACT, && case_sem_INSN_DT_COMPACT }, | |
75 | { SH64_COMPACT_INSN_EXTSB_COMPACT, && case_sem_INSN_EXTSB_COMPACT }, | |
76 | { SH64_COMPACT_INSN_EXTSW_COMPACT, && case_sem_INSN_EXTSW_COMPACT }, | |
77 | { SH64_COMPACT_INSN_EXTUB_COMPACT, && case_sem_INSN_EXTUB_COMPACT }, | |
78 | { SH64_COMPACT_INSN_EXTUW_COMPACT, && case_sem_INSN_EXTUW_COMPACT }, | |
79 | { SH64_COMPACT_INSN_FABS_COMPACT, && case_sem_INSN_FABS_COMPACT }, | |
80 | { SH64_COMPACT_INSN_FADD_COMPACT, && case_sem_INSN_FADD_COMPACT }, | |
81 | { SH64_COMPACT_INSN_FCMPEQ_COMPACT, && case_sem_INSN_FCMPEQ_COMPACT }, | |
82 | { SH64_COMPACT_INSN_FCMPGT_COMPACT, && case_sem_INSN_FCMPGT_COMPACT }, | |
83 | { SH64_COMPACT_INSN_FCNVDS_COMPACT, && case_sem_INSN_FCNVDS_COMPACT }, | |
84 | { SH64_COMPACT_INSN_FCNVSD_COMPACT, && case_sem_INSN_FCNVSD_COMPACT }, | |
85 | { SH64_COMPACT_INSN_FDIV_COMPACT, && case_sem_INSN_FDIV_COMPACT }, | |
86 | { SH64_COMPACT_INSN_FIPR_COMPACT, && case_sem_INSN_FIPR_COMPACT }, | |
87 | { SH64_COMPACT_INSN_FLDS_COMPACT, && case_sem_INSN_FLDS_COMPACT }, | |
88 | { SH64_COMPACT_INSN_FLDI0_COMPACT, && case_sem_INSN_FLDI0_COMPACT }, | |
89 | { SH64_COMPACT_INSN_FLDI1_COMPACT, && case_sem_INSN_FLDI1_COMPACT }, | |
90 | { SH64_COMPACT_INSN_FLOAT_COMPACT, && case_sem_INSN_FLOAT_COMPACT }, | |
91 | { SH64_COMPACT_INSN_FMAC_COMPACT, && case_sem_INSN_FMAC_COMPACT }, | |
92 | { SH64_COMPACT_INSN_FMOV1_COMPACT, && case_sem_INSN_FMOV1_COMPACT }, | |
93 | { SH64_COMPACT_INSN_FMOV2_COMPACT, && case_sem_INSN_FMOV2_COMPACT }, | |
94 | { SH64_COMPACT_INSN_FMOV3_COMPACT, && case_sem_INSN_FMOV3_COMPACT }, | |
95 | { SH64_COMPACT_INSN_FMOV4_COMPACT, && case_sem_INSN_FMOV4_COMPACT }, | |
96 | { SH64_COMPACT_INSN_FMOV5_COMPACT, && case_sem_INSN_FMOV5_COMPACT }, | |
97 | { SH64_COMPACT_INSN_FMOV6_COMPACT, && case_sem_INSN_FMOV6_COMPACT }, | |
98 | { SH64_COMPACT_INSN_FMOV7_COMPACT, && case_sem_INSN_FMOV7_COMPACT }, | |
99 | { SH64_COMPACT_INSN_FMUL_COMPACT, && case_sem_INSN_FMUL_COMPACT }, | |
100 | { SH64_COMPACT_INSN_FNEG_COMPACT, && case_sem_INSN_FNEG_COMPACT }, | |
101 | { SH64_COMPACT_INSN_FRCHG_COMPACT, && case_sem_INSN_FRCHG_COMPACT }, | |
102 | { SH64_COMPACT_INSN_FSCHG_COMPACT, && case_sem_INSN_FSCHG_COMPACT }, | |
103 | { SH64_COMPACT_INSN_FSQRT_COMPACT, && case_sem_INSN_FSQRT_COMPACT }, | |
104 | { SH64_COMPACT_INSN_FSTS_COMPACT, && case_sem_INSN_FSTS_COMPACT }, | |
105 | { SH64_COMPACT_INSN_FSUB_COMPACT, && case_sem_INSN_FSUB_COMPACT }, | |
106 | { SH64_COMPACT_INSN_FTRC_COMPACT, && case_sem_INSN_FTRC_COMPACT }, | |
107 | { SH64_COMPACT_INSN_FTRV_COMPACT, && case_sem_INSN_FTRV_COMPACT }, | |
108 | { SH64_COMPACT_INSN_JMP_COMPACT, && case_sem_INSN_JMP_COMPACT }, | |
109 | { SH64_COMPACT_INSN_JSR_COMPACT, && case_sem_INSN_JSR_COMPACT }, | |
110 | { SH64_COMPACT_INSN_LDC_COMPACT, && case_sem_INSN_LDC_COMPACT }, | |
111 | { SH64_COMPACT_INSN_LDCL_COMPACT, && case_sem_INSN_LDCL_COMPACT }, | |
112 | { SH64_COMPACT_INSN_LDS_FPSCR_COMPACT, && case_sem_INSN_LDS_FPSCR_COMPACT }, | |
113 | { SH64_COMPACT_INSN_LDSL_FPSCR_COMPACT, && case_sem_INSN_LDSL_FPSCR_COMPACT }, | |
114 | { SH64_COMPACT_INSN_LDS_FPUL_COMPACT, && case_sem_INSN_LDS_FPUL_COMPACT }, | |
115 | { SH64_COMPACT_INSN_LDSL_FPUL_COMPACT, && case_sem_INSN_LDSL_FPUL_COMPACT }, | |
116 | { SH64_COMPACT_INSN_LDS_MACH_COMPACT, && case_sem_INSN_LDS_MACH_COMPACT }, | |
117 | { SH64_COMPACT_INSN_LDSL_MACH_COMPACT, && case_sem_INSN_LDSL_MACH_COMPACT }, | |
118 | { SH64_COMPACT_INSN_LDS_MACL_COMPACT, && case_sem_INSN_LDS_MACL_COMPACT }, | |
119 | { SH64_COMPACT_INSN_LDSL_MACL_COMPACT, && case_sem_INSN_LDSL_MACL_COMPACT }, | |
120 | { SH64_COMPACT_INSN_LDS_PR_COMPACT, && case_sem_INSN_LDS_PR_COMPACT }, | |
121 | { SH64_COMPACT_INSN_LDSL_PR_COMPACT, && case_sem_INSN_LDSL_PR_COMPACT }, | |
122 | { SH64_COMPACT_INSN_MACL_COMPACT, && case_sem_INSN_MACL_COMPACT }, | |
123 | { SH64_COMPACT_INSN_MACW_COMPACT, && case_sem_INSN_MACW_COMPACT }, | |
124 | { SH64_COMPACT_INSN_MOV_COMPACT, && case_sem_INSN_MOV_COMPACT }, | |
125 | { SH64_COMPACT_INSN_MOVI_COMPACT, && case_sem_INSN_MOVI_COMPACT }, | |
126 | { SH64_COMPACT_INSN_MOVB1_COMPACT, && case_sem_INSN_MOVB1_COMPACT }, | |
127 | { SH64_COMPACT_INSN_MOVB2_COMPACT, && case_sem_INSN_MOVB2_COMPACT }, | |
128 | { SH64_COMPACT_INSN_MOVB3_COMPACT, && case_sem_INSN_MOVB3_COMPACT }, | |
129 | { SH64_COMPACT_INSN_MOVB4_COMPACT, && case_sem_INSN_MOVB4_COMPACT }, | |
130 | { SH64_COMPACT_INSN_MOVB5_COMPACT, && case_sem_INSN_MOVB5_COMPACT }, | |
131 | { SH64_COMPACT_INSN_MOVB6_COMPACT, && case_sem_INSN_MOVB6_COMPACT }, | |
132 | { SH64_COMPACT_INSN_MOVB7_COMPACT, && case_sem_INSN_MOVB7_COMPACT }, | |
133 | { SH64_COMPACT_INSN_MOVB8_COMPACT, && case_sem_INSN_MOVB8_COMPACT }, | |
134 | { SH64_COMPACT_INSN_MOVB9_COMPACT, && case_sem_INSN_MOVB9_COMPACT }, | |
135 | { SH64_COMPACT_INSN_MOVB10_COMPACT, && case_sem_INSN_MOVB10_COMPACT }, | |
136 | { SH64_COMPACT_INSN_MOVL1_COMPACT, && case_sem_INSN_MOVL1_COMPACT }, | |
137 | { SH64_COMPACT_INSN_MOVL2_COMPACT, && case_sem_INSN_MOVL2_COMPACT }, | |
138 | { SH64_COMPACT_INSN_MOVL3_COMPACT, && case_sem_INSN_MOVL3_COMPACT }, | |
139 | { SH64_COMPACT_INSN_MOVL4_COMPACT, && case_sem_INSN_MOVL4_COMPACT }, | |
140 | { SH64_COMPACT_INSN_MOVL5_COMPACT, && case_sem_INSN_MOVL5_COMPACT }, | |
141 | { SH64_COMPACT_INSN_MOVL6_COMPACT, && case_sem_INSN_MOVL6_COMPACT }, | |
142 | { SH64_COMPACT_INSN_MOVL7_COMPACT, && case_sem_INSN_MOVL7_COMPACT }, | |
143 | { SH64_COMPACT_INSN_MOVL8_COMPACT, && case_sem_INSN_MOVL8_COMPACT }, | |
144 | { SH64_COMPACT_INSN_MOVL9_COMPACT, && case_sem_INSN_MOVL9_COMPACT }, | |
145 | { SH64_COMPACT_INSN_MOVL10_COMPACT, && case_sem_INSN_MOVL10_COMPACT }, | |
146 | { SH64_COMPACT_INSN_MOVL11_COMPACT, && case_sem_INSN_MOVL11_COMPACT }, | |
147 | { SH64_COMPACT_INSN_MOVW1_COMPACT, && case_sem_INSN_MOVW1_COMPACT }, | |
148 | { SH64_COMPACT_INSN_MOVW2_COMPACT, && case_sem_INSN_MOVW2_COMPACT }, | |
149 | { SH64_COMPACT_INSN_MOVW3_COMPACT, && case_sem_INSN_MOVW3_COMPACT }, | |
150 | { SH64_COMPACT_INSN_MOVW4_COMPACT, && case_sem_INSN_MOVW4_COMPACT }, | |
151 | { SH64_COMPACT_INSN_MOVW5_COMPACT, && case_sem_INSN_MOVW5_COMPACT }, | |
152 | { SH64_COMPACT_INSN_MOVW6_COMPACT, && case_sem_INSN_MOVW6_COMPACT }, | |
153 | { SH64_COMPACT_INSN_MOVW7_COMPACT, && case_sem_INSN_MOVW7_COMPACT }, | |
154 | { SH64_COMPACT_INSN_MOVW8_COMPACT, && case_sem_INSN_MOVW8_COMPACT }, | |
155 | { SH64_COMPACT_INSN_MOVW9_COMPACT, && case_sem_INSN_MOVW9_COMPACT }, | |
156 | { SH64_COMPACT_INSN_MOVW10_COMPACT, && case_sem_INSN_MOVW10_COMPACT }, | |
157 | { SH64_COMPACT_INSN_MOVW11_COMPACT, && case_sem_INSN_MOVW11_COMPACT }, | |
158 | { SH64_COMPACT_INSN_MOVA_COMPACT, && case_sem_INSN_MOVA_COMPACT }, | |
159 | { SH64_COMPACT_INSN_MOVCAL_COMPACT, && case_sem_INSN_MOVCAL_COMPACT }, | |
160 | { SH64_COMPACT_INSN_MOVT_COMPACT, && case_sem_INSN_MOVT_COMPACT }, | |
161 | { SH64_COMPACT_INSN_MULL_COMPACT, && case_sem_INSN_MULL_COMPACT }, | |
162 | { SH64_COMPACT_INSN_MULSW_COMPACT, && case_sem_INSN_MULSW_COMPACT }, | |
163 | { SH64_COMPACT_INSN_MULUW_COMPACT, && case_sem_INSN_MULUW_COMPACT }, | |
164 | { SH64_COMPACT_INSN_NEG_COMPACT, && case_sem_INSN_NEG_COMPACT }, | |
165 | { SH64_COMPACT_INSN_NEGC_COMPACT, && case_sem_INSN_NEGC_COMPACT }, | |
166 | { SH64_COMPACT_INSN_NOP_COMPACT, && case_sem_INSN_NOP_COMPACT }, | |
167 | { SH64_COMPACT_INSN_NOT_COMPACT, && case_sem_INSN_NOT_COMPACT }, | |
168 | { SH64_COMPACT_INSN_OCBI_COMPACT, && case_sem_INSN_OCBI_COMPACT }, | |
169 | { SH64_COMPACT_INSN_OCBP_COMPACT, && case_sem_INSN_OCBP_COMPACT }, | |
170 | { SH64_COMPACT_INSN_OCBWB_COMPACT, && case_sem_INSN_OCBWB_COMPACT }, | |
171 | { SH64_COMPACT_INSN_OR_COMPACT, && case_sem_INSN_OR_COMPACT }, | |
172 | { SH64_COMPACT_INSN_ORI_COMPACT, && case_sem_INSN_ORI_COMPACT }, | |
173 | { SH64_COMPACT_INSN_ORB_COMPACT, && case_sem_INSN_ORB_COMPACT }, | |
174 | { SH64_COMPACT_INSN_PREF_COMPACT, && case_sem_INSN_PREF_COMPACT }, | |
175 | { SH64_COMPACT_INSN_ROTCL_COMPACT, && case_sem_INSN_ROTCL_COMPACT }, | |
176 | { SH64_COMPACT_INSN_ROTCR_COMPACT, && case_sem_INSN_ROTCR_COMPACT }, | |
177 | { SH64_COMPACT_INSN_ROTL_COMPACT, && case_sem_INSN_ROTL_COMPACT }, | |
178 | { SH64_COMPACT_INSN_ROTR_COMPACT, && case_sem_INSN_ROTR_COMPACT }, | |
179 | { SH64_COMPACT_INSN_RTS_COMPACT, && case_sem_INSN_RTS_COMPACT }, | |
180 | { SH64_COMPACT_INSN_SETS_COMPACT, && case_sem_INSN_SETS_COMPACT }, | |
181 | { SH64_COMPACT_INSN_SETT_COMPACT, && case_sem_INSN_SETT_COMPACT }, | |
182 | { SH64_COMPACT_INSN_SHAD_COMPACT, && case_sem_INSN_SHAD_COMPACT }, | |
183 | { SH64_COMPACT_INSN_SHAL_COMPACT, && case_sem_INSN_SHAL_COMPACT }, | |
184 | { SH64_COMPACT_INSN_SHAR_COMPACT, && case_sem_INSN_SHAR_COMPACT }, | |
185 | { SH64_COMPACT_INSN_SHLD_COMPACT, && case_sem_INSN_SHLD_COMPACT }, | |
186 | { SH64_COMPACT_INSN_SHLL_COMPACT, && case_sem_INSN_SHLL_COMPACT }, | |
187 | { SH64_COMPACT_INSN_SHLL2_COMPACT, && case_sem_INSN_SHLL2_COMPACT }, | |
188 | { SH64_COMPACT_INSN_SHLL8_COMPACT, && case_sem_INSN_SHLL8_COMPACT }, | |
189 | { SH64_COMPACT_INSN_SHLL16_COMPACT, && case_sem_INSN_SHLL16_COMPACT }, | |
190 | { SH64_COMPACT_INSN_SHLR_COMPACT, && case_sem_INSN_SHLR_COMPACT }, | |
191 | { SH64_COMPACT_INSN_SHLR2_COMPACT, && case_sem_INSN_SHLR2_COMPACT }, | |
192 | { SH64_COMPACT_INSN_SHLR8_COMPACT, && case_sem_INSN_SHLR8_COMPACT }, | |
193 | { SH64_COMPACT_INSN_SHLR16_COMPACT, && case_sem_INSN_SHLR16_COMPACT }, | |
194 | { SH64_COMPACT_INSN_STC_GBR_COMPACT, && case_sem_INSN_STC_GBR_COMPACT }, | |
195 | { SH64_COMPACT_INSN_STCL_GBR_COMPACT, && case_sem_INSN_STCL_GBR_COMPACT }, | |
196 | { SH64_COMPACT_INSN_STS_FPSCR_COMPACT, && case_sem_INSN_STS_FPSCR_COMPACT }, | |
197 | { SH64_COMPACT_INSN_STSL_FPSCR_COMPACT, && case_sem_INSN_STSL_FPSCR_COMPACT }, | |
198 | { SH64_COMPACT_INSN_STS_FPUL_COMPACT, && case_sem_INSN_STS_FPUL_COMPACT }, | |
199 | { SH64_COMPACT_INSN_STSL_FPUL_COMPACT, && case_sem_INSN_STSL_FPUL_COMPACT }, | |
200 | { SH64_COMPACT_INSN_STS_MACH_COMPACT, && case_sem_INSN_STS_MACH_COMPACT }, | |
201 | { SH64_COMPACT_INSN_STSL_MACH_COMPACT, && case_sem_INSN_STSL_MACH_COMPACT }, | |
202 | { SH64_COMPACT_INSN_STS_MACL_COMPACT, && case_sem_INSN_STS_MACL_COMPACT }, | |
203 | { SH64_COMPACT_INSN_STSL_MACL_COMPACT, && case_sem_INSN_STSL_MACL_COMPACT }, | |
204 | { SH64_COMPACT_INSN_STS_PR_COMPACT, && case_sem_INSN_STS_PR_COMPACT }, | |
205 | { SH64_COMPACT_INSN_STSL_PR_COMPACT, && case_sem_INSN_STSL_PR_COMPACT }, | |
206 | { SH64_COMPACT_INSN_SUB_COMPACT, && case_sem_INSN_SUB_COMPACT }, | |
207 | { SH64_COMPACT_INSN_SUBC_COMPACT, && case_sem_INSN_SUBC_COMPACT }, | |
208 | { SH64_COMPACT_INSN_SUBV_COMPACT, && case_sem_INSN_SUBV_COMPACT }, | |
209 | { SH64_COMPACT_INSN_SWAPB_COMPACT, && case_sem_INSN_SWAPB_COMPACT }, | |
210 | { SH64_COMPACT_INSN_SWAPW_COMPACT, && case_sem_INSN_SWAPW_COMPACT }, | |
211 | { SH64_COMPACT_INSN_TASB_COMPACT, && case_sem_INSN_TASB_COMPACT }, | |
212 | { SH64_COMPACT_INSN_TRAPA_COMPACT, && case_sem_INSN_TRAPA_COMPACT }, | |
213 | { SH64_COMPACT_INSN_TST_COMPACT, && case_sem_INSN_TST_COMPACT }, | |
214 | { SH64_COMPACT_INSN_TSTI_COMPACT, && case_sem_INSN_TSTI_COMPACT }, | |
215 | { SH64_COMPACT_INSN_TSTB_COMPACT, && case_sem_INSN_TSTB_COMPACT }, | |
216 | { SH64_COMPACT_INSN_XOR_COMPACT, && case_sem_INSN_XOR_COMPACT }, | |
217 | { SH64_COMPACT_INSN_XORI_COMPACT, && case_sem_INSN_XORI_COMPACT }, | |
218 | { SH64_COMPACT_INSN_XORB_COMPACT, && case_sem_INSN_XORB_COMPACT }, | |
219 | { SH64_COMPACT_INSN_XTRCT_COMPACT, && case_sem_INSN_XTRCT_COMPACT }, | |
220 | { 0, 0 } | |
221 | }; | |
222 | int i; | |
223 | ||
224 | for (i = 0; labels[i].label != 0; ++i) | |
225 | { | |
226 | #if FAST_P | |
227 | CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label; | |
228 | #else | |
229 | CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label; | |
230 | #endif | |
231 | } | |
232 | ||
233 | #undef DEFINE_LABELS | |
234 | #endif /* DEFINE_LABELS */ | |
235 | ||
236 | #ifdef DEFINE_SWITCH | |
237 | ||
238 | /* If hyper-fast [well not unnecessarily slow] execution is selected, turn | |
239 | off frills like tracing and profiling. */ | |
240 | /* FIXME: A better way would be to have TRACE_RESULT check for something | |
241 | that can cause it to be optimized out. Another way would be to emit | |
242 | special handlers into the instruction "stream". */ | |
243 | ||
244 | #if FAST_P | |
245 | #undef TRACE_RESULT | |
246 | #define TRACE_RESULT(cpu, abuf, name, type, val) | |
247 | #endif | |
248 | ||
249 | #undef GET_ATTR | |
250 | #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) | |
251 | #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr) | |
252 | #else | |
253 | #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr) | |
254 | #endif | |
255 | ||
256 | { | |
257 | ||
258 | #if WITH_SCACHE_PBB | |
259 | ||
260 | /* Branch to next handler without going around main loop. */ | |
261 | #define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case | |
262 | SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) | |
263 | ||
264 | #else /* ! WITH_SCACHE_PBB */ | |
265 | ||
266 | #define NEXT(vpc) BREAK (sem) | |
267 | #ifdef __GNUC__ | |
268 | #if FAST_P | |
269 | SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab) | |
270 | #else | |
271 | SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab) | |
272 | #endif | |
273 | #else | |
274 | SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num) | |
275 | #endif | |
276 | ||
277 | #endif /* ! WITH_SCACHE_PBB */ | |
278 | ||
279 | { | |
280 | ||
281 | CASE (sem, INSN_X_INVALID) : /* --invalid-- */ | |
282 | { | |
283 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
284 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
285 | #define FLD(f) abuf->fields.fmt_empty.f | |
286 | int UNUSED written = 0; | |
287 | IADDR UNUSED pc = abuf->addr; | |
288 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
289 | ||
290 | { | |
291 | /* Update the recorded pc in the cpu state struct. | |
292 | Only necessary for WITH_SCACHE case, but to avoid the | |
293 | conditional compilation .... */ | |
294 | SET_H_PC (pc); | |
295 | /* Virtual insns have zero size. Overwrite vpc with address of next insn | |
296 | using the default-insn-bitsize spec. When executing insns in parallel | |
297 | we may want to queue the fault and continue execution. */ | |
298 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
299 | vpc = sim_engine_invalid_insn (current_cpu, pc, vpc); | |
300 | } | |
301 | ||
302 | #undef FLD | |
303 | } | |
304 | NEXT (vpc); | |
305 | ||
306 | CASE (sem, INSN_X_AFTER) : /* --after-- */ | |
307 | { | |
308 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
309 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
310 | #define FLD(f) abuf->fields.fmt_empty.f | |
311 | int UNUSED written = 0; | |
312 | IADDR UNUSED pc = abuf->addr; | |
313 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
314 | ||
315 | { | |
316 | #if WITH_SCACHE_PBB_SH64_COMPACT | |
317 | sh64_compact_pbb_after (current_cpu, sem_arg); | |
318 | #endif | |
319 | } | |
320 | ||
321 | #undef FLD | |
322 | } | |
323 | NEXT (vpc); | |
324 | ||
325 | CASE (sem, INSN_X_BEFORE) : /* --before-- */ | |
326 | { | |
327 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
328 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
329 | #define FLD(f) abuf->fields.fmt_empty.f | |
330 | int UNUSED written = 0; | |
331 | IADDR UNUSED pc = abuf->addr; | |
332 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
333 | ||
334 | { | |
335 | #if WITH_SCACHE_PBB_SH64_COMPACT | |
336 | sh64_compact_pbb_before (current_cpu, sem_arg); | |
337 | #endif | |
338 | } | |
339 | ||
340 | #undef FLD | |
341 | } | |
342 | NEXT (vpc); | |
343 | ||
344 | CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */ | |
345 | { | |
346 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
347 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
348 | #define FLD(f) abuf->fields.fmt_empty.f | |
349 | int UNUSED written = 0; | |
350 | IADDR UNUSED pc = abuf->addr; | |
351 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
352 | ||
353 | { | |
354 | #if WITH_SCACHE_PBB_SH64_COMPACT | |
355 | #ifdef DEFINE_SWITCH | |
356 | vpc = sh64_compact_pbb_cti_chain (current_cpu, sem_arg, | |
357 | pbb_br_type, pbb_br_npc); | |
358 | BREAK (sem); | |
359 | #else | |
360 | /* FIXME: Allow provision of explicit ifmt spec in insn spec. */ | |
361 | vpc = sh64_compact_pbb_cti_chain (current_cpu, sem_arg, | |
362 | CPU_PBB_BR_TYPE (current_cpu), | |
363 | CPU_PBB_BR_NPC (current_cpu)); | |
364 | #endif | |
365 | #endif | |
366 | } | |
367 | ||
368 | #undef FLD | |
369 | } | |
370 | NEXT (vpc); | |
371 | ||
372 | CASE (sem, INSN_X_CHAIN) : /* --chain-- */ | |
373 | { | |
374 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
375 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
376 | #define FLD(f) abuf->fields.fmt_empty.f | |
377 | int UNUSED written = 0; | |
378 | IADDR UNUSED pc = abuf->addr; | |
379 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
380 | ||
381 | { | |
382 | #if WITH_SCACHE_PBB_SH64_COMPACT | |
383 | vpc = sh64_compact_pbb_chain (current_cpu, sem_arg); | |
384 | #ifdef DEFINE_SWITCH | |
385 | BREAK (sem); | |
386 | #endif | |
387 | #endif | |
388 | } | |
389 | ||
390 | #undef FLD | |
391 | } | |
392 | NEXT (vpc); | |
393 | ||
394 | CASE (sem, INSN_X_BEGIN) : /* --begin-- */ | |
395 | { | |
396 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
397 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
398 | #define FLD(f) abuf->fields.fmt_empty.f | |
399 | int UNUSED written = 0; | |
400 | IADDR UNUSED pc = abuf->addr; | |
401 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
402 | ||
403 | { | |
404 | #if WITH_SCACHE_PBB_SH64_COMPACT | |
405 | #if defined DEFINE_SWITCH || defined FAST_P | |
406 | /* In the switch case FAST_P is a constant, allowing several optimizations | |
407 | in any called inline functions. */ | |
408 | vpc = sh64_compact_pbb_begin (current_cpu, FAST_P); | |
409 | #else | |
410 | #if 0 /* cgen engine can't handle dynamic fast/full switching yet. */ | |
411 | vpc = sh64_compact_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu))); | |
412 | #else | |
413 | vpc = sh64_compact_pbb_begin (current_cpu, 0); | |
414 | #endif | |
415 | #endif | |
416 | #endif | |
417 | } | |
418 | ||
419 | #undef FLD | |
420 | } | |
421 | NEXT (vpc); | |
422 | ||
423 | CASE (sem, INSN_ADD_COMPACT) : /* add $rm, $rn */ | |
424 | { | |
425 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
426 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
427 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
428 | int UNUSED written = 0; | |
429 | IADDR UNUSED pc = abuf->addr; | |
430 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
431 | ||
432 | { | |
433 | SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm))); | |
434 | SET_H_GRC (FLD (f_rn), opval); | |
435 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
436 | } | |
437 | ||
438 | #undef FLD | |
439 | } | |
440 | NEXT (vpc); | |
441 | ||
442 | CASE (sem, INSN_ADDI_COMPACT) : /* add #$imm8, $rn */ | |
443 | { | |
444 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
445 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
446 | #define FLD(f) abuf->fields.sfmt_addi_compact.f | |
447 | int UNUSED written = 0; | |
448 | IADDR UNUSED pc = abuf->addr; | |
449 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
450 | ||
451 | { | |
452 | SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), EXTQISI (ANDQI (FLD (f_imm8), 255))); | |
453 | SET_H_GRC (FLD (f_rn), opval); | |
454 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
455 | } | |
456 | ||
457 | #undef FLD | |
458 | } | |
459 | NEXT (vpc); | |
460 | ||
461 | CASE (sem, INSN_ADDC_COMPACT) : /* addc $rm, $rn */ | |
462 | { | |
463 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
464 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
465 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
466 | int UNUSED written = 0; | |
467 | IADDR UNUSED pc = abuf->addr; | |
468 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
469 | ||
470 | { | |
471 | BI tmp_flag; | |
472 | tmp_flag = ADDCFSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), GET_H_TBIT ()); | |
473 | { | |
474 | SI opval = ADDCSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), GET_H_TBIT ()); | |
475 | SET_H_GRC (FLD (f_rn), opval); | |
476 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
477 | } | |
478 | { | |
479 | BI opval = tmp_flag; | |
480 | SET_H_TBIT (opval); | |
481 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); | |
482 | } | |
483 | } | |
484 | ||
485 | #undef FLD | |
486 | } | |
487 | NEXT (vpc); | |
488 | ||
489 | CASE (sem, INSN_ADDV_COMPACT) : /* addv $rm, $rn */ | |
490 | { | |
491 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
492 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
493 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
494 | int UNUSED written = 0; | |
495 | IADDR UNUSED pc = abuf->addr; | |
496 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
497 | ||
498 | { | |
499 | BI tmp_t; | |
500 | tmp_t = ADDOFSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), 0); | |
501 | { | |
502 | SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm))); | |
503 | SET_H_GRC (FLD (f_rn), opval); | |
504 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
505 | } | |
506 | { | |
507 | BI opval = tmp_t; | |
508 | SET_H_TBIT (opval); | |
509 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); | |
510 | } | |
511 | } | |
512 | ||
513 | #undef FLD | |
514 | } | |
515 | NEXT (vpc); | |
516 | ||
517 | CASE (sem, INSN_AND_COMPACT) : /* and $rm64, $rn64 */ | |
518 | { | |
519 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
520 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
521 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
522 | int UNUSED written = 0; | |
523 | IADDR UNUSED pc = abuf->addr; | |
524 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
525 | ||
526 | { | |
527 | DI opval = ANDDI (GET_H_GR (FLD (f_rm)), GET_H_GR (FLD (f_rn))); | |
528 | SET_H_GR (FLD (f_rn), opval); | |
529 | TRACE_RESULT (current_cpu, abuf, "rn64", 'D', opval); | |
530 | } | |
531 | ||
532 | #undef FLD | |
533 | } | |
534 | NEXT (vpc); | |
535 | ||
536 | CASE (sem, INSN_ANDI_COMPACT) : /* and #$uimm8, r0 */ | |
537 | { | |
538 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
539 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
540 | #define FLD(f) abuf->fields.sfmt_addi_compact.f | |
541 | int UNUSED written = 0; | |
542 | IADDR UNUSED pc = abuf->addr; | |
543 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
544 | ||
545 | { | |
546 | SI opval = ANDSI (GET_H_GRC (((UINT) 0)), ZEXTSIDI (FLD (f_imm8))); | |
547 | SET_H_GRC (((UINT) 0), opval); | |
548 | TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval); | |
549 | } | |
550 | ||
551 | #undef FLD | |
552 | } | |
553 | NEXT (vpc); | |
554 | ||
555 | CASE (sem, INSN_ANDB_COMPACT) : /* and.b #$imm8, @(r0, gbr) */ | |
556 | { | |
557 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
558 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
559 | #define FLD(f) abuf->fields.sfmt_addi_compact.f | |
560 | int UNUSED written = 0; | |
561 | IADDR UNUSED pc = abuf->addr; | |
562 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
563 | ||
564 | { | |
565 | DI tmp_addr; | |
566 | UQI tmp_data; | |
567 | tmp_addr = ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GBR ()); | |
568 | tmp_data = ANDQI (GETMEMUQI (current_cpu, pc, tmp_addr), FLD (f_imm8)); | |
569 | { | |
570 | UQI opval = tmp_data; | |
571 | SETMEMUQI (current_cpu, pc, tmp_addr, opval); | |
572 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
573 | } | |
574 | } | |
575 | ||
576 | #undef FLD | |
577 | } | |
578 | NEXT (vpc); | |
579 | ||
580 | CASE (sem, INSN_BF_COMPACT) : /* bf $disp8 */ | |
581 | { | |
582 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
583 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
584 | #define FLD(f) abuf->fields.sfmt_bf_compact.f | |
585 | int UNUSED written = 0; | |
586 | IADDR UNUSED pc = abuf->addr; | |
587 | SEM_BRANCH_INIT | |
588 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
589 | ||
590 | if (NOTBI (GET_H_TBIT ())) { | |
591 | { | |
592 | UDI opval = FLD (i_disp8); | |
593 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
594 | written |= (1 << 2); | |
595 | TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); | |
596 | } | |
597 | } | |
598 | ||
599 | abuf->written = written; | |
600 | SEM_BRANCH_FINI (vpc); | |
601 | #undef FLD | |
602 | } | |
603 | NEXT (vpc); | |
604 | ||
605 | CASE (sem, INSN_BFS_COMPACT) : /* bf/s $disp8 */ | |
606 | { | |
607 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
608 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
609 | #define FLD(f) abuf->fields.sfmt_bf_compact.f | |
610 | int UNUSED written = 0; | |
611 | IADDR UNUSED pc = abuf->addr; | |
612 | SEM_BRANCH_INIT | |
613 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
614 | ||
615 | if (NOTBI (GET_H_TBIT ())) { | |
616 | { | |
617 | { | |
618 | UDI opval = FLD (i_disp8); | |
619 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
620 | written |= (1 << 2); | |
621 | TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); | |
622 | } | |
623 | } | |
624 | } | |
625 | ||
626 | abuf->written = written; | |
627 | SEM_BRANCH_FINI (vpc); | |
628 | #undef FLD | |
629 | } | |
630 | NEXT (vpc); | |
631 | ||
632 | CASE (sem, INSN_BRA_COMPACT) : /* bra $disp12 */ | |
633 | { | |
634 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
635 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
636 | #define FLD(f) abuf->fields.sfmt_bra_compact.f | |
637 | int UNUSED written = 0; | |
638 | IADDR UNUSED pc = abuf->addr; | |
639 | SEM_BRANCH_INIT | |
640 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
641 | ||
642 | { | |
643 | { | |
644 | UDI opval = FLD (i_disp12); | |
645 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
646 | TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); | |
647 | } | |
648 | } | |
649 | ||
650 | SEM_BRANCH_FINI (vpc); | |
651 | #undef FLD | |
652 | } | |
653 | NEXT (vpc); | |
654 | ||
655 | CASE (sem, INSN_BRAF_COMPACT) : /* braf $rn */ | |
656 | { | |
657 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
658 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
659 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
660 | int UNUSED written = 0; | |
661 | IADDR UNUSED pc = abuf->addr; | |
662 | SEM_BRANCH_INIT | |
663 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
664 | ||
665 | { | |
666 | { | |
667 | UDI opval = ADDDI (EXTSIDI (GET_H_GRC (FLD (f_rn))), ADDDI (pc, 4)); | |
668 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); | |
669 | TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); | |
670 | } | |
671 | } | |
672 | ||
673 | SEM_BRANCH_FINI (vpc); | |
674 | #undef FLD | |
675 | } | |
676 | NEXT (vpc); | |
677 | ||
678 | CASE (sem, INSN_BRK_COMPACT) : /* brk */ | |
679 | { | |
680 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
681 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
682 | #define FLD(f) abuf->fields.fmt_empty.f | |
683 | int UNUSED written = 0; | |
684 | IADDR UNUSED pc = abuf->addr; | |
685 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
686 | ||
687 | sh64_break (current_cpu, pc); | |
688 | ||
689 | #undef FLD | |
690 | } | |
691 | NEXT (vpc); | |
692 | ||
693 | CASE (sem, INSN_BSR_COMPACT) : /* bsr $disp12 */ | |
694 | { | |
695 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
696 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
697 | #define FLD(f) abuf->fields.sfmt_bra_compact.f | |
698 | int UNUSED written = 0; | |
699 | IADDR UNUSED pc = abuf->addr; | |
700 | SEM_BRANCH_INIT | |
701 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
702 | ||
703 | { | |
704 | { | |
705 | { | |
706 | SI opval = ADDDI (pc, 4); | |
707 | SET_H_PR (opval); | |
708 | TRACE_RESULT (current_cpu, abuf, "pr", 'x', opval); | |
709 | } | |
710 | { | |
711 | UDI opval = FLD (i_disp12); | |
712 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
713 | TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); | |
714 | } | |
715 | } | |
716 | } | |
717 | ||
718 | SEM_BRANCH_FINI (vpc); | |
719 | #undef FLD | |
720 | } | |
721 | NEXT (vpc); | |
722 | ||
723 | CASE (sem, INSN_BSRF_COMPACT) : /* bsrf $rn */ | |
724 | { | |
725 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
726 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
727 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
728 | int UNUSED written = 0; | |
729 | IADDR UNUSED pc = abuf->addr; | |
730 | SEM_BRANCH_INIT | |
731 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
732 | ||
733 | { | |
734 | { | |
735 | { | |
736 | SI opval = ADDDI (pc, 4); | |
737 | SET_H_PR (opval); | |
738 | TRACE_RESULT (current_cpu, abuf, "pr", 'x', opval); | |
739 | } | |
740 | { | |
741 | UDI opval = ADDDI (EXTSIDI (GET_H_GRC (FLD (f_rn))), ADDDI (pc, 4)); | |
742 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); | |
743 | TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); | |
744 | } | |
745 | } | |
746 | } | |
747 | ||
748 | SEM_BRANCH_FINI (vpc); | |
749 | #undef FLD | |
750 | } | |
751 | NEXT (vpc); | |
752 | ||
753 | CASE (sem, INSN_BT_COMPACT) : /* bt $disp8 */ | |
754 | { | |
755 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
756 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
757 | #define FLD(f) abuf->fields.sfmt_bf_compact.f | |
758 | int UNUSED written = 0; | |
759 | IADDR UNUSED pc = abuf->addr; | |
760 | SEM_BRANCH_INIT | |
761 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
762 | ||
763 | if (GET_H_TBIT ()) { | |
764 | { | |
765 | UDI opval = FLD (i_disp8); | |
766 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
767 | written |= (1 << 2); | |
768 | TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); | |
769 | } | |
770 | } | |
771 | ||
772 | abuf->written = written; | |
773 | SEM_BRANCH_FINI (vpc); | |
774 | #undef FLD | |
775 | } | |
776 | NEXT (vpc); | |
777 | ||
778 | CASE (sem, INSN_BTS_COMPACT) : /* bt/s $disp8 */ | |
779 | { | |
780 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
781 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
782 | #define FLD(f) abuf->fields.sfmt_bf_compact.f | |
783 | int UNUSED written = 0; | |
784 | IADDR UNUSED pc = abuf->addr; | |
785 | SEM_BRANCH_INIT | |
786 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
787 | ||
788 | if (GET_H_TBIT ()) { | |
789 | { | |
790 | { | |
791 | UDI opval = FLD (i_disp8); | |
792 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
793 | written |= (1 << 2); | |
794 | TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); | |
795 | } | |
796 | } | |
797 | } | |
798 | ||
799 | abuf->written = written; | |
800 | SEM_BRANCH_FINI (vpc); | |
801 | #undef FLD | |
802 | } | |
803 | NEXT (vpc); | |
804 | ||
805 | CASE (sem, INSN_CLRMAC_COMPACT) : /* clrmac */ | |
806 | { | |
807 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
808 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
809 | #define FLD(f) abuf->fields.fmt_empty.f | |
810 | int UNUSED written = 0; | |
811 | IADDR UNUSED pc = abuf->addr; | |
812 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
813 | ||
814 | { | |
815 | { | |
816 | SI opval = 0; | |
817 | SET_H_MACL (opval); | |
818 | TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval); | |
819 | } | |
820 | { | |
821 | SI opval = 0; | |
822 | SET_H_MACH (opval); | |
823 | TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval); | |
824 | } | |
825 | } | |
826 | ||
827 | #undef FLD | |
828 | } | |
829 | NEXT (vpc); | |
830 | ||
831 | CASE (sem, INSN_CLRS_COMPACT) : /* clrs */ | |
832 | { | |
833 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
834 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
835 | #define FLD(f) abuf->fields.fmt_empty.f | |
836 | int UNUSED written = 0; | |
837 | IADDR UNUSED pc = abuf->addr; | |
838 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
839 | ||
840 | { | |
841 | BI opval = 0; | |
842 | SET_H_SBIT (opval); | |
843 | TRACE_RESULT (current_cpu, abuf, "sbit", 'x', opval); | |
844 | } | |
845 | ||
846 | #undef FLD | |
847 | } | |
848 | NEXT (vpc); | |
849 | ||
850 | CASE (sem, INSN_CLRT_COMPACT) : /* clrt */ | |
851 | { | |
852 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
853 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
854 | #define FLD(f) abuf->fields.fmt_empty.f | |
855 | int UNUSED written = 0; | |
856 | IADDR UNUSED pc = abuf->addr; | |
857 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
858 | ||
859 | { | |
860 | BI opval = 0; | |
861 | SET_H_TBIT (opval); | |
862 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); | |
863 | } | |
864 | ||
865 | #undef FLD | |
866 | } | |
867 | NEXT (vpc); | |
868 | ||
869 | CASE (sem, INSN_CMPEQ_COMPACT) : /* cmp/eq $rm, $rn */ | |
870 | { | |
871 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
872 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
873 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
874 | int UNUSED written = 0; | |
875 | IADDR UNUSED pc = abuf->addr; | |
876 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
877 | ||
878 | { | |
879 | BI opval = EQSI (GET_H_GRC (FLD (f_rm)), GET_H_GRC (FLD (f_rn))); | |
880 | SET_H_TBIT (opval); | |
881 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); | |
882 | } | |
883 | ||
884 | #undef FLD | |
885 | } | |
886 | NEXT (vpc); | |
887 | ||
888 | CASE (sem, INSN_CMPEQI_COMPACT) : /* cmp/eq #$imm8, r0 */ | |
889 | { | |
890 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
891 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
892 | #define FLD(f) abuf->fields.sfmt_addi_compact.f | |
893 | int UNUSED written = 0; | |
894 | IADDR UNUSED pc = abuf->addr; | |
895 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
896 | ||
897 | { | |
898 | BI opval = EQSI (GET_H_GRC (((UINT) 0)), EXTQISI (ANDQI (FLD (f_imm8), 255))); | |
899 | SET_H_TBIT (opval); | |
900 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); | |
901 | } | |
902 | ||
903 | #undef FLD | |
904 | } | |
905 | NEXT (vpc); | |
906 | ||
907 | CASE (sem, INSN_CMPGE_COMPACT) : /* cmp/ge $rm, $rn */ | |
908 | { | |
909 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
910 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
911 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
912 | int UNUSED written = 0; | |
913 | IADDR UNUSED pc = abuf->addr; | |
914 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
915 | ||
916 | { | |
917 | BI opval = GESI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm))); | |
918 | SET_H_TBIT (opval); | |
919 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); | |
920 | } | |
921 | ||
922 | #undef FLD | |
923 | } | |
924 | NEXT (vpc); | |
925 | ||
926 | CASE (sem, INSN_CMPGT_COMPACT) : /* cmp/gt $rm, $rn */ | |
927 | { | |
928 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
929 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
930 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
931 | int UNUSED written = 0; | |
932 | IADDR UNUSED pc = abuf->addr; | |
933 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
934 | ||
935 | { | |
936 | BI opval = GTSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm))); | |
937 | SET_H_TBIT (opval); | |
938 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); | |
939 | } | |
940 | ||
941 | #undef FLD | |
942 | } | |
943 | NEXT (vpc); | |
944 | ||
945 | CASE (sem, INSN_CMPHI_COMPACT) : /* cmp/hi $rm, $rn */ | |
946 | { | |
947 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
948 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
949 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
950 | int UNUSED written = 0; | |
951 | IADDR UNUSED pc = abuf->addr; | |
952 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
953 | ||
954 | { | |
955 | BI opval = GTUSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm))); | |
956 | SET_H_TBIT (opval); | |
957 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); | |
958 | } | |
959 | ||
960 | #undef FLD | |
961 | } | |
962 | NEXT (vpc); | |
963 | ||
964 | CASE (sem, INSN_CMPHS_COMPACT) : /* cmp/hs $rm, $rn */ | |
965 | { | |
966 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
967 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
968 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
969 | int UNUSED written = 0; | |
970 | IADDR UNUSED pc = abuf->addr; | |
971 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
972 | ||
973 | { | |
974 | BI opval = GEUSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm))); | |
975 | SET_H_TBIT (opval); | |
976 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); | |
977 | } | |
978 | ||
979 | #undef FLD | |
980 | } | |
981 | NEXT (vpc); | |
982 | ||
983 | CASE (sem, INSN_CMPPL_COMPACT) : /* cmp/pl $rn */ | |
984 | { | |
985 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
986 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
987 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
988 | int UNUSED written = 0; | |
989 | IADDR UNUSED pc = abuf->addr; | |
990 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
991 | ||
992 | { | |
993 | BI opval = GTSI (GET_H_GRC (FLD (f_rn)), 0); | |
994 | SET_H_TBIT (opval); | |
995 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); | |
996 | } | |
997 | ||
998 | #undef FLD | |
999 | } | |
1000 | NEXT (vpc); | |
1001 | ||
1002 | CASE (sem, INSN_CMPPZ_COMPACT) : /* cmp/pz $rn */ | |
1003 | { | |
1004 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1005 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1006 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
1007 | int UNUSED written = 0; | |
1008 | IADDR UNUSED pc = abuf->addr; | |
1009 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1010 | ||
1011 | { | |
1012 | BI opval = GESI (GET_H_GRC (FLD (f_rn)), 0); | |
1013 | SET_H_TBIT (opval); | |
1014 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); | |
1015 | } | |
1016 | ||
1017 | #undef FLD | |
1018 | } | |
1019 | NEXT (vpc); | |
1020 | ||
1021 | CASE (sem, INSN_CMPSTR_COMPACT) : /* cmp/str $rm, $rn */ | |
1022 | { | |
1023 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1024 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1025 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
1026 | int UNUSED written = 0; | |
1027 | IADDR UNUSED pc = abuf->addr; | |
1028 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1029 | ||
1030 | { | |
1031 | BI tmp_t; | |
1032 | SI tmp_temp; | |
1033 | tmp_temp = XORSI (GET_H_GRC (FLD (f_rm)), GET_H_GRC (FLD (f_rn))); | |
1034 | tmp_t = EQSI (ANDSI (tmp_temp, 0xff000000), 0); | |
1035 | tmp_t = ORBI (EQSI (ANDSI (tmp_temp, 16711680), 0), tmp_t); | |
1036 | tmp_t = ORBI (EQSI (ANDSI (tmp_temp, 65280), 0), tmp_t); | |
1037 | tmp_t = ORBI (EQSI (ANDSI (tmp_temp, 255), 0), tmp_t); | |
1038 | { | |
1039 | BI opval = ((GTUBI (tmp_t, 0)) ? (1) : (0)); | |
1040 | SET_H_TBIT (opval); | |
1041 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); | |
1042 | } | |
1043 | } | |
1044 | ||
1045 | #undef FLD | |
1046 | } | |
1047 | NEXT (vpc); | |
1048 | ||
1049 | CASE (sem, INSN_DIV0S_COMPACT) : /* div0s $rm, $rn */ | |
1050 | { | |
1051 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1052 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1053 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
1054 | int UNUSED written = 0; | |
1055 | IADDR UNUSED pc = abuf->addr; | |
1056 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1057 | ||
1058 | { | |
1059 | { | |
1060 | BI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 31); | |
1061 | SET_H_QBIT (opval); | |
1062 | TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval); | |
1063 | } | |
1064 | { | |
1065 | BI opval = SRLSI (GET_H_GRC (FLD (f_rm)), 31); | |
1066 | SET_H_MBIT (opval); | |
1067 | TRACE_RESULT (current_cpu, abuf, "mbit", 'x', opval); | |
1068 | } | |
1069 | { | |
1070 | BI opval = ((EQSI (SRLSI (GET_H_GRC (FLD (f_rm)), 31), SRLSI (GET_H_GRC (FLD (f_rn)), 31))) ? (0) : (1)); | |
1071 | SET_H_TBIT (opval); | |
1072 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); | |
1073 | } | |
1074 | } | |
1075 | ||
1076 | #undef FLD | |
1077 | } | |
1078 | NEXT (vpc); | |
1079 | ||
1080 | CASE (sem, INSN_DIV0U_COMPACT) : /* div0u */ | |
1081 | { | |
1082 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1083 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1084 | #define FLD(f) abuf->fields.fmt_empty.f | |
1085 | int UNUSED written = 0; | |
1086 | IADDR UNUSED pc = abuf->addr; | |
1087 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1088 | ||
1089 | { | |
1090 | { | |
1091 | BI opval = 0; | |
1092 | SET_H_TBIT (opval); | |
1093 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); | |
1094 | } | |
1095 | { | |
1096 | BI opval = 0; | |
1097 | SET_H_QBIT (opval); | |
1098 | TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval); | |
1099 | } | |
1100 | { | |
1101 | BI opval = 0; | |
1102 | SET_H_MBIT (opval); | |
1103 | TRACE_RESULT (current_cpu, abuf, "mbit", 'x', opval); | |
1104 | } | |
1105 | } | |
1106 | ||
1107 | #undef FLD | |
1108 | } | |
1109 | NEXT (vpc); | |
1110 | ||
1111 | CASE (sem, INSN_DIV1_COMPACT) : /* div1 $rm, $rn */ | |
1112 | { | |
1113 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1114 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1115 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
1116 | int UNUSED written = 0; | |
1117 | IADDR UNUSED pc = abuf->addr; | |
1118 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1119 | ||
1120 | { | |
1121 | BI tmp_oldq; | |
1122 | SI tmp_tmp0; | |
1123 | UQI tmp_tmp1; | |
1124 | tmp_oldq = GET_H_QBIT (); | |
1125 | { | |
1126 | BI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 31); | |
1127 | SET_H_QBIT (opval); | |
1128 | TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval); | |
1129 | } | |
1130 | { | |
1131 | SI opval = ORSI (SLLSI (GET_H_GRC (FLD (f_rn)), 1), ZEXTBISI (GET_H_TBIT ())); | |
1132 | SET_H_GRC (FLD (f_rn), opval); | |
1133 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
1134 | } | |
1135 | if (NOTBI (tmp_oldq)) { | |
1136 | if (NOTBI (GET_H_MBIT ())) { | |
1137 | { | |
1138 | tmp_tmp0 = GET_H_GRC (FLD (f_rn)); | |
1139 | { | |
1140 | SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm))); | |
1141 | SET_H_GRC (FLD (f_rn), opval); | |
1142 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
1143 | } | |
1144 | tmp_tmp1 = GTUSI (GET_H_GRC (FLD (f_rn)), tmp_tmp0); | |
1145 | if (NOTBI (GET_H_QBIT ())) { | |
1146 | { | |
1147 | BI opval = ((tmp_tmp1) ? (1) : (0)); | |
1148 | SET_H_QBIT (opval); | |
1149 | TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval); | |
1150 | } | |
1151 | } else { | |
1152 | { | |
1153 | BI opval = ((EQQI (tmp_tmp1, 0)) ? (1) : (0)); | |
1154 | SET_H_QBIT (opval); | |
1155 | TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval); | |
1156 | } | |
1157 | } | |
1158 | } | |
1159 | } else { | |
1160 | { | |
1161 | tmp_tmp0 = GET_H_GRC (FLD (f_rn)); | |
1162 | { | |
1163 | SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm))); | |
1164 | SET_H_GRC (FLD (f_rn), opval); | |
1165 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
1166 | } | |
1167 | tmp_tmp1 = LTUSI (GET_H_GRC (FLD (f_rn)), tmp_tmp0); | |
1168 | if (NOTBI (GET_H_QBIT ())) { | |
1169 | { | |
1170 | BI opval = ((EQQI (tmp_tmp1, 0)) ? (1) : (0)); | |
1171 | SET_H_QBIT (opval); | |
1172 | TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval); | |
1173 | } | |
1174 | } else { | |
1175 | { | |
1176 | BI opval = ((tmp_tmp1) ? (1) : (0)); | |
1177 | SET_H_QBIT (opval); | |
1178 | TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval); | |
1179 | } | |
1180 | } | |
1181 | } | |
1182 | } | |
1183 | } else { | |
1184 | if (NOTBI (GET_H_MBIT ())) { | |
1185 | { | |
1186 | tmp_tmp0 = GET_H_GRC (FLD (f_rn)); | |
1187 | { | |
1188 | SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), GET_H_GRC (FLD (f_rn))); | |
1189 | SET_H_GRC (FLD (f_rn), opval); | |
1190 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
1191 | } | |
1192 | tmp_tmp1 = LTUSI (GET_H_GRC (FLD (f_rn)), tmp_tmp0); | |
1193 | if (NOTBI (GET_H_QBIT ())) { | |
1194 | { | |
1195 | BI opval = ((tmp_tmp1) ? (1) : (0)); | |
1196 | SET_H_QBIT (opval); | |
1197 | TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval); | |
1198 | } | |
1199 | } else { | |
1200 | { | |
1201 | BI opval = ((EQQI (tmp_tmp1, 0)) ? (1) : (0)); | |
1202 | SET_H_QBIT (opval); | |
1203 | TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval); | |
1204 | } | |
1205 | } | |
1206 | } | |
1207 | } else { | |
1208 | { | |
1209 | tmp_tmp0 = GET_H_GRC (FLD (f_rn)); | |
1210 | { | |
1211 | SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm))); | |
1212 | SET_H_GRC (FLD (f_rn), opval); | |
1213 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
1214 | } | |
1215 | tmp_tmp1 = GTUSI (GET_H_GRC (FLD (f_rn)), tmp_tmp0); | |
1216 | if (NOTBI (GET_H_QBIT ())) { | |
1217 | { | |
1218 | BI opval = ((EQQI (tmp_tmp1, 0)) ? (1) : (0)); | |
1219 | SET_H_QBIT (opval); | |
1220 | TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval); | |
1221 | } | |
1222 | } else { | |
1223 | { | |
1224 | BI opval = ((tmp_tmp1) ? (1) : (0)); | |
1225 | SET_H_QBIT (opval); | |
1226 | TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval); | |
1227 | } | |
1228 | } | |
1229 | } | |
1230 | } | |
1231 | } | |
1232 | { | |
1233 | BI opval = ((EQBI (GET_H_QBIT (), GET_H_MBIT ())) ? (1) : (0)); | |
1234 | SET_H_TBIT (opval); | |
1235 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); | |
1236 | } | |
1237 | } | |
1238 | ||
1239 | #undef FLD | |
1240 | } | |
1241 | NEXT (vpc); | |
1242 | ||
1243 | CASE (sem, INSN_DMULSL_COMPACT) : /* dmuls.l $rm, $rn */ | |
1244 | { | |
1245 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1246 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1247 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
1248 | int UNUSED written = 0; | |
1249 | IADDR UNUSED pc = abuf->addr; | |
1250 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1251 | ||
1252 | { | |
1253 | DI tmp_result; | |
1254 | tmp_result = MULDI (EXTSIDI (GET_H_GRC (FLD (f_rm))), EXTSIDI (GET_H_GRC (FLD (f_rn)))); | |
1255 | { | |
1256 | SI opval = SUBWORDDISI (tmp_result, 0); | |
1257 | SET_H_MACH (opval); | |
1258 | TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval); | |
1259 | } | |
1260 | { | |
1261 | SI opval = SUBWORDDISI (tmp_result, 1); | |
1262 | SET_H_MACL (opval); | |
1263 | TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval); | |
1264 | } | |
1265 | } | |
1266 | ||
1267 | #undef FLD | |
1268 | } | |
1269 | NEXT (vpc); | |
1270 | ||
1271 | CASE (sem, INSN_DMULUL_COMPACT) : /* dmulu.l $rm, $rn */ | |
1272 | { | |
1273 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1274 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1275 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
1276 | int UNUSED written = 0; | |
1277 | IADDR UNUSED pc = abuf->addr; | |
1278 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1279 | ||
1280 | { | |
1281 | DI tmp_result; | |
1282 | tmp_result = MULDI (ZEXTSIDI (GET_H_GRC (FLD (f_rm))), ZEXTSIDI (GET_H_GRC (FLD (f_rn)))); | |
1283 | { | |
1284 | SI opval = SUBWORDDISI (tmp_result, 0); | |
1285 | SET_H_MACH (opval); | |
1286 | TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval); | |
1287 | } | |
1288 | { | |
1289 | SI opval = SUBWORDDISI (tmp_result, 1); | |
1290 | SET_H_MACL (opval); | |
1291 | TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval); | |
1292 | } | |
1293 | } | |
1294 | ||
1295 | #undef FLD | |
1296 | } | |
1297 | NEXT (vpc); | |
1298 | ||
1299 | CASE (sem, INSN_DT_COMPACT) : /* dt $rn */ | |
1300 | { | |
1301 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1302 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1303 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
1304 | int UNUSED written = 0; | |
1305 | IADDR UNUSED pc = abuf->addr; | |
1306 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1307 | ||
1308 | { | |
1309 | { | |
1310 | SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), 1); | |
1311 | SET_H_GRC (FLD (f_rn), opval); | |
1312 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
1313 | } | |
1314 | { | |
1315 | BI opval = EQSI (GET_H_GRC (FLD (f_rn)), 0); | |
1316 | SET_H_TBIT (opval); | |
1317 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); | |
1318 | } | |
1319 | } | |
1320 | ||
1321 | #undef FLD | |
1322 | } | |
1323 | NEXT (vpc); | |
1324 | ||
1325 | CASE (sem, INSN_EXTSB_COMPACT) : /* exts.b $rm, $rn */ | |
1326 | { | |
1327 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1328 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1329 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
1330 | int UNUSED written = 0; | |
1331 | IADDR UNUSED pc = abuf->addr; | |
1332 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1333 | ||
1334 | { | |
1335 | SI opval = EXTQISI (SUBWORDSIQI (GET_H_GRC (FLD (f_rm)), 3)); | |
1336 | SET_H_GRC (FLD (f_rn), opval); | |
1337 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
1338 | } | |
1339 | ||
1340 | #undef FLD | |
1341 | } | |
1342 | NEXT (vpc); | |
1343 | ||
1344 | CASE (sem, INSN_EXTSW_COMPACT) : /* exts.w $rm, $rn */ | |
1345 | { | |
1346 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1347 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1348 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
1349 | int UNUSED written = 0; | |
1350 | IADDR UNUSED pc = abuf->addr; | |
1351 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1352 | ||
1353 | { | |
1354 | SI opval = EXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1)); | |
1355 | SET_H_GRC (FLD (f_rn), opval); | |
1356 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
1357 | } | |
1358 | ||
1359 | #undef FLD | |
1360 | } | |
1361 | NEXT (vpc); | |
1362 | ||
1363 | CASE (sem, INSN_EXTUB_COMPACT) : /* extu.b $rm, $rn */ | |
1364 | { | |
1365 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1366 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1367 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
1368 | int UNUSED written = 0; | |
1369 | IADDR UNUSED pc = abuf->addr; | |
1370 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1371 | ||
1372 | { | |
1373 | SI opval = ZEXTQISI (SUBWORDSIQI (GET_H_GRC (FLD (f_rm)), 3)); | |
1374 | SET_H_GRC (FLD (f_rn), opval); | |
1375 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
1376 | } | |
1377 | ||
1378 | #undef FLD | |
1379 | } | |
1380 | NEXT (vpc); | |
1381 | ||
1382 | CASE (sem, INSN_EXTUW_COMPACT) : /* extu.w $rm, $rn */ | |
1383 | { | |
1384 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1385 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1386 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
1387 | int UNUSED written = 0; | |
1388 | IADDR UNUSED pc = abuf->addr; | |
1389 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1390 | ||
1391 | { | |
1392 | SI opval = ZEXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1)); | |
1393 | SET_H_GRC (FLD (f_rn), opval); | |
1394 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
1395 | } | |
1396 | ||
1397 | #undef FLD | |
1398 | } | |
1399 | NEXT (vpc); | |
1400 | ||
1401 | CASE (sem, INSN_FABS_COMPACT) : /* fabs $fsdn */ | |
1402 | { | |
1403 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1404 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1405 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
1406 | int UNUSED written = 0; | |
1407 | IADDR UNUSED pc = abuf->addr; | |
1408 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1409 | ||
1410 | if (GET_H_PRBIT ()) { | |
1411 | { | |
1412 | DF opval = sh64_fabsd (current_cpu, GET_H_DR (FLD (f_rn))); | |
1413 | SET_H_DR (FLD (f_rn), opval); | |
1414 | written |= (1 << 5); | |
1415 | TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval); | |
1416 | } | |
1417 | } else { | |
1418 | { | |
1419 | SF opval = sh64_fabss (current_cpu, GET_H_FRC (FLD (f_rn))); | |
1420 | SET_H_FRC (FLD (f_rn), opval); | |
1421 | written |= (1 << 4); | |
1422 | TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval); | |
1423 | } | |
1424 | } | |
1425 | ||
1426 | abuf->written = written; | |
1427 | #undef FLD | |
1428 | } | |
1429 | NEXT (vpc); | |
1430 | ||
1431 | CASE (sem, INSN_FADD_COMPACT) : /* fadd $fsdm, $fsdn */ | |
1432 | { | |
1433 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1434 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1435 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
1436 | int UNUSED written = 0; | |
1437 | IADDR UNUSED pc = abuf->addr; | |
1438 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1439 | ||
1440 | if (GET_H_PRBIT ()) { | |
1441 | { | |
1442 | DF opval = sh64_faddd (current_cpu, GET_H_DR (FLD (f_rm)), GET_H_DR (FLD (f_rn))); | |
1443 | SET_H_DR (FLD (f_rn), opval); | |
1444 | written |= (1 << 8); | |
1445 | TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval); | |
1446 | } | |
1447 | } else { | |
1448 | { | |
1449 | SF opval = sh64_fadds (current_cpu, GET_H_FRC (FLD (f_rm)), GET_H_FRC (FLD (f_rn))); | |
1450 | SET_H_FRC (FLD (f_rn), opval); | |
1451 | written |= (1 << 7); | |
1452 | TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval); | |
1453 | } | |
1454 | } | |
1455 | ||
1456 | abuf->written = written; | |
1457 | #undef FLD | |
1458 | } | |
1459 | NEXT (vpc); | |
1460 | ||
1461 | CASE (sem, INSN_FCMPEQ_COMPACT) : /* fcmp/eq $fsdm, $fsdn */ | |
1462 | { | |
1463 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1464 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1465 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
1466 | int UNUSED written = 0; | |
1467 | IADDR UNUSED pc = abuf->addr; | |
1468 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1469 | ||
1470 | if (GET_H_PRBIT ()) { | |
1471 | { | |
1472 | BI opval = sh64_fcmpeqd (current_cpu, GET_H_DR (FLD (f_rm)), GET_H_DR (FLD (f_rn))); | |
1473 | SET_H_TBIT (opval); | |
1474 | written |= (1 << 7); | |
1475 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); | |
1476 | } | |
1477 | } else { | |
1478 | { | |
1479 | BI opval = sh64_fcmpeqs (current_cpu, GET_H_FRC (FLD (f_rm)), GET_H_FRC (FLD (f_rn))); | |
1480 | SET_H_TBIT (opval); | |
1481 | written |= (1 << 7); | |
1482 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); | |
1483 | } | |
1484 | } | |
1485 | ||
1486 | abuf->written = written; | |
1487 | #undef FLD | |
1488 | } | |
1489 | NEXT (vpc); | |
1490 | ||
1491 | CASE (sem, INSN_FCMPGT_COMPACT) : /* fcmp/gt $fsdm, $fsdn */ | |
1492 | { | |
1493 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1494 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1495 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
1496 | int UNUSED written = 0; | |
1497 | IADDR UNUSED pc = abuf->addr; | |
1498 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1499 | ||
1500 | if (GET_H_PRBIT ()) { | |
1501 | { | |
1502 | BI opval = sh64_fcmpgtd (current_cpu, GET_H_DR (FLD (f_rn)), GET_H_DR (FLD (f_rm))); | |
1503 | SET_H_TBIT (opval); | |
1504 | written |= (1 << 7); | |
1505 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); | |
1506 | } | |
1507 | } else { | |
1508 | { | |
1509 | BI opval = sh64_fcmpgts (current_cpu, GET_H_FRC (FLD (f_rn)), GET_H_FRC (FLD (f_rm))); | |
1510 | SET_H_TBIT (opval); | |
1511 | written |= (1 << 7); | |
1512 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); | |
1513 | } | |
1514 | } | |
1515 | ||
1516 | abuf->written = written; | |
1517 | #undef FLD | |
1518 | } | |
1519 | NEXT (vpc); | |
1520 | ||
1521 | CASE (sem, INSN_FCNVDS_COMPACT) : /* fcnvds $drn, fpul */ | |
1522 | { | |
1523 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1524 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1525 | #define FLD(f) abuf->fields.sfmt_fcnvds_compact.f | |
1526 | int UNUSED written = 0; | |
1527 | IADDR UNUSED pc = abuf->addr; | |
1528 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1529 | ||
1530 | { | |
1531 | SF opval = sh64_fcnvds (current_cpu, GET_H_DRC (FLD (f_dn))); | |
1532 | CPU (h_fr[((UINT) 32)]) = opval; | |
1533 | TRACE_RESULT (current_cpu, abuf, "fpul", 'f', opval); | |
1534 | } | |
1535 | ||
1536 | #undef FLD | |
1537 | } | |
1538 | NEXT (vpc); | |
1539 | ||
1540 | CASE (sem, INSN_FCNVSD_COMPACT) : /* fcnvsd fpul, $drn */ | |
1541 | { | |
1542 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1543 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1544 | #define FLD(f) abuf->fields.sfmt_fcnvds_compact.f | |
1545 | int UNUSED written = 0; | |
1546 | IADDR UNUSED pc = abuf->addr; | |
1547 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1548 | ||
1549 | { | |
1550 | DF opval = sh64_fcnvsd (current_cpu, CPU (h_fr[((UINT) 32)])); | |
1551 | SET_H_DRC (FLD (f_dn), opval); | |
1552 | TRACE_RESULT (current_cpu, abuf, "drn", 'f', opval); | |
1553 | } | |
1554 | ||
1555 | #undef FLD | |
1556 | } | |
1557 | NEXT (vpc); | |
1558 | ||
1559 | CASE (sem, INSN_FDIV_COMPACT) : /* fdiv $fsdm, $fsdn */ | |
1560 | { | |
1561 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1562 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1563 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
1564 | int UNUSED written = 0; | |
1565 | IADDR UNUSED pc = abuf->addr; | |
1566 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1567 | ||
1568 | if (GET_H_PRBIT ()) { | |
1569 | { | |
1570 | DF opval = sh64_fdivd (current_cpu, GET_H_DR (FLD (f_rn)), GET_H_DR (FLD (f_rm))); | |
1571 | SET_H_DR (FLD (f_rn), opval); | |
1572 | written |= (1 << 8); | |
1573 | TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval); | |
1574 | } | |
1575 | } else { | |
1576 | { | |
1577 | SF opval = sh64_fdivs (current_cpu, GET_H_FRC (FLD (f_rn)), GET_H_FRC (FLD (f_rm))); | |
1578 | SET_H_FRC (FLD (f_rn), opval); | |
1579 | written |= (1 << 7); | |
1580 | TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval); | |
1581 | } | |
1582 | } | |
1583 | ||
1584 | abuf->written = written; | |
1585 | #undef FLD | |
1586 | } | |
1587 | NEXT (vpc); | |
1588 | ||
1589 | CASE (sem, INSN_FIPR_COMPACT) : /* fipr $fvm, $fvn */ | |
1590 | { | |
1591 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1592 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1593 | #define FLD(f) abuf->fields.sfmt_fipr_compact.f | |
1594 | int UNUSED written = 0; | |
1595 | IADDR UNUSED pc = abuf->addr; | |
1596 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1597 | ||
1598 | { | |
1599 | QI tmp_m; | |
1600 | QI tmp_n; | |
1601 | SF tmp_res; | |
1602 | tmp_m = FLD (f_vm); | |
1603 | tmp_n = FLD (f_vn); | |
1604 | tmp_res = sh64_fmuls (current_cpu, GET_H_FVC (FLD (f_vm)), GET_H_FVC (FLD (f_vn))); | |
1605 | tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_FRC (ADDQI (tmp_m, 1)), GET_H_FRC (ADDQI (tmp_n, 1)))); | |
1606 | tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_FRC (ADDQI (tmp_m, 2)), GET_H_FRC (ADDQI (tmp_n, 2)))); | |
1607 | tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_FRC (ADDQI (tmp_m, 3)), GET_H_FRC (ADDQI (tmp_n, 3)))); | |
1608 | { | |
1609 | SF opval = tmp_res; | |
1610 | SET_H_FRC (ADDQI (tmp_n, 3), opval); | |
1611 | TRACE_RESULT (current_cpu, abuf, "frc-add--DFLT-n-3", 'f', opval); | |
1612 | } | |
1613 | } | |
1614 | ||
1615 | #undef FLD | |
1616 | } | |
1617 | NEXT (vpc); | |
1618 | ||
1619 | CASE (sem, INSN_FLDS_COMPACT) : /* flds $frn */ | |
1620 | { | |
1621 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1622 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1623 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
1624 | int UNUSED written = 0; | |
1625 | IADDR UNUSED pc = abuf->addr; | |
1626 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1627 | ||
1628 | { | |
1629 | SF opval = GET_H_FRC (FLD (f_rn)); | |
1630 | CPU (h_fr[((UINT) 32)]) = opval; | |
1631 | TRACE_RESULT (current_cpu, abuf, "fpul", 'f', opval); | |
1632 | } | |
1633 | ||
1634 | #undef FLD | |
1635 | } | |
1636 | NEXT (vpc); | |
1637 | ||
1638 | CASE (sem, INSN_FLDI0_COMPACT) : /* fldi0 $frn */ | |
1639 | { | |
1640 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1641 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1642 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
1643 | int UNUSED written = 0; | |
1644 | IADDR UNUSED pc = abuf->addr; | |
1645 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1646 | ||
1647 | { | |
1648 | SF opval = sh64_fldi0 (current_cpu); | |
1649 | SET_H_FRC (FLD (f_rn), opval); | |
1650 | TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval); | |
1651 | } | |
1652 | ||
1653 | #undef FLD | |
1654 | } | |
1655 | NEXT (vpc); | |
1656 | ||
1657 | CASE (sem, INSN_FLDI1_COMPACT) : /* fldi1 $frn */ | |
1658 | { | |
1659 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1660 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1661 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
1662 | int UNUSED written = 0; | |
1663 | IADDR UNUSED pc = abuf->addr; | |
1664 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1665 | ||
1666 | { | |
1667 | SF opval = sh64_fldi1 (current_cpu); | |
1668 | SET_H_FRC (FLD (f_rn), opval); | |
1669 | TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval); | |
1670 | } | |
1671 | ||
1672 | #undef FLD | |
1673 | } | |
1674 | NEXT (vpc); | |
1675 | ||
1676 | CASE (sem, INSN_FLOAT_COMPACT) : /* float fpul, $fsdn */ | |
1677 | { | |
1678 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1679 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1680 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
1681 | int UNUSED written = 0; | |
1682 | IADDR UNUSED pc = abuf->addr; | |
1683 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1684 | ||
1685 | if (GET_H_PRBIT ()) { | |
1686 | { | |
1687 | DF opval = sh64_floatld (current_cpu, CPU (h_fr[((UINT) 32)])); | |
1688 | SET_H_DR (FLD (f_rn), opval); | |
1689 | written |= (1 << 4); | |
1690 | TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval); | |
1691 | } | |
1692 | } else { | |
1693 | { | |
1694 | SF opval = sh64_floatls (current_cpu, CPU (h_fr[((UINT) 32)])); | |
1695 | SET_H_FRC (FLD (f_rn), opval); | |
1696 | written |= (1 << 3); | |
1697 | TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval); | |
1698 | } | |
1699 | } | |
1700 | ||
1701 | abuf->written = written; | |
1702 | #undef FLD | |
1703 | } | |
1704 | NEXT (vpc); | |
1705 | ||
1706 | CASE (sem, INSN_FMAC_COMPACT) : /* fmac fr0, $frm, $frn */ | |
1707 | { | |
1708 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1709 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1710 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
1711 | int UNUSED written = 0; | |
1712 | IADDR UNUSED pc = abuf->addr; | |
1713 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1714 | ||
1715 | { | |
1716 | SF opval = sh64_fmacs (current_cpu, GET_H_FRC (((UINT) 0)), GET_H_FRC (FLD (f_rm)), GET_H_FRC (FLD (f_rn))); | |
1717 | SET_H_FRC (FLD (f_rn), opval); | |
1718 | TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval); | |
1719 | } | |
1720 | ||
1721 | #undef FLD | |
1722 | } | |
1723 | NEXT (vpc); | |
1724 | ||
1725 | CASE (sem, INSN_FMOV1_COMPACT) : /* fmov $frm, $frn */ | |
1726 | { | |
1727 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1728 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1729 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
1730 | int UNUSED written = 0; | |
1731 | IADDR UNUSED pc = abuf->addr; | |
1732 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1733 | ||
1734 | if (NOTBI (GET_H_SZBIT ())) { | |
1735 | { | |
1736 | SF opval = GET_H_FRC (FLD (f_rm)); | |
1737 | SET_H_FRC (FLD (f_rn), opval); | |
1738 | written |= (1 << 6); | |
1739 | TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval); | |
1740 | } | |
1741 | } else { | |
1742 | if (EQSI (ANDSI (FLD (f_rm), 1), 1)) { | |
1743 | if (EQSI (ANDSI (FLD (f_rn), 1), 1)) { | |
1744 | { | |
1745 | DF opval = GET_H_XD (((FLD (f_rm)) & (INVQI (1)))); | |
1746 | SET_H_XD (((FLD (f_rn)) & (INVQI (1))), opval); | |
1747 | written |= (1 << 8); | |
1748 | TRACE_RESULT (current_cpu, abuf, "xd-and--DFLT-index-of--DFLT-frn-inv--QI-1", 'f', opval); | |
1749 | } | |
1750 | } else { | |
1751 | { | |
1752 | DF opval = GET_H_XD (((FLD (f_rm)) & (INVQI (1)))); | |
1753 | SET_H_DR (FLD (f_rn), opval); | |
1754 | written |= (1 << 7); | |
1755 | TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-frn", 'f', opval); | |
1756 | } | |
1757 | } | |
1758 | } else { | |
1759 | if (EQSI (ANDSI (FLD (f_rn), 1), 1)) { | |
1760 | { | |
1761 | DF opval = GET_H_DR (FLD (f_rm)); | |
1762 | SET_H_XD (((FLD (f_rn)) & (INVQI (1))), opval); | |
1763 | written |= (1 << 8); | |
1764 | TRACE_RESULT (current_cpu, abuf, "xd-and--DFLT-index-of--DFLT-frn-inv--QI-1", 'f', opval); | |
1765 | } | |
1766 | } else { | |
1767 | { | |
1768 | DF opval = GET_H_DR (FLD (f_rm)); | |
1769 | SET_H_DR (FLD (f_rn), opval); | |
1770 | written |= (1 << 7); | |
1771 | TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-frn", 'f', opval); | |
1772 | } | |
1773 | } | |
1774 | } | |
1775 | } | |
1776 | ||
1777 | abuf->written = written; | |
1778 | #undef FLD | |
1779 | } | |
1780 | NEXT (vpc); | |
1781 | ||
1782 | CASE (sem, INSN_FMOV2_COMPACT) : /* fmov @$rm, $frn */ | |
1783 | { | |
1784 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1785 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1786 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
1787 | int UNUSED written = 0; | |
1788 | IADDR UNUSED pc = abuf->addr; | |
1789 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1790 | ||
1791 | if (NOTBI (GET_H_SZBIT ())) { | |
1792 | { | |
1793 | SF opval = GETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rm))); | |
1794 | SET_H_FRC (FLD (f_rn), opval); | |
1795 | written |= (1 << 5); | |
1796 | TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval); | |
1797 | } | |
1798 | } else { | |
1799 | if (EQSI (ANDSI (FLD (f_rn), 1), 1)) { | |
1800 | { | |
1801 | DF opval = GETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rm))); | |
1802 | SET_H_XD (((FLD (f_rn)) & (INVQI (1))), opval); | |
1803 | written |= (1 << 7); | |
1804 | TRACE_RESULT (current_cpu, abuf, "xd-and--DFLT-index-of--DFLT-frn-inv--QI-1", 'f', opval); | |
1805 | } | |
1806 | } else { | |
1807 | { | |
1808 | DF opval = GETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rm))); | |
1809 | SET_H_DR (FLD (f_rn), opval); | |
1810 | written |= (1 << 6); | |
1811 | TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-frn", 'f', opval); | |
1812 | } | |
1813 | } | |
1814 | } | |
1815 | ||
1816 | abuf->written = written; | |
1817 | #undef FLD | |
1818 | } | |
1819 | NEXT (vpc); | |
1820 | ||
1821 | CASE (sem, INSN_FMOV3_COMPACT) : /* fmov @${rm}+, frn */ | |
1822 | { | |
1823 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1824 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1825 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
1826 | int UNUSED written = 0; | |
1827 | IADDR UNUSED pc = abuf->addr; | |
1828 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1829 | ||
1830 | if (NOTBI (GET_H_SZBIT ())) { | |
1831 | { | |
1832 | { | |
1833 | SF opval = GETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rm))); | |
1834 | SET_H_FRC (FLD (f_rn), opval); | |
1835 | written |= (1 << 5); | |
1836 | TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval); | |
1837 | } | |
1838 | { | |
1839 | SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 4); | |
1840 | SET_H_GRC (FLD (f_rm), opval); | |
1841 | written |= (1 << 8); | |
1842 | TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval); | |
1843 | } | |
1844 | } | |
1845 | } else { | |
1846 | { | |
1847 | if (EQSI (ANDSI (FLD (f_rn), 1), 1)) { | |
1848 | { | |
1849 | DF opval = GETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rm))); | |
1850 | SET_H_XD (((FLD (f_rn)) & (INVQI (1))), opval); | |
1851 | written |= (1 << 7); | |
1852 | TRACE_RESULT (current_cpu, abuf, "xd-and--DFLT-index-of--DFLT-frn-inv--QI-1", 'f', opval); | |
1853 | } | |
1854 | } else { | |
1855 | { | |
1856 | DF opval = GETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rm))); | |
1857 | SET_H_DR (FLD (f_rn), opval); | |
1858 | written |= (1 << 6); | |
1859 | TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-frn", 'f', opval); | |
1860 | } | |
1861 | } | |
1862 | { | |
1863 | SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 8); | |
1864 | SET_H_GRC (FLD (f_rm), opval); | |
1865 | written |= (1 << 8); | |
1866 | TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval); | |
1867 | } | |
1868 | } | |
1869 | } | |
1870 | ||
1871 | abuf->written = written; | |
1872 | #undef FLD | |
1873 | } | |
1874 | NEXT (vpc); | |
1875 | ||
1876 | CASE (sem, INSN_FMOV4_COMPACT) : /* fmov @(r0, $rm), $frn */ | |
1877 | { | |
1878 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1879 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1880 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
1881 | int UNUSED written = 0; | |
1882 | IADDR UNUSED pc = abuf->addr; | |
1883 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1884 | ||
1885 | if (NOTBI (GET_H_SZBIT ())) { | |
1886 | { | |
1887 | SF opval = GETMEMSF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm)))); | |
1888 | SET_H_FRC (FLD (f_rn), opval); | |
1889 | written |= (1 << 6); | |
1890 | TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval); | |
1891 | } | |
1892 | } else { | |
1893 | if (EQSI (ANDSI (FLD (f_rn), 1), 1)) { | |
1894 | { | |
1895 | DF opval = GETMEMDF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm)))); | |
1896 | SET_H_XD (((FLD (f_rn)) & (INVQI (1))), opval); | |
1897 | written |= (1 << 8); | |
1898 | TRACE_RESULT (current_cpu, abuf, "xd-and--DFLT-index-of--DFLT-frn-inv--QI-1", 'f', opval); | |
1899 | } | |
1900 | } else { | |
1901 | { | |
1902 | DF opval = GETMEMDF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm)))); | |
1903 | SET_H_DR (FLD (f_rn), opval); | |
1904 | written |= (1 << 7); | |
1905 | TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-frn", 'f', opval); | |
1906 | } | |
1907 | } | |
1908 | } | |
1909 | ||
1910 | abuf->written = written; | |
1911 | #undef FLD | |
1912 | } | |
1913 | NEXT (vpc); | |
1914 | ||
1915 | CASE (sem, INSN_FMOV5_COMPACT) : /* fmov $frm, @$rn */ | |
1916 | { | |
1917 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1918 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1919 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
1920 | int UNUSED written = 0; | |
1921 | IADDR UNUSED pc = abuf->addr; | |
1922 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1923 | ||
1924 | if (NOTBI (GET_H_SZBIT ())) { | |
1925 | { | |
1926 | SF opval = GET_H_FRC (FLD (f_rm)); | |
1927 | SETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval); | |
1928 | written |= (1 << 6); | |
1929 | TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); | |
1930 | } | |
1931 | } else { | |
1932 | if (EQSI (ANDSI (FLD (f_rm), 1), 1)) { | |
1933 | { | |
1934 | DF opval = GET_H_XD (((FLD (f_rm)) & (INVQI (1)))); | |
1935 | SETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval); | |
1936 | written |= (1 << 7); | |
1937 | TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); | |
1938 | } | |
1939 | } else { | |
1940 | { | |
1941 | DF opval = GET_H_DR (FLD (f_rm)); | |
1942 | SETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval); | |
1943 | written |= (1 << 7); | |
1944 | TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); | |
1945 | } | |
1946 | } | |
1947 | } | |
1948 | ||
1949 | abuf->written = written; | |
1950 | #undef FLD | |
1951 | } | |
1952 | NEXT (vpc); | |
1953 | ||
1954 | CASE (sem, INSN_FMOV6_COMPACT) : /* fmov $frm, @-$rn */ | |
1955 | { | |
1956 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1957 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1958 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
1959 | int UNUSED written = 0; | |
1960 | IADDR UNUSED pc = abuf->addr; | |
1961 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1962 | ||
1963 | if (NOTBI (GET_H_SZBIT ())) { | |
1964 | { | |
1965 | { | |
1966 | SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), 4); | |
1967 | SET_H_GRC (FLD (f_rn), opval); | |
1968 | written |= (1 << 8); | |
1969 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
1970 | } | |
1971 | { | |
1972 | SF opval = GET_H_FRC (FLD (f_rm)); | |
1973 | SETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval); | |
1974 | written |= (1 << 6); | |
1975 | TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); | |
1976 | } | |
1977 | } | |
1978 | } else { | |
1979 | { | |
1980 | { | |
1981 | SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), 8); | |
1982 | SET_H_GRC (FLD (f_rn), opval); | |
1983 | written |= (1 << 8); | |
1984 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
1985 | } | |
1986 | if (EQSI (ANDSI (FLD (f_rm), 1), 1)) { | |
1987 | { | |
1988 | DF opval = GET_H_XD (((FLD (f_rm)) & (INVQI (1)))); | |
1989 | SETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval); | |
1990 | written |= (1 << 7); | |
1991 | TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); | |
1992 | } | |
1993 | } else { | |
1994 | { | |
1995 | DF opval = GET_H_DR (FLD (f_rm)); | |
1996 | SETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval); | |
1997 | written |= (1 << 7); | |
1998 | TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); | |
1999 | } | |
2000 | } | |
2001 | } | |
2002 | } | |
2003 | ||
2004 | abuf->written = written; | |
2005 | #undef FLD | |
2006 | } | |
2007 | NEXT (vpc); | |
2008 | ||
2009 | CASE (sem, INSN_FMOV7_COMPACT) : /* fmov $frm, @(r0, $rn) */ | |
2010 | { | |
2011 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2012 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2013 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
2014 | int UNUSED written = 0; | |
2015 | IADDR UNUSED pc = abuf->addr; | |
2016 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2017 | ||
2018 | if (NOTBI (GET_H_SZBIT ())) { | |
2019 | { | |
2020 | SF opval = GET_H_FRC (FLD (f_rm)); | |
2021 | SETMEMSF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval); | |
2022 | written |= (1 << 7); | |
2023 | TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); | |
2024 | } | |
2025 | } else { | |
2026 | if (EQSI (ANDSI (FLD (f_rm), 1), 1)) { | |
2027 | { | |
2028 | DF opval = GET_H_XD (((FLD (f_rm)) & (INVQI (1)))); | |
2029 | SETMEMDF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval); | |
2030 | written |= (1 << 8); | |
2031 | TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); | |
2032 | } | |
2033 | } else { | |
2034 | { | |
2035 | DF opval = GET_H_DR (FLD (f_rm)); | |
2036 | SETMEMDF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval); | |
2037 | written |= (1 << 8); | |
2038 | TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); | |
2039 | } | |
2040 | } | |
2041 | } | |
2042 | ||
2043 | abuf->written = written; | |
2044 | #undef FLD | |
2045 | } | |
2046 | NEXT (vpc); | |
2047 | ||
2048 | CASE (sem, INSN_FMUL_COMPACT) : /* fmul $fsdm, $fsdn */ | |
2049 | { | |
2050 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2051 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2052 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
2053 | int UNUSED written = 0; | |
2054 | IADDR UNUSED pc = abuf->addr; | |
2055 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2056 | ||
2057 | if (GET_H_PRBIT ()) { | |
2058 | { | |
2059 | DF opval = sh64_fmuld (current_cpu, GET_H_DR (FLD (f_rm)), GET_H_DR (FLD (f_rn))); | |
2060 | SET_H_DR (FLD (f_rn), opval); | |
2061 | written |= (1 << 8); | |
2062 | TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval); | |
2063 | } | |
2064 | } else { | |
2065 | { | |
2066 | SF opval = sh64_fmuls (current_cpu, GET_H_FRC (FLD (f_rm)), GET_H_FRC (FLD (f_rn))); | |
2067 | SET_H_FRC (FLD (f_rn), opval); | |
2068 | written |= (1 << 7); | |
2069 | TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval); | |
2070 | } | |
2071 | } | |
2072 | ||
2073 | abuf->written = written; | |
2074 | #undef FLD | |
2075 | } | |
2076 | NEXT (vpc); | |
2077 | ||
2078 | CASE (sem, INSN_FNEG_COMPACT) : /* fneg $fsdn */ | |
2079 | { | |
2080 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2081 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2082 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
2083 | int UNUSED written = 0; | |
2084 | IADDR UNUSED pc = abuf->addr; | |
2085 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2086 | ||
2087 | if (GET_H_PRBIT ()) { | |
2088 | { | |
2089 | DF opval = sh64_fnegd (current_cpu, GET_H_DR (FLD (f_rn))); | |
2090 | SET_H_DR (FLD (f_rn), opval); | |
2091 | written |= (1 << 5); | |
2092 | TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval); | |
2093 | } | |
2094 | } else { | |
2095 | { | |
2096 | SF opval = sh64_fnegs (current_cpu, GET_H_FRC (FLD (f_rn))); | |
2097 | SET_H_FRC (FLD (f_rn), opval); | |
2098 | written |= (1 << 4); | |
2099 | TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval); | |
2100 | } | |
2101 | } | |
2102 | ||
2103 | abuf->written = written; | |
2104 | #undef FLD | |
2105 | } | |
2106 | NEXT (vpc); | |
2107 | ||
2108 | CASE (sem, INSN_FRCHG_COMPACT) : /* frchg */ | |
2109 | { | |
2110 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2111 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2112 | #define FLD(f) abuf->fields.fmt_empty.f | |
2113 | int UNUSED written = 0; | |
2114 | IADDR UNUSED pc = abuf->addr; | |
2115 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2116 | ||
2117 | { | |
2118 | BI opval = NOTBI (GET_H_FRBIT ()); | |
2119 | SET_H_FRBIT (opval); | |
2120 | TRACE_RESULT (current_cpu, abuf, "frbit", 'x', opval); | |
2121 | } | |
2122 | ||
2123 | #undef FLD | |
2124 | } | |
2125 | NEXT (vpc); | |
2126 | ||
2127 | CASE (sem, INSN_FSCHG_COMPACT) : /* fschg */ | |
2128 | { | |
2129 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2130 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2131 | #define FLD(f) abuf->fields.fmt_empty.f | |
2132 | int UNUSED written = 0; | |
2133 | IADDR UNUSED pc = abuf->addr; | |
2134 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2135 | ||
2136 | { | |
2137 | BI opval = NOTBI (GET_H_SZBIT ()); | |
2138 | SET_H_SZBIT (opval); | |
2139 | TRACE_RESULT (current_cpu, abuf, "szbit", 'x', opval); | |
2140 | } | |
2141 | ||
2142 | #undef FLD | |
2143 | } | |
2144 | NEXT (vpc); | |
2145 | ||
2146 | CASE (sem, INSN_FSQRT_COMPACT) : /* fsqrt $fsdn */ | |
2147 | { | |
2148 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2149 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2150 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
2151 | int UNUSED written = 0; | |
2152 | IADDR UNUSED pc = abuf->addr; | |
2153 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2154 | ||
2155 | if (GET_H_PRBIT ()) { | |
2156 | { | |
2157 | DF opval = sh64_fsqrtd (current_cpu, GET_H_DR (FLD (f_rn))); | |
2158 | SET_H_DR (FLD (f_rn), opval); | |
2159 | written |= (1 << 5); | |
2160 | TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval); | |
2161 | } | |
2162 | } else { | |
2163 | { | |
2164 | SF opval = sh64_fsqrts (current_cpu, GET_H_FRC (FLD (f_rn))); | |
2165 | SET_H_FRC (FLD (f_rn), opval); | |
2166 | written |= (1 << 4); | |
2167 | TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval); | |
2168 | } | |
2169 | } | |
2170 | ||
2171 | abuf->written = written; | |
2172 | #undef FLD | |
2173 | } | |
2174 | NEXT (vpc); | |
2175 | ||
2176 | CASE (sem, INSN_FSTS_COMPACT) : /* fsts fpul, $frn */ | |
2177 | { | |
2178 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2179 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2180 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
2181 | int UNUSED written = 0; | |
2182 | IADDR UNUSED pc = abuf->addr; | |
2183 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2184 | ||
2185 | { | |
2186 | SF opval = CPU (h_fr[((UINT) 32)]); | |
2187 | SET_H_FRC (FLD (f_rn), opval); | |
2188 | TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval); | |
2189 | } | |
2190 | ||
2191 | #undef FLD | |
2192 | } | |
2193 | NEXT (vpc); | |
2194 | ||
2195 | CASE (sem, INSN_FSUB_COMPACT) : /* fsub $fsdm, $fsdn */ | |
2196 | { | |
2197 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2198 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2199 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
2200 | int UNUSED written = 0; | |
2201 | IADDR UNUSED pc = abuf->addr; | |
2202 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2203 | ||
2204 | if (GET_H_PRBIT ()) { | |
2205 | { | |
2206 | DF opval = sh64_fsubd (current_cpu, GET_H_DR (FLD (f_rn)), GET_H_DR (FLD (f_rm))); | |
2207 | SET_H_DR (FLD (f_rn), opval); | |
2208 | written |= (1 << 8); | |
2209 | TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval); | |
2210 | } | |
2211 | } else { | |
2212 | { | |
2213 | SF opval = sh64_fsubs (current_cpu, GET_H_FRC (FLD (f_rn)), GET_H_FRC (FLD (f_rm))); | |
2214 | SET_H_FRC (FLD (f_rn), opval); | |
2215 | written |= (1 << 7); | |
2216 | TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval); | |
2217 | } | |
2218 | } | |
2219 | ||
2220 | abuf->written = written; | |
2221 | #undef FLD | |
2222 | } | |
2223 | NEXT (vpc); | |
2224 | ||
2225 | CASE (sem, INSN_FTRC_COMPACT) : /* ftrc $fsdn, fpul */ | |
2226 | { | |
2227 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2228 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2229 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
2230 | int UNUSED written = 0; | |
2231 | IADDR UNUSED pc = abuf->addr; | |
2232 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2233 | ||
2234 | { | |
2235 | SF opval = ((GET_H_PRBIT ()) ? (sh64_ftrcdl (current_cpu, GET_H_DR (FLD (f_rn)))) : (sh64_ftrcsl (current_cpu, GET_H_FRC (FLD (f_rn))))); | |
2236 | CPU (h_fr[((UINT) 32)]) = opval; | |
2237 | TRACE_RESULT (current_cpu, abuf, "fpul", 'f', opval); | |
2238 | } | |
2239 | ||
2240 | #undef FLD | |
2241 | } | |
2242 | NEXT (vpc); | |
2243 | ||
2244 | CASE (sem, INSN_FTRV_COMPACT) : /* ftrv xmtrx, $fvn */ | |
2245 | { | |
2246 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2247 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2248 | #define FLD(f) abuf->fields.sfmt_fipr_compact.f | |
2249 | int UNUSED written = 0; | |
2250 | IADDR UNUSED pc = abuf->addr; | |
2251 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2252 | ||
2253 | { | |
2254 | QI tmp_n; | |
2255 | SF tmp_res; | |
2256 | tmp_n = FLD (f_vn); | |
2257 | tmp_res = sh64_fmuls (current_cpu, GET_H_XF (((UINT) 0)), GET_H_FRC (tmp_n)); | |
2258 | tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 4)), GET_H_FRC (ADDQI (tmp_n, 1)))); | |
2259 | tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 8)), GET_H_FRC (ADDQI (tmp_n, 2)))); | |
2260 | tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 12)), GET_H_FRC (ADDQI (tmp_n, 3)))); | |
2261 | { | |
2262 | SF opval = tmp_res; | |
2263 | SET_H_FRC (tmp_n, opval); | |
2264 | TRACE_RESULT (current_cpu, abuf, "frc-n", 'f', opval); | |
2265 | } | |
2266 | tmp_res = sh64_fmuls (current_cpu, GET_H_XF (((UINT) 1)), GET_H_FRC (tmp_n)); | |
2267 | tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 5)), GET_H_FRC (ADDQI (tmp_n, 1)))); | |
2268 | tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 9)), GET_H_FRC (ADDQI (tmp_n, 2)))); | |
2269 | tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 13)), GET_H_FRC (ADDQI (tmp_n, 3)))); | |
2270 | { | |
2271 | SF opval = tmp_res; | |
2272 | SET_H_FRC (ADDQI (tmp_n, 1), opval); | |
2273 | TRACE_RESULT (current_cpu, abuf, "frc-add--DFLT-n-1", 'f', opval); | |
2274 | } | |
2275 | tmp_res = sh64_fmuls (current_cpu, GET_H_XF (((UINT) 2)), GET_H_FRC (tmp_n)); | |
2276 | tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 6)), GET_H_FRC (ADDQI (tmp_n, 1)))); | |
2277 | tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 10)), GET_H_FRC (ADDQI (tmp_n, 2)))); | |
2278 | tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 14)), GET_H_FRC (ADDQI (tmp_n, 3)))); | |
2279 | { | |
2280 | SF opval = tmp_res; | |
2281 | SET_H_FRC (ADDQI (tmp_n, 2), opval); | |
2282 | TRACE_RESULT (current_cpu, abuf, "frc-add--DFLT-n-2", 'f', opval); | |
2283 | } | |
2284 | tmp_res = sh64_fmuls (current_cpu, GET_H_XF (((UINT) 3)), GET_H_FRC (tmp_n)); | |
2285 | tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 7)), GET_H_FRC (ADDQI (tmp_n, 1)))); | |
2286 | tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 11)), GET_H_FRC (ADDQI (tmp_n, 2)))); | |
2287 | tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 15)), GET_H_FRC (ADDQI (tmp_n, 3)))); | |
2288 | { | |
2289 | SF opval = tmp_res; | |
2290 | SET_H_FRC (ADDQI (tmp_n, 3), opval); | |
2291 | TRACE_RESULT (current_cpu, abuf, "frc-add--DFLT-n-3", 'f', opval); | |
2292 | } | |
2293 | } | |
2294 | ||
2295 | #undef FLD | |
2296 | } | |
2297 | NEXT (vpc); | |
2298 | ||
2299 | CASE (sem, INSN_JMP_COMPACT) : /* jmp @$rn */ | |
2300 | { | |
2301 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2302 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2303 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
2304 | int UNUSED written = 0; | |
2305 | IADDR UNUSED pc = abuf->addr; | |
2306 | SEM_BRANCH_INIT | |
2307 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2308 | ||
2309 | { | |
2310 | { | |
2311 | UDI opval = GET_H_GRC (FLD (f_rn)); | |
2312 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); | |
2313 | TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); | |
2314 | } | |
2315 | } | |
2316 | ||
2317 | SEM_BRANCH_FINI (vpc); | |
2318 | #undef FLD | |
2319 | } | |
2320 | NEXT (vpc); | |
2321 | ||
2322 | CASE (sem, INSN_JSR_COMPACT) : /* jsr @$rn */ | |
2323 | { | |
2324 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2325 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2326 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
2327 | int UNUSED written = 0; | |
2328 | IADDR UNUSED pc = abuf->addr; | |
2329 | SEM_BRANCH_INIT | |
2330 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2331 | ||
2332 | { | |
2333 | { | |
2334 | { | |
2335 | SI opval = ADDDI (pc, 4); | |
2336 | SET_H_PR (opval); | |
2337 | TRACE_RESULT (current_cpu, abuf, "pr", 'x', opval); | |
2338 | } | |
2339 | { | |
2340 | UDI opval = GET_H_GRC (FLD (f_rn)); | |
2341 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); | |
2342 | TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); | |
2343 | } | |
2344 | } | |
2345 | } | |
2346 | ||
2347 | SEM_BRANCH_FINI (vpc); | |
2348 | #undef FLD | |
2349 | } | |
2350 | NEXT (vpc); | |
2351 | ||
2352 | CASE (sem, INSN_LDC_COMPACT) : /* ldc $rn, gbr */ | |
2353 | { | |
2354 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2355 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2356 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
2357 | int UNUSED written = 0; | |
2358 | IADDR UNUSED pc = abuf->addr; | |
2359 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2360 | ||
2361 | { | |
2362 | SI opval = GET_H_GRC (FLD (f_rn)); | |
2363 | SET_H_GBR (opval); | |
2364 | TRACE_RESULT (current_cpu, abuf, "gbr", 'x', opval); | |
2365 | } | |
2366 | ||
2367 | #undef FLD | |
2368 | } | |
2369 | NEXT (vpc); | |
2370 | ||
2371 | CASE (sem, INSN_LDCL_COMPACT) : /* ldc.l @${rn}+, gbr */ | |
2372 | { | |
2373 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2374 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2375 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
2376 | int UNUSED written = 0; | |
2377 | IADDR UNUSED pc = abuf->addr; | |
2378 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2379 | ||
2380 | { | |
2381 | { | |
2382 | SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn))); | |
2383 | SET_H_GBR (opval); | |
2384 | TRACE_RESULT (current_cpu, abuf, "gbr", 'x', opval); | |
2385 | } | |
2386 | { | |
2387 | SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4); | |
2388 | SET_H_GRC (FLD (f_rn), opval); | |
2389 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
2390 | } | |
2391 | } | |
2392 | ||
2393 | #undef FLD | |
2394 | } | |
2395 | NEXT (vpc); | |
2396 | ||
2397 | CASE (sem, INSN_LDS_FPSCR_COMPACT) : /* lds $rn, fpscr */ | |
2398 | { | |
2399 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2400 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2401 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
2402 | int UNUSED written = 0; | |
2403 | IADDR UNUSED pc = abuf->addr; | |
2404 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2405 | ||
2406 | { | |
2407 | SI opval = GET_H_GRC (FLD (f_rn)); | |
2408 | SET_H_FPCCR (opval); | |
2409 | TRACE_RESULT (current_cpu, abuf, "fpscr", 'x', opval); | |
2410 | } | |
2411 | ||
2412 | #undef FLD | |
2413 | } | |
2414 | NEXT (vpc); | |
2415 | ||
2416 | CASE (sem, INSN_LDSL_FPSCR_COMPACT) : /* lds.l @${rn}+, fpscr */ | |
2417 | { | |
2418 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2419 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2420 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
2421 | int UNUSED written = 0; | |
2422 | IADDR UNUSED pc = abuf->addr; | |
2423 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2424 | ||
2425 | { | |
2426 | { | |
2427 | SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn))); | |
2428 | SET_H_FPCCR (opval); | |
2429 | TRACE_RESULT (current_cpu, abuf, "fpscr", 'x', opval); | |
2430 | } | |
2431 | { | |
2432 | SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4); | |
2433 | SET_H_GRC (FLD (f_rn), opval); | |
2434 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
2435 | } | |
2436 | } | |
2437 | ||
2438 | #undef FLD | |
2439 | } | |
2440 | NEXT (vpc); | |
2441 | ||
2442 | CASE (sem, INSN_LDS_FPUL_COMPACT) : /* lds $rn, fpul */ | |
2443 | { | |
2444 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2445 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2446 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
2447 | int UNUSED written = 0; | |
2448 | IADDR UNUSED pc = abuf->addr; | |
2449 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2450 | ||
2451 | { | |
2452 | SF opval = SUBWORDSISF (GET_H_GRC (FLD (f_rn))); | |
2453 | CPU (h_fr[((UINT) 32)]) = opval; | |
2454 | TRACE_RESULT (current_cpu, abuf, "fpul", 'f', opval); | |
2455 | } | |
2456 | ||
2457 | #undef FLD | |
2458 | } | |
2459 | NEXT (vpc); | |
2460 | ||
2461 | CASE (sem, INSN_LDSL_FPUL_COMPACT) : /* lds.l @${rn}+, fpul */ | |
2462 | { | |
2463 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2464 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2465 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
2466 | int UNUSED written = 0; | |
2467 | IADDR UNUSED pc = abuf->addr; | |
2468 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2469 | ||
2470 | { | |
2471 | { | |
2472 | SF opval = GETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rn))); | |
2473 | CPU (h_fr[((UINT) 32)]) = opval; | |
2474 | TRACE_RESULT (current_cpu, abuf, "fpul", 'f', opval); | |
2475 | } | |
2476 | { | |
2477 | SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4); | |
2478 | SET_H_GRC (FLD (f_rn), opval); | |
2479 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
2480 | } | |
2481 | } | |
2482 | ||
2483 | #undef FLD | |
2484 | } | |
2485 | NEXT (vpc); | |
2486 | ||
2487 | CASE (sem, INSN_LDS_MACH_COMPACT) : /* lds $rn, mach */ | |
2488 | { | |
2489 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2490 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2491 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
2492 | int UNUSED written = 0; | |
2493 | IADDR UNUSED pc = abuf->addr; | |
2494 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2495 | ||
2496 | { | |
2497 | SI opval = GET_H_GRC (FLD (f_rn)); | |
2498 | SET_H_MACH (opval); | |
2499 | TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval); | |
2500 | } | |
2501 | ||
2502 | #undef FLD | |
2503 | } | |
2504 | NEXT (vpc); | |
2505 | ||
2506 | CASE (sem, INSN_LDSL_MACH_COMPACT) : /* lds.l @${rn}+, mach */ | |
2507 | { | |
2508 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2509 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2510 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
2511 | int UNUSED written = 0; | |
2512 | IADDR UNUSED pc = abuf->addr; | |
2513 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2514 | ||
2515 | { | |
2516 | { | |
2517 | SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn))); | |
2518 | SET_H_MACH (opval); | |
2519 | TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval); | |
2520 | } | |
2521 | { | |
2522 | SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4); | |
2523 | SET_H_GRC (FLD (f_rn), opval); | |
2524 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
2525 | } | |
2526 | } | |
2527 | ||
2528 | #undef FLD | |
2529 | } | |
2530 | NEXT (vpc); | |
2531 | ||
2532 | CASE (sem, INSN_LDS_MACL_COMPACT) : /* lds $rn, macl */ | |
2533 | { | |
2534 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2535 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2536 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
2537 | int UNUSED written = 0; | |
2538 | IADDR UNUSED pc = abuf->addr; | |
2539 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2540 | ||
2541 | { | |
2542 | SI opval = GET_H_GRC (FLD (f_rn)); | |
2543 | SET_H_MACL (opval); | |
2544 | TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval); | |
2545 | } | |
2546 | ||
2547 | #undef FLD | |
2548 | } | |
2549 | NEXT (vpc); | |
2550 | ||
2551 | CASE (sem, INSN_LDSL_MACL_COMPACT) : /* lds.l @${rn}+, macl */ | |
2552 | { | |
2553 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2554 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2555 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
2556 | int UNUSED written = 0; | |
2557 | IADDR UNUSED pc = abuf->addr; | |
2558 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2559 | ||
2560 | { | |
2561 | { | |
2562 | SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn))); | |
2563 | SET_H_MACL (opval); | |
2564 | TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval); | |
2565 | } | |
2566 | { | |
2567 | SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4); | |
2568 | SET_H_GRC (FLD (f_rn), opval); | |
2569 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
2570 | } | |
2571 | } | |
2572 | ||
2573 | #undef FLD | |
2574 | } | |
2575 | NEXT (vpc); | |
2576 | ||
2577 | CASE (sem, INSN_LDS_PR_COMPACT) : /* lds $rn, pr */ | |
2578 | { | |
2579 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2580 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2581 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
2582 | int UNUSED written = 0; | |
2583 | IADDR UNUSED pc = abuf->addr; | |
2584 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2585 | ||
2586 | { | |
2587 | SI opval = GET_H_GRC (FLD (f_rn)); | |
2588 | SET_H_PR (opval); | |
2589 | TRACE_RESULT (current_cpu, abuf, "pr", 'x', opval); | |
2590 | } | |
2591 | ||
2592 | #undef FLD | |
2593 | } | |
2594 | NEXT (vpc); | |
2595 | ||
2596 | CASE (sem, INSN_LDSL_PR_COMPACT) : /* lds.l @${rn}+, pr */ | |
2597 | { | |
2598 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2599 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2600 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
2601 | int UNUSED written = 0; | |
2602 | IADDR UNUSED pc = abuf->addr; | |
2603 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2604 | ||
2605 | { | |
2606 | { | |
2607 | SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn))); | |
2608 | SET_H_PR (opval); | |
2609 | TRACE_RESULT (current_cpu, abuf, "pr", 'x', opval); | |
2610 | } | |
2611 | { | |
2612 | SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4); | |
2613 | SET_H_GRC (FLD (f_rn), opval); | |
2614 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
2615 | } | |
2616 | } | |
2617 | ||
2618 | #undef FLD | |
2619 | } | |
2620 | NEXT (vpc); | |
2621 | ||
2622 | CASE (sem, INSN_MACL_COMPACT) : /* mac.l @${rm}+, @${rn}+ */ | |
2623 | { | |
2624 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2625 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2626 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
2627 | int UNUSED written = 0; | |
2628 | IADDR UNUSED pc = abuf->addr; | |
2629 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2630 | ||
2631 | { | |
2632 | DI tmp_tmpry; | |
2633 | DI tmp_mac; | |
2634 | DI tmp_result; | |
2635 | SI tmp_x; | |
2636 | SI tmp_y; | |
2637 | tmp_x = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn))); | |
2638 | { | |
2639 | SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4); | |
2640 | SET_H_GRC (FLD (f_rn), opval); | |
2641 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
2642 | } | |
2643 | if (EQSI (FLD (f_rn), FLD (f_rm))) { | |
2644 | { | |
2645 | { | |
2646 | SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4); | |
2647 | SET_H_GRC (FLD (f_rn), opval); | |
2648 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
2649 | } | |
2650 | { | |
2651 | SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 4); | |
2652 | SET_H_GRC (FLD (f_rm), opval); | |
2653 | written |= (1 << 11); | |
2654 | TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval); | |
2655 | } | |
2656 | } | |
2657 | } | |
2658 | tmp_y = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rm))); | |
2659 | { | |
2660 | SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 4); | |
2661 | SET_H_GRC (FLD (f_rm), opval); | |
2662 | written |= (1 << 11); | |
2663 | TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval); | |
2664 | } | |
2665 | tmp_tmpry = MULDI (ZEXTSIDI (tmp_x), ZEXTSIDI (tmp_y)); | |
2666 | tmp_mac = ORDI (SLLDI (ZEXTSIDI (GET_H_MACH ()), 32), ZEXTSIDI (GET_H_MACL ())); | |
2667 | tmp_result = ADDDI (tmp_mac, tmp_tmpry); | |
2668 | { | |
2669 | if (GET_H_SBIT ()) { | |
2670 | { | |
2671 | SI tmp_min; | |
2672 | SI tmp_max; | |
2673 | tmp_max = SRLDI (INVDI (0), 16); | |
2674 | tmp_min = SRLDI (INVDI (0), 15); | |
2675 | if (GTDI (tmp_result, tmp_max)) { | |
2676 | tmp_result = tmp_max; | |
2677 | } else { | |
2678 | if (LTDI (tmp_result, tmp_min)) { | |
2679 | tmp_result = tmp_min; | |
2680 | } | |
2681 | } | |
2682 | } | |
2683 | } | |
2684 | { | |
2685 | SI opval = SUBWORDDISI (tmp_result, 0); | |
2686 | SET_H_MACH (opval); | |
2687 | TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval); | |
2688 | } | |
2689 | { | |
2690 | SI opval = SUBWORDDISI (tmp_result, 1); | |
2691 | SET_H_MACL (opval); | |
2692 | TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval); | |
2693 | } | |
2694 | } | |
2695 | } | |
2696 | ||
2697 | abuf->written = written; | |
2698 | #undef FLD | |
2699 | } | |
2700 | NEXT (vpc); | |
2701 | ||
2702 | CASE (sem, INSN_MACW_COMPACT) : /* mac.w @${rm}+, @${rn}+ */ | |
2703 | { | |
2704 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2705 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2706 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
2707 | int UNUSED written = 0; | |
2708 | IADDR UNUSED pc = abuf->addr; | |
2709 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2710 | ||
2711 | { | |
2712 | SI tmp_tmpry; | |
2713 | DI tmp_mac; | |
2714 | DI tmp_result; | |
2715 | HI tmp_x; | |
2716 | HI tmp_y; | |
2717 | tmp_x = GETMEMHI (current_cpu, pc, GET_H_GRC (FLD (f_rn))); | |
2718 | { | |
2719 | SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 2); | |
2720 | SET_H_GRC (FLD (f_rn), opval); | |
2721 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
2722 | } | |
2723 | if (EQSI (FLD (f_rn), FLD (f_rm))) { | |
2724 | { | |
2725 | { | |
2726 | SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 2); | |
2727 | SET_H_GRC (FLD (f_rn), opval); | |
2728 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
2729 | } | |
2730 | { | |
2731 | SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 2); | |
2732 | SET_H_GRC (FLD (f_rm), opval); | |
2733 | written |= (1 << 11); | |
2734 | TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval); | |
2735 | } | |
2736 | } | |
2737 | } | |
2738 | tmp_y = GETMEMHI (current_cpu, pc, GET_H_GRC (FLD (f_rm))); | |
2739 | { | |
2740 | SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 2); | |
2741 | SET_H_GRC (FLD (f_rm), opval); | |
2742 | written |= (1 << 11); | |
2743 | TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval); | |
2744 | } | |
2745 | tmp_tmpry = MULSI (ZEXTHISI (tmp_x), ZEXTHISI (tmp_y)); | |
2746 | if (GET_H_SBIT ()) { | |
2747 | { | |
2748 | if (ADDOFSI (tmp_tmpry, GET_H_MACL (), 0)) { | |
2749 | { | |
2750 | SI opval = 1; | |
2751 | SET_H_MACH (opval); | |
2752 | written |= (1 << 9); | |
2753 | TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval); | |
2754 | } | |
2755 | } | |
2756 | { | |
2757 | SI opval = ADDSI (tmp_tmpry, GET_H_MACL ()); | |
2758 | SET_H_MACL (opval); | |
2759 | written |= (1 << 10); | |
2760 | TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval); | |
2761 | } | |
2762 | } | |
2763 | } else { | |
2764 | { | |
2765 | tmp_mac = ORDI (SLLDI (ZEXTSIDI (GET_H_MACH ()), 32), ZEXTSIDI (GET_H_MACL ())); | |
2766 | tmp_result = ADDDI (tmp_mac, EXTSIDI (tmp_tmpry)); | |
2767 | { | |
2768 | SI opval = SUBWORDDISI (tmp_result, 0); | |
2769 | SET_H_MACH (opval); | |
2770 | written |= (1 << 9); | |
2771 | TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval); | |
2772 | } | |
2773 | { | |
2774 | SI opval = SUBWORDDISI (tmp_result, 1); | |
2775 | SET_H_MACL (opval); | |
2776 | written |= (1 << 10); | |
2777 | TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval); | |
2778 | } | |
2779 | } | |
2780 | } | |
2781 | } | |
2782 | ||
2783 | abuf->written = written; | |
2784 | #undef FLD | |
2785 | } | |
2786 | NEXT (vpc); | |
2787 | ||
2788 | CASE (sem, INSN_MOV_COMPACT) : /* mov $rm64, $rn64 */ | |
2789 | { | |
2790 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2791 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2792 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
2793 | int UNUSED written = 0; | |
2794 | IADDR UNUSED pc = abuf->addr; | |
2795 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2796 | ||
2797 | { | |
2798 | DI opval = GET_H_GR (FLD (f_rm)); | |
2799 | SET_H_GR (FLD (f_rn), opval); | |
2800 | TRACE_RESULT (current_cpu, abuf, "rn64", 'D', opval); | |
2801 | } | |
2802 | ||
2803 | #undef FLD | |
2804 | } | |
2805 | NEXT (vpc); | |
2806 | ||
2807 | CASE (sem, INSN_MOVI_COMPACT) : /* mov #$imm8, $rn */ | |
2808 | { | |
2809 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2810 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2811 | #define FLD(f) abuf->fields.sfmt_addi_compact.f | |
2812 | int UNUSED written = 0; | |
2813 | IADDR UNUSED pc = abuf->addr; | |
2814 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2815 | ||
2816 | { | |
2817 | SI opval = EXTQIDI (ANDQI (FLD (f_imm8), 255)); | |
2818 | SET_H_GRC (FLD (f_rn), opval); | |
2819 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
2820 | } | |
2821 | ||
2822 | #undef FLD | |
2823 | } | |
2824 | NEXT (vpc); | |
2825 | ||
2826 | CASE (sem, INSN_MOVB1_COMPACT) : /* mov.b $rm, @$rn */ | |
2827 | { | |
2828 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2829 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2830 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
2831 | int UNUSED written = 0; | |
2832 | IADDR UNUSED pc = abuf->addr; | |
2833 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2834 | ||
2835 | { | |
2836 | UQI opval = SUBWORDSIUQI (GET_H_GRC (FLD (f_rm)), 3); | |
2837 | SETMEMUQI (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval); | |
2838 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
2839 | } | |
2840 | ||
2841 | #undef FLD | |
2842 | } | |
2843 | NEXT (vpc); | |
2844 | ||
2845 | CASE (sem, INSN_MOVB2_COMPACT) : /* mov.b $rm, @-$rn */ | |
2846 | { | |
2847 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2848 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2849 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
2850 | int UNUSED written = 0; | |
2851 | IADDR UNUSED pc = abuf->addr; | |
2852 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2853 | ||
2854 | { | |
2855 | DI tmp_addr; | |
2856 | tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 1); | |
2857 | { | |
2858 | UQI opval = SUBWORDSIUQI (GET_H_GRC (FLD (f_rm)), 3); | |
2859 | SETMEMUQI (current_cpu, pc, tmp_addr, opval); | |
2860 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
2861 | } | |
2862 | { | |
2863 | SI opval = tmp_addr; | |
2864 | SET_H_GRC (FLD (f_rn), opval); | |
2865 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
2866 | } | |
2867 | } | |
2868 | ||
2869 | #undef FLD | |
2870 | } | |
2871 | NEXT (vpc); | |
2872 | ||
2873 | CASE (sem, INSN_MOVB3_COMPACT) : /* mov.b $rm, @(r0,$rn) */ | |
2874 | { | |
2875 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2876 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2877 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
2878 | int UNUSED written = 0; | |
2879 | IADDR UNUSED pc = abuf->addr; | |
2880 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2881 | ||
2882 | { | |
2883 | UQI opval = SUBWORDSIUQI (GET_H_GRC (FLD (f_rm)), 3); | |
2884 | SETMEMUQI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval); | |
2885 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
2886 | } | |
2887 | ||
2888 | #undef FLD | |
2889 | } | |
2890 | NEXT (vpc); | |
2891 | ||
2892 | CASE (sem, INSN_MOVB4_COMPACT) : /* mov.b r0, @($imm8, gbr) */ | |
2893 | { | |
2894 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2895 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2896 | #define FLD(f) abuf->fields.sfmt_addi_compact.f | |
2897 | int UNUSED written = 0; | |
2898 | IADDR UNUSED pc = abuf->addr; | |
2899 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2900 | ||
2901 | { | |
2902 | DI tmp_addr; | |
2903 | tmp_addr = ADDSI (GET_H_GBR (), FLD (f_imm8)); | |
2904 | { | |
2905 | UQI opval = SUBWORDSIUQI (GET_H_GRC (((UINT) 0)), 3); | |
2906 | SETMEMUQI (current_cpu, pc, tmp_addr, opval); | |
2907 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
2908 | } | |
2909 | } | |
2910 | ||
2911 | #undef FLD | |
2912 | } | |
2913 | NEXT (vpc); | |
2914 | ||
2915 | CASE (sem, INSN_MOVB5_COMPACT) : /* mov.b r0, @($imm4, $rm) */ | |
2916 | { | |
2917 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2918 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2919 | #define FLD(f) abuf->fields.sfmt_movb5_compact.f | |
2920 | int UNUSED written = 0; | |
2921 | IADDR UNUSED pc = abuf->addr; | |
2922 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2923 | ||
2924 | { | |
2925 | DI tmp_addr; | |
2926 | tmp_addr = ADDSI (GET_H_GRC (FLD (f_rm)), FLD (f_imm4)); | |
2927 | { | |
2928 | UQI opval = SUBWORDSIUQI (GET_H_GRC (((UINT) 0)), 3); | |
2929 | SETMEMUQI (current_cpu, pc, tmp_addr, opval); | |
2930 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
2931 | } | |
2932 | } | |
2933 | ||
2934 | #undef FLD | |
2935 | } | |
2936 | NEXT (vpc); | |
2937 | ||
2938 | CASE (sem, INSN_MOVB6_COMPACT) : /* mov.b @$rm, $rn */ | |
2939 | { | |
2940 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2941 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2942 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
2943 | int UNUSED written = 0; | |
2944 | IADDR UNUSED pc = abuf->addr; | |
2945 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2946 | ||
2947 | { | |
2948 | SI opval = EXTQISI (GETMEMQI (current_cpu, pc, GET_H_GRC (FLD (f_rm)))); | |
2949 | SET_H_GRC (FLD (f_rn), opval); | |
2950 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
2951 | } | |
2952 | ||
2953 | #undef FLD | |
2954 | } | |
2955 | NEXT (vpc); | |
2956 | ||
2957 | CASE (sem, INSN_MOVB7_COMPACT) : /* mov.b @${rm}+, $rn */ | |
2958 | { | |
2959 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2960 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2961 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
2962 | int UNUSED written = 0; | |
2963 | IADDR UNUSED pc = abuf->addr; | |
2964 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2965 | ||
2966 | { | |
2967 | QI tmp_data; | |
2968 | tmp_data = GETMEMQI (current_cpu, pc, GET_H_GRC (FLD (f_rm))); | |
2969 | if (EQSI (FLD (f_rm), FLD (f_rn))) { | |
2970 | { | |
2971 | SI opval = EXTQISI (tmp_data); | |
2972 | SET_H_GRC (FLD (f_rm), opval); | |
2973 | written |= (1 << 4); | |
2974 | TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval); | |
2975 | } | |
2976 | } else { | |
2977 | { | |
2978 | SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 1); | |
2979 | SET_H_GRC (FLD (f_rm), opval); | |
2980 | written |= (1 << 4); | |
2981 | TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval); | |
2982 | } | |
2983 | } | |
2984 | { | |
2985 | SI opval = EXTQISI (tmp_data); | |
2986 | SET_H_GRC (FLD (f_rn), opval); | |
2987 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
2988 | } | |
2989 | } | |
2990 | ||
2991 | abuf->written = written; | |
2992 | #undef FLD | |
2993 | } | |
2994 | NEXT (vpc); | |
2995 | ||
2996 | CASE (sem, INSN_MOVB8_COMPACT) : /* mov.b @(r0, $rm), $rn */ | |
2997 | { | |
2998 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2999 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3000 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
3001 | int UNUSED written = 0; | |
3002 | IADDR UNUSED pc = abuf->addr; | |
3003 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3004 | ||
3005 | { | |
3006 | SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm))))); | |
3007 | SET_H_GRC (FLD (f_rn), opval); | |
3008 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
3009 | } | |
3010 | ||
3011 | #undef FLD | |
3012 | } | |
3013 | NEXT (vpc); | |
3014 | ||
3015 | CASE (sem, INSN_MOVB9_COMPACT) : /* mov.b @($imm8, gbr), r0 */ | |
3016 | { | |
3017 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3018 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3019 | #define FLD(f) abuf->fields.sfmt_addi_compact.f | |
3020 | int UNUSED written = 0; | |
3021 | IADDR UNUSED pc = abuf->addr; | |
3022 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3023 | ||
3024 | { | |
3025 | SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (GET_H_GBR (), FLD (f_imm8)))); | |
3026 | SET_H_GRC (((UINT) 0), opval); | |
3027 | TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval); | |
3028 | } | |
3029 | ||
3030 | #undef FLD | |
3031 | } | |
3032 | NEXT (vpc); | |
3033 | ||
3034 | CASE (sem, INSN_MOVB10_COMPACT) : /* mov.b @($imm4, $rm), r0 */ | |
3035 | { | |
3036 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3037 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3038 | #define FLD(f) abuf->fields.sfmt_movb5_compact.f | |
3039 | int UNUSED written = 0; | |
3040 | IADDR UNUSED pc = abuf->addr; | |
3041 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3042 | ||
3043 | { | |
3044 | SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rm)), FLD (f_imm4)))); | |
3045 | SET_H_GRC (((UINT) 0), opval); | |
3046 | TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval); | |
3047 | } | |
3048 | ||
3049 | #undef FLD | |
3050 | } | |
3051 | NEXT (vpc); | |
3052 | ||
3053 | CASE (sem, INSN_MOVL1_COMPACT) : /* mov.l $rm, @$rn */ | |
3054 | { | |
3055 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3056 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3057 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
3058 | int UNUSED written = 0; | |
3059 | IADDR UNUSED pc = abuf->addr; | |
3060 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3061 | ||
3062 | { | |
3063 | SI opval = GET_H_GRC (FLD (f_rm)); | |
3064 | SETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval); | |
3065 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
3066 | } | |
3067 | ||
3068 | #undef FLD | |
3069 | } | |
3070 | NEXT (vpc); | |
3071 | ||
3072 | CASE (sem, INSN_MOVL2_COMPACT) : /* mov.l $rm, @-$rn */ | |
3073 | { | |
3074 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3075 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3076 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
3077 | int UNUSED written = 0; | |
3078 | IADDR UNUSED pc = abuf->addr; | |
3079 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3080 | ||
3081 | { | |
3082 | SI tmp_addr; | |
3083 | tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4); | |
3084 | { | |
3085 | SI opval = GET_H_GRC (FLD (f_rm)); | |
3086 | SETMEMSI (current_cpu, pc, tmp_addr, opval); | |
3087 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
3088 | } | |
3089 | { | |
3090 | SI opval = tmp_addr; | |
3091 | SET_H_GRC (FLD (f_rn), opval); | |
3092 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
3093 | } | |
3094 | } | |
3095 | ||
3096 | #undef FLD | |
3097 | } | |
3098 | NEXT (vpc); | |
3099 | ||
3100 | CASE (sem, INSN_MOVL3_COMPACT) : /* mov.l $rm, @(r0, $rn) */ | |
3101 | { | |
3102 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3103 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3104 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
3105 | int UNUSED written = 0; | |
3106 | IADDR UNUSED pc = abuf->addr; | |
3107 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3108 | ||
3109 | { | |
3110 | SI opval = GET_H_GRC (FLD (f_rm)); | |
3111 | SETMEMSI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval); | |
3112 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
3113 | } | |
3114 | ||
3115 | #undef FLD | |
3116 | } | |
3117 | NEXT (vpc); | |
3118 | ||
3119 | CASE (sem, INSN_MOVL4_COMPACT) : /* mov.l r0, @($imm8x4, gbr) */ | |
3120 | { | |
3121 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3122 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3123 | #define FLD(f) abuf->fields.sfmt_movl10_compact.f | |
3124 | int UNUSED written = 0; | |
3125 | IADDR UNUSED pc = abuf->addr; | |
3126 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3127 | ||
3128 | { | |
3129 | SI opval = GET_H_GRC (((UINT) 0)); | |
3130 | SETMEMSI (current_cpu, pc, ADDSI (GET_H_GBR (), FLD (f_imm8x4)), opval); | |
3131 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
3132 | } | |
3133 | ||
3134 | #undef FLD | |
3135 | } | |
3136 | NEXT (vpc); | |
3137 | ||
3138 | CASE (sem, INSN_MOVL5_COMPACT) : /* mov.l $rm, @($imm4x4, $rn) */ | |
3139 | { | |
3140 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3141 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3142 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
3143 | int UNUSED written = 0; | |
3144 | IADDR UNUSED pc = abuf->addr; | |
3145 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3146 | ||
3147 | { | |
3148 | SI opval = GET_H_GRC (FLD (f_rm)); | |
3149 | SETMEMSI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rn)), FLD (f_imm4x4)), opval); | |
3150 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
3151 | } | |
3152 | ||
3153 | #undef FLD | |
3154 | } | |
3155 | NEXT (vpc); | |
3156 | ||
3157 | CASE (sem, INSN_MOVL6_COMPACT) : /* mov.l @$rm, $rn */ | |
3158 | { | |
3159 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3160 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3161 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
3162 | int UNUSED written = 0; | |
3163 | IADDR UNUSED pc = abuf->addr; | |
3164 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3165 | ||
3166 | { | |
3167 | SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rm))); | |
3168 | SET_H_GRC (FLD (f_rn), opval); | |
3169 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
3170 | } | |
3171 | ||
3172 | #undef FLD | |
3173 | } | |
3174 | NEXT (vpc); | |
3175 | ||
3176 | CASE (sem, INSN_MOVL7_COMPACT) : /* mov.l @${rm}+, $rn */ | |
3177 | { | |
3178 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3179 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3180 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
3181 | int UNUSED written = 0; | |
3182 | IADDR UNUSED pc = abuf->addr; | |
3183 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3184 | ||
3185 | { | |
3186 | { | |
3187 | SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rm))); | |
3188 | SET_H_GRC (FLD (f_rn), opval); | |
3189 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
3190 | } | |
3191 | if (EQSI (FLD (f_rm), FLD (f_rn))) { | |
3192 | { | |
3193 | SI opval = GET_H_GRC (FLD (f_rn)); | |
3194 | SET_H_GRC (FLD (f_rm), opval); | |
3195 | written |= (1 << 5); | |
3196 | TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval); | |
3197 | } | |
3198 | } else { | |
3199 | { | |
3200 | SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 4); | |
3201 | SET_H_GRC (FLD (f_rm), opval); | |
3202 | written |= (1 << 5); | |
3203 | TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval); | |
3204 | } | |
3205 | } | |
3206 | } | |
3207 | ||
3208 | abuf->written = written; | |
3209 | #undef FLD | |
3210 | } | |
3211 | NEXT (vpc); | |
3212 | ||
3213 | CASE (sem, INSN_MOVL8_COMPACT) : /* mov.l @(r0, $rm), $rn */ | |
3214 | { | |
3215 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3216 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3217 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
3218 | int UNUSED written = 0; | |
3219 | IADDR UNUSED pc = abuf->addr; | |
3220 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3221 | ||
3222 | { | |
3223 | SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm)))); | |
3224 | SET_H_GRC (FLD (f_rn), opval); | |
3225 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
3226 | } | |
3227 | ||
3228 | #undef FLD | |
3229 | } | |
3230 | NEXT (vpc); | |
3231 | ||
3232 | CASE (sem, INSN_MOVL9_COMPACT) : /* mov.l @($imm8x4, gbr), r0 */ | |
3233 | { | |
3234 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3235 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3236 | #define FLD(f) abuf->fields.sfmt_movl10_compact.f | |
3237 | int UNUSED written = 0; | |
3238 | IADDR UNUSED pc = abuf->addr; | |
3239 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3240 | ||
3241 | { | |
3242 | SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GBR (), FLD (f_imm8x4))); | |
3243 | SET_H_GRC (((UINT) 0), opval); | |
3244 | TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval); | |
3245 | } | |
3246 | ||
3247 | #undef FLD | |
3248 | } | |
3249 | NEXT (vpc); | |
3250 | ||
3251 | CASE (sem, INSN_MOVL10_COMPACT) : /* mov.l @($imm8x4, pc), $rn */ | |
3252 | { | |
3253 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3254 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3255 | #define FLD(f) abuf->fields.sfmt_movl10_compact.f | |
3256 | int UNUSED written = 0; | |
3257 | IADDR UNUSED pc = abuf->addr; | |
3258 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3259 | ||
3260 | { | |
3261 | SI opval = GETMEMSI (current_cpu, pc, ADDSI (FLD (f_imm8x4), ANDDI (ADDDI (pc, 4), INVSI (3)))); | |
3262 | SET_H_GRC (FLD (f_rn), opval); | |
3263 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
3264 | } | |
3265 | ||
3266 | #undef FLD | |
3267 | } | |
3268 | NEXT (vpc); | |
3269 | ||
3270 | CASE (sem, INSN_MOVL11_COMPACT) : /* mov.l @($imm4x4, $rm), $rn */ | |
3271 | { | |
3272 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3273 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3274 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
3275 | int UNUSED written = 0; | |
3276 | IADDR UNUSED pc = abuf->addr; | |
3277 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3278 | ||
3279 | { | |
3280 | SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rm)), FLD (f_imm4x4))); | |
3281 | SET_H_GRC (FLD (f_rn), opval); | |
3282 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
3283 | } | |
3284 | ||
3285 | #undef FLD | |
3286 | } | |
3287 | NEXT (vpc); | |
3288 | ||
3289 | CASE (sem, INSN_MOVW1_COMPACT) : /* mov.w $rm, @$rn */ | |
3290 | { | |
3291 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3292 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3293 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
3294 | int UNUSED written = 0; | |
3295 | IADDR UNUSED pc = abuf->addr; | |
3296 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3297 | ||
3298 | { | |
3299 | HI opval = SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1); | |
3300 | SETMEMHI (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval); | |
3301 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
3302 | } | |
3303 | ||
3304 | #undef FLD | |
3305 | } | |
3306 | NEXT (vpc); | |
3307 | ||
3308 | CASE (sem, INSN_MOVW2_COMPACT) : /* mov.w $rm, @-$rn */ | |
3309 | { | |
3310 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3311 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3312 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
3313 | int UNUSED written = 0; | |
3314 | IADDR UNUSED pc = abuf->addr; | |
3315 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3316 | ||
3317 | { | |
3318 | DI tmp_addr; | |
3319 | tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 2); | |
3320 | { | |
3321 | HI opval = SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1); | |
3322 | SETMEMHI (current_cpu, pc, tmp_addr, opval); | |
3323 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
3324 | } | |
3325 | { | |
3326 | SI opval = tmp_addr; | |
3327 | SET_H_GRC (FLD (f_rn), opval); | |
3328 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
3329 | } | |
3330 | } | |
3331 | ||
3332 | #undef FLD | |
3333 | } | |
3334 | NEXT (vpc); | |
3335 | ||
3336 | CASE (sem, INSN_MOVW3_COMPACT) : /* mov.w $rm, @(r0, $rn) */ | |
3337 | { | |
3338 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3339 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3340 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
3341 | int UNUSED written = 0; | |
3342 | IADDR UNUSED pc = abuf->addr; | |
3343 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3344 | ||
3345 | { | |
3346 | HI opval = SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1); | |
3347 | SETMEMHI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval); | |
3348 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
3349 | } | |
3350 | ||
3351 | #undef FLD | |
3352 | } | |
3353 | NEXT (vpc); | |
3354 | ||
3355 | CASE (sem, INSN_MOVW4_COMPACT) : /* mov.w r0, @($imm8x2, gbr) */ | |
3356 | { | |
3357 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3358 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3359 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
3360 | int UNUSED written = 0; | |
3361 | IADDR UNUSED pc = abuf->addr; | |
3362 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3363 | ||
3364 | { | |
3365 | HI opval = SUBWORDSIHI (GET_H_GRC (((UINT) 0)), 1); | |
3366 | SETMEMHI (current_cpu, pc, ADDSI (GET_H_GBR (), FLD (f_imm8x2)), opval); | |
3367 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
3368 | } | |
3369 | ||
3370 | #undef FLD | |
3371 | } | |
3372 | NEXT (vpc); | |
3373 | ||
3374 | CASE (sem, INSN_MOVW5_COMPACT) : /* mov.w r0, @($imm4x2, $rn) */ | |
3375 | { | |
3376 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3377 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3378 | #define FLD(f) abuf->fields.sfmt_movw5_compact.f | |
3379 | int UNUSED written = 0; | |
3380 | IADDR UNUSED pc = abuf->addr; | |
3381 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3382 | ||
3383 | { | |
3384 | HI opval = SUBWORDSIHI (GET_H_GRC (((UINT) 0)), 1); | |
3385 | SETMEMHI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rn)), FLD (f_imm4x2)), opval); | |
3386 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
3387 | } | |
3388 | ||
3389 | #undef FLD | |
3390 | } | |
3391 | NEXT (vpc); | |
3392 | ||
3393 | CASE (sem, INSN_MOVW6_COMPACT) : /* mov.w @$rm, $rn */ | |
3394 | { | |
3395 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3396 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3397 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
3398 | int UNUSED written = 0; | |
3399 | IADDR UNUSED pc = abuf->addr; | |
3400 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3401 | ||
3402 | { | |
3403 | SI opval = EXTHISI (GETMEMHI (current_cpu, pc, GET_H_GRC (FLD (f_rm)))); | |
3404 | SET_H_GRC (FLD (f_rn), opval); | |
3405 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
3406 | } | |
3407 | ||
3408 | #undef FLD | |
3409 | } | |
3410 | NEXT (vpc); | |
3411 | ||
3412 | CASE (sem, INSN_MOVW7_COMPACT) : /* mov.w @${rm}+, $rn */ | |
3413 | { | |
3414 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3415 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3416 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
3417 | int UNUSED written = 0; | |
3418 | IADDR UNUSED pc = abuf->addr; | |
3419 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3420 | ||
3421 | { | |
3422 | HI tmp_data; | |
3423 | tmp_data = GETMEMHI (current_cpu, pc, GET_H_GRC (FLD (f_rm))); | |
3424 | if (EQSI (FLD (f_rm), FLD (f_rn))) { | |
3425 | { | |
3426 | SI opval = EXTHISI (tmp_data); | |
3427 | SET_H_GRC (FLD (f_rm), opval); | |
3428 | written |= (1 << 4); | |
3429 | TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval); | |
3430 | } | |
3431 | } else { | |
3432 | { | |
3433 | SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 2); | |
3434 | SET_H_GRC (FLD (f_rm), opval); | |
3435 | written |= (1 << 4); | |
3436 | TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval); | |
3437 | } | |
3438 | } | |
3439 | { | |
3440 | SI opval = EXTHISI (tmp_data); | |
3441 | SET_H_GRC (FLD (f_rn), opval); | |
3442 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
3443 | } | |
3444 | } | |
3445 | ||
3446 | abuf->written = written; | |
3447 | #undef FLD | |
3448 | } | |
3449 | NEXT (vpc); | |
3450 | ||
3451 | CASE (sem, INSN_MOVW8_COMPACT) : /* mov.w @(r0, $rm), $rn */ | |
3452 | { | |
3453 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3454 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3455 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
3456 | int UNUSED written = 0; | |
3457 | IADDR UNUSED pc = abuf->addr; | |
3458 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3459 | ||
3460 | { | |
3461 | SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm))))); | |
3462 | SET_H_GRC (FLD (f_rn), opval); | |
3463 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
3464 | } | |
3465 | ||
3466 | #undef FLD | |
3467 | } | |
3468 | NEXT (vpc); | |
3469 | ||
3470 | CASE (sem, INSN_MOVW9_COMPACT) : /* mov.w @($imm8x2, gbr), r0 */ | |
3471 | { | |
3472 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3473 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3474 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
3475 | int UNUSED written = 0; | |
3476 | IADDR UNUSED pc = abuf->addr; | |
3477 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3478 | ||
3479 | { | |
3480 | SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (GET_H_GBR (), FLD (f_imm8x2)))); | |
3481 | SET_H_GRC (((UINT) 0), opval); | |
3482 | TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval); | |
3483 | } | |
3484 | ||
3485 | #undef FLD | |
3486 | } | |
3487 | NEXT (vpc); | |
3488 | ||
3489 | CASE (sem, INSN_MOVW10_COMPACT) : /* mov.w @($imm8x2, pc), $rn */ | |
3490 | { | |
3491 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3492 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3493 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
3494 | int UNUSED written = 0; | |
3495 | IADDR UNUSED pc = abuf->addr; | |
3496 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3497 | ||
3498 | { | |
3499 | SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDDI (ADDDI (pc, 4), FLD (f_imm8x2)))); | |
3500 | SET_H_GRC (FLD (f_rn), opval); | |
3501 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
3502 | } | |
3503 | ||
3504 | #undef FLD | |
3505 | } | |
3506 | NEXT (vpc); | |
3507 | ||
3508 | CASE (sem, INSN_MOVW11_COMPACT) : /* mov.w @($imm4x2, $rm), r0 */ | |
3509 | { | |
3510 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3511 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3512 | #define FLD(f) abuf->fields.sfmt_movw11_compact.f | |
3513 | int UNUSED written = 0; | |
3514 | IADDR UNUSED pc = abuf->addr; | |
3515 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3516 | ||
3517 | { | |
3518 | SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rm)), FLD (f_imm4x2)))); | |
3519 | SET_H_GRC (((UINT) 0), opval); | |
3520 | TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval); | |
3521 | } | |
3522 | ||
3523 | #undef FLD | |
3524 | } | |
3525 | NEXT (vpc); | |
3526 | ||
3527 | CASE (sem, INSN_MOVA_COMPACT) : /* mova @($imm8x4, pc), r0 */ | |
3528 | { | |
3529 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3530 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3531 | #define FLD(f) abuf->fields.sfmt_movl10_compact.f | |
3532 | int UNUSED written = 0; | |
3533 | IADDR UNUSED pc = abuf->addr; | |
3534 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3535 | ||
3536 | { | |
3537 | SI opval = ADDDI (ANDDI (ADDDI (pc, 4), INVSI (3)), FLD (f_imm8x4)); | |
3538 | SET_H_GRC (((UINT) 0), opval); | |
3539 | TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval); | |
3540 | } | |
3541 | ||
3542 | #undef FLD | |
3543 | } | |
3544 | NEXT (vpc); | |
3545 | ||
3546 | CASE (sem, INSN_MOVCAL_COMPACT) : /* movca.l r0, @$rn */ | |
3547 | { | |
3548 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3549 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3550 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
3551 | int UNUSED written = 0; | |
3552 | IADDR UNUSED pc = abuf->addr; | |
3553 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3554 | ||
3555 | { | |
3556 | SI opval = GET_H_GRC (((UINT) 0)); | |
3557 | SETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval); | |
3558 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
3559 | } | |
3560 | ||
3561 | #undef FLD | |
3562 | } | |
3563 | NEXT (vpc); | |
3564 | ||
3565 | CASE (sem, INSN_MOVT_COMPACT) : /* movt $rn */ | |
3566 | { | |
3567 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3568 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3569 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
3570 | int UNUSED written = 0; | |
3571 | IADDR UNUSED pc = abuf->addr; | |
3572 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3573 | ||
3574 | { | |
3575 | SI opval = ZEXTBISI (GET_H_TBIT ()); | |
3576 | SET_H_GRC (FLD (f_rn), opval); | |
3577 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
3578 | } | |
3579 | ||
3580 | #undef FLD | |
3581 | } | |
3582 | NEXT (vpc); | |
3583 | ||
3584 | CASE (sem, INSN_MULL_COMPACT) : /* mul.l $rm, $rn */ | |
3585 | { | |
3586 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3587 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3588 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
3589 | int UNUSED written = 0; | |
3590 | IADDR UNUSED pc = abuf->addr; | |
3591 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3592 | ||
3593 | { | |
3594 | SI opval = MULSI (GET_H_GRC (FLD (f_rm)), GET_H_GRC (FLD (f_rn))); | |
3595 | SET_H_MACL (opval); | |
3596 | TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval); | |
3597 | } | |
3598 | ||
3599 | #undef FLD | |
3600 | } | |
3601 | NEXT (vpc); | |
3602 | ||
3603 | CASE (sem, INSN_MULSW_COMPACT) : /* muls.w $rm, $rn */ | |
3604 | { | |
3605 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3606 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3607 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
3608 | int UNUSED written = 0; | |
3609 | IADDR UNUSED pc = abuf->addr; | |
3610 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3611 | ||
3612 | { | |
3613 | SI opval = MULSI (EXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1)), EXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rn)), 1))); | |
3614 | SET_H_MACL (opval); | |
3615 | TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval); | |
3616 | } | |
3617 | ||
3618 | #undef FLD | |
3619 | } | |
3620 | NEXT (vpc); | |
3621 | ||
3622 | CASE (sem, INSN_MULUW_COMPACT) : /* mulu.w $rm, $rn */ | |
3623 | { | |
3624 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3625 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3626 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
3627 | int UNUSED written = 0; | |
3628 | IADDR UNUSED pc = abuf->addr; | |
3629 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3630 | ||
3631 | { | |
3632 | SI opval = MULSI (ZEXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1)), ZEXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rn)), 1))); | |
3633 | SET_H_MACL (opval); | |
3634 | TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval); | |
3635 | } | |
3636 | ||
3637 | #undef FLD | |
3638 | } | |
3639 | NEXT (vpc); | |
3640 | ||
3641 | CASE (sem, INSN_NEG_COMPACT) : /* neg $rm, $rn */ | |
3642 | { | |
3643 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3644 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3645 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
3646 | int UNUSED written = 0; | |
3647 | IADDR UNUSED pc = abuf->addr; | |
3648 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3649 | ||
3650 | { | |
3651 | SI opval = NEGSI (GET_H_GRC (FLD (f_rm))); | |
3652 | SET_H_GRC (FLD (f_rn), opval); | |
3653 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
3654 | } | |
3655 | ||
3656 | #undef FLD | |
3657 | } | |
3658 | NEXT (vpc); | |
3659 | ||
3660 | CASE (sem, INSN_NEGC_COMPACT) : /* negc $rm, $rn */ | |
3661 | { | |
3662 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3663 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3664 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
3665 | int UNUSED written = 0; | |
3666 | IADDR UNUSED pc = abuf->addr; | |
3667 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3668 | ||
3669 | { | |
3670 | BI tmp_flag; | |
3671 | tmp_flag = SUBCFSI (0, GET_H_GRC (FLD (f_rm)), GET_H_TBIT ()); | |
3672 | { | |
3673 | SI opval = SUBCSI (0, GET_H_GRC (FLD (f_rm)), GET_H_TBIT ()); | |
3674 | SET_H_GRC (FLD (f_rn), opval); | |
3675 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
3676 | } | |
3677 | { | |
3678 | BI opval = tmp_flag; | |
3679 | SET_H_TBIT (opval); | |
3680 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); | |
3681 | } | |
3682 | } | |
3683 | ||
3684 | #undef FLD | |
3685 | } | |
3686 | NEXT (vpc); | |
3687 | ||
3688 | CASE (sem, INSN_NOP_COMPACT) : /* nop */ | |
3689 | { | |
3690 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3691 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3692 | #define FLD(f) abuf->fields.fmt_empty.f | |
3693 | int UNUSED written = 0; | |
3694 | IADDR UNUSED pc = abuf->addr; | |
3695 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3696 | ||
3697 | ((void) 0); /*nop*/ | |
3698 | ||
3699 | #undef FLD | |
3700 | } | |
3701 | NEXT (vpc); | |
3702 | ||
3703 | CASE (sem, INSN_NOT_COMPACT) : /* not $rm64, $rn64 */ | |
3704 | { | |
3705 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3706 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3707 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
3708 | int UNUSED written = 0; | |
3709 | IADDR UNUSED pc = abuf->addr; | |
3710 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3711 | ||
3712 | { | |
3713 | DI opval = INVDI (GET_H_GR (FLD (f_rm))); | |
3714 | SET_H_GR (FLD (f_rn), opval); | |
3715 | TRACE_RESULT (current_cpu, abuf, "rn64", 'D', opval); | |
3716 | } | |
3717 | ||
3718 | #undef FLD | |
3719 | } | |
3720 | NEXT (vpc); | |
3721 | ||
3722 | CASE (sem, INSN_OCBI_COMPACT) : /* ocbi @$rn */ | |
3723 | { | |
3724 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3725 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3726 | #define FLD(f) abuf->fields.fmt_empty.f | |
3727 | int UNUSED written = 0; | |
3728 | IADDR UNUSED pc = abuf->addr; | |
3729 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3730 | ||
3731 | ((void) 0); /*nop*/ | |
3732 | ||
3733 | #undef FLD | |
3734 | } | |
3735 | NEXT (vpc); | |
3736 | ||
3737 | CASE (sem, INSN_OCBP_COMPACT) : /* ocbp @$rn */ | |
3738 | { | |
3739 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3740 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3741 | #define FLD(f) abuf->fields.fmt_empty.f | |
3742 | int UNUSED written = 0; | |
3743 | IADDR UNUSED pc = abuf->addr; | |
3744 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3745 | ||
3746 | ((void) 0); /*nop*/ | |
3747 | ||
3748 | #undef FLD | |
3749 | } | |
3750 | NEXT (vpc); | |
3751 | ||
3752 | CASE (sem, INSN_OCBWB_COMPACT) : /* ocbwb @$rn */ | |
3753 | { | |
3754 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3755 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3756 | #define FLD(f) abuf->fields.fmt_empty.f | |
3757 | int UNUSED written = 0; | |
3758 | IADDR UNUSED pc = abuf->addr; | |
3759 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3760 | ||
3761 | ((void) 0); /*nop*/ | |
3762 | ||
3763 | #undef FLD | |
3764 | } | |
3765 | NEXT (vpc); | |
3766 | ||
3767 | CASE (sem, INSN_OR_COMPACT) : /* or $rm64, $rn64 */ | |
3768 | { | |
3769 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3770 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3771 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
3772 | int UNUSED written = 0; | |
3773 | IADDR UNUSED pc = abuf->addr; | |
3774 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3775 | ||
3776 | { | |
3777 | DI opval = ORDI (GET_H_GR (FLD (f_rm)), GET_H_GR (FLD (f_rn))); | |
3778 | SET_H_GR (FLD (f_rn), opval); | |
3779 | TRACE_RESULT (current_cpu, abuf, "rn64", 'D', opval); | |
3780 | } | |
3781 | ||
3782 | #undef FLD | |
3783 | } | |
3784 | NEXT (vpc); | |
3785 | ||
3786 | CASE (sem, INSN_ORI_COMPACT) : /* or #$uimm8, r0 */ | |
3787 | { | |
3788 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3789 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3790 | #define FLD(f) abuf->fields.sfmt_addi_compact.f | |
3791 | int UNUSED written = 0; | |
3792 | IADDR UNUSED pc = abuf->addr; | |
3793 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3794 | ||
3795 | { | |
3796 | SI opval = ORSI (GET_H_GRC (((UINT) 0)), ZEXTSIDI (FLD (f_imm8))); | |
3797 | SET_H_GRC (((UINT) 0), opval); | |
3798 | TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval); | |
3799 | } | |
3800 | ||
3801 | #undef FLD | |
3802 | } | |
3803 | NEXT (vpc); | |
3804 | ||
3805 | CASE (sem, INSN_ORB_COMPACT) : /* or.b #$imm8, @(r0, gbr) */ | |
3806 | { | |
3807 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3808 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3809 | #define FLD(f) abuf->fields.sfmt_addi_compact.f | |
3810 | int UNUSED written = 0; | |
3811 | IADDR UNUSED pc = abuf->addr; | |
3812 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3813 | ||
3814 | { | |
3815 | DI tmp_addr; | |
3816 | UQI tmp_data; | |
3817 | tmp_addr = ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GBR ()); | |
3818 | tmp_data = ORQI (GETMEMUQI (current_cpu, pc, tmp_addr), FLD (f_imm8)); | |
3819 | { | |
3820 | UQI opval = tmp_data; | |
3821 | SETMEMUQI (current_cpu, pc, tmp_addr, opval); | |
3822 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
3823 | } | |
3824 | } | |
3825 | ||
3826 | #undef FLD | |
3827 | } | |
3828 | NEXT (vpc); | |
3829 | ||
3830 | CASE (sem, INSN_PREF_COMPACT) : /* pref @$rn */ | |
3831 | { | |
3832 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3833 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3834 | #define FLD(f) abuf->fields.fmt_empty.f | |
3835 | int UNUSED written = 0; | |
3836 | IADDR UNUSED pc = abuf->addr; | |
3837 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3838 | ||
3839 | ((void) 0); /*nop*/ | |
3840 | ||
3841 | #undef FLD | |
3842 | } | |
3843 | NEXT (vpc); | |
3844 | ||
3845 | CASE (sem, INSN_ROTCL_COMPACT) : /* rotcl $rn */ | |
3846 | { | |
3847 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3848 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3849 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
3850 | int UNUSED written = 0; | |
3851 | IADDR UNUSED pc = abuf->addr; | |
3852 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3853 | ||
3854 | { | |
3855 | BI tmp_temp; | |
3856 | tmp_temp = SRLSI (GET_H_GRC (FLD (f_rn)), 31); | |
3857 | { | |
3858 | SI opval = ORSI (SLLSI (GET_H_GRC (FLD (f_rn)), 1), GET_H_TBIT ()); | |
3859 | SET_H_GRC (FLD (f_rn), opval); | |
3860 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
3861 | } | |
3862 | { | |
3863 | BI opval = ((tmp_temp) ? (1) : (0)); | |
3864 | SET_H_TBIT (opval); | |
3865 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); | |
3866 | } | |
3867 | } | |
3868 | ||
3869 | #undef FLD | |
3870 | } | |
3871 | NEXT (vpc); | |
3872 | ||
3873 | CASE (sem, INSN_ROTCR_COMPACT) : /* rotcr $rn */ | |
3874 | { | |
3875 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3876 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3877 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
3878 | int UNUSED written = 0; | |
3879 | IADDR UNUSED pc = abuf->addr; | |
3880 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3881 | ||
3882 | { | |
3883 | BI tmp_lsbit; | |
3884 | SI tmp_temp; | |
3885 | tmp_lsbit = ((EQSI (ANDSI (GET_H_GRC (FLD (f_rn)), 1), 0)) ? (0) : (1)); | |
3886 | tmp_temp = GET_H_TBIT (); | |
3887 | { | |
3888 | SI opval = ORSI (SRLSI (GET_H_GRC (FLD (f_rn)), 1), SLLSI (tmp_temp, 31)); | |
3889 | SET_H_GRC (FLD (f_rn), opval); | |
3890 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
3891 | } | |
3892 | { | |
3893 | BI opval = ((tmp_lsbit) ? (1) : (0)); | |
3894 | SET_H_TBIT (opval); | |
3895 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); | |
3896 | } | |
3897 | } | |
3898 | ||
3899 | #undef FLD | |
3900 | } | |
3901 | NEXT (vpc); | |
3902 | ||
3903 | CASE (sem, INSN_ROTL_COMPACT) : /* rotl $rn */ | |
3904 | { | |
3905 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3906 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3907 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
3908 | int UNUSED written = 0; | |
3909 | IADDR UNUSED pc = abuf->addr; | |
3910 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3911 | ||
3912 | { | |
3913 | BI tmp_temp; | |
3914 | tmp_temp = SRLSI (GET_H_GRC (FLD (f_rn)), 31); | |
3915 | { | |
3916 | SI opval = ORSI (SLLSI (GET_H_GRC (FLD (f_rn)), 1), tmp_temp); | |
3917 | SET_H_GRC (FLD (f_rn), opval); | |
3918 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
3919 | } | |
3920 | { | |
3921 | BI opval = ((tmp_temp) ? (1) : (0)); | |
3922 | SET_H_TBIT (opval); | |
3923 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); | |
3924 | } | |
3925 | } | |
3926 | ||
3927 | #undef FLD | |
3928 | } | |
3929 | NEXT (vpc); | |
3930 | ||
3931 | CASE (sem, INSN_ROTR_COMPACT) : /* rotr $rn */ | |
3932 | { | |
3933 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3934 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3935 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
3936 | int UNUSED written = 0; | |
3937 | IADDR UNUSED pc = abuf->addr; | |
3938 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3939 | ||
3940 | { | |
3941 | BI tmp_lsbit; | |
3942 | SI tmp_temp; | |
3943 | tmp_lsbit = ((EQSI (ANDSI (GET_H_GRC (FLD (f_rn)), 1), 0)) ? (0) : (1)); | |
3944 | tmp_temp = tmp_lsbit; | |
3945 | { | |
3946 | SI opval = ORSI (SRLSI (GET_H_GRC (FLD (f_rn)), 1), SLLSI (tmp_temp, 31)); | |
3947 | SET_H_GRC (FLD (f_rn), opval); | |
3948 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
3949 | } | |
3950 | { | |
3951 | BI opval = ((tmp_lsbit) ? (1) : (0)); | |
3952 | SET_H_TBIT (opval); | |
3953 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); | |
3954 | } | |
3955 | } | |
3956 | ||
3957 | #undef FLD | |
3958 | } | |
3959 | NEXT (vpc); | |
3960 | ||
3961 | CASE (sem, INSN_RTS_COMPACT) : /* rts */ | |
3962 | { | |
3963 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3964 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3965 | #define FLD(f) abuf->fields.fmt_empty.f | |
3966 | int UNUSED written = 0; | |
3967 | IADDR UNUSED pc = abuf->addr; | |
3968 | SEM_BRANCH_INIT | |
3969 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3970 | ||
3971 | { | |
3972 | { | |
3973 | UDI opval = GET_H_PR (); | |
3974 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); | |
3975 | TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); | |
3976 | } | |
3977 | } | |
3978 | ||
3979 | SEM_BRANCH_FINI (vpc); | |
3980 | #undef FLD | |
3981 | } | |
3982 | NEXT (vpc); | |
3983 | ||
3984 | CASE (sem, INSN_SETS_COMPACT) : /* sets */ | |
3985 | { | |
3986 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3987 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3988 | #define FLD(f) abuf->fields.fmt_empty.f | |
3989 | int UNUSED written = 0; | |
3990 | IADDR UNUSED pc = abuf->addr; | |
3991 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3992 | ||
3993 | { | |
3994 | BI opval = 1; | |
3995 | SET_H_SBIT (opval); | |
3996 | TRACE_RESULT (current_cpu, abuf, "sbit", 'x', opval); | |
3997 | } | |
3998 | ||
3999 | #undef FLD | |
4000 | } | |
4001 | NEXT (vpc); | |
4002 | ||
4003 | CASE (sem, INSN_SETT_COMPACT) : /* sett */ | |
4004 | { | |
4005 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4006 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4007 | #define FLD(f) abuf->fields.fmt_empty.f | |
4008 | int UNUSED written = 0; | |
4009 | IADDR UNUSED pc = abuf->addr; | |
4010 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4011 | ||
4012 | { | |
4013 | BI opval = 1; | |
4014 | SET_H_TBIT (opval); | |
4015 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); | |
4016 | } | |
4017 | ||
4018 | #undef FLD | |
4019 | } | |
4020 | NEXT (vpc); | |
4021 | ||
4022 | CASE (sem, INSN_SHAD_COMPACT) : /* shad $rm, $rn */ | |
4023 | { | |
4024 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4025 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4026 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
4027 | int UNUSED written = 0; | |
4028 | IADDR UNUSED pc = abuf->addr; | |
4029 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4030 | ||
4031 | { | |
4032 | QI tmp_shamt; | |
4033 | tmp_shamt = ANDQI (GET_H_GRC (FLD (f_rm)), 31); | |
4034 | if (GESI (GET_H_GRC (FLD (f_rm)), 0)) { | |
4035 | { | |
4036 | SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), tmp_shamt); | |
4037 | SET_H_GRC (FLD (f_rn), opval); | |
4038 | written |= (1 << 3); | |
4039 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
4040 | } | |
4041 | } else { | |
4042 | if (NEQI (tmp_shamt, 0)) { | |
4043 | { | |
4044 | SI opval = SRASI (GET_H_GRC (FLD (f_rn)), SUBSI (32, tmp_shamt)); | |
4045 | SET_H_GRC (FLD (f_rn), opval); | |
4046 | written |= (1 << 3); | |
4047 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
4048 | } | |
4049 | } else { | |
4050 | if (LTSI (GET_H_GRC (FLD (f_rn)), 0)) { | |
4051 | { | |
4052 | SI opval = NEGSI (1); | |
4053 | SET_H_GRC (FLD (f_rn), opval); | |
4054 | written |= (1 << 3); | |
4055 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
4056 | } | |
4057 | } else { | |
4058 | { | |
4059 | SI opval = 0; | |
4060 | SET_H_GRC (FLD (f_rn), opval); | |
4061 | written |= (1 << 3); | |
4062 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
4063 | } | |
4064 | } | |
4065 | } | |
4066 | } | |
4067 | } | |
4068 | ||
4069 | abuf->written = written; | |
4070 | #undef FLD | |
4071 | } | |
4072 | NEXT (vpc); | |
4073 | ||
4074 | CASE (sem, INSN_SHAL_COMPACT) : /* shal $rn */ | |
4075 | { | |
4076 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4077 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4078 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
4079 | int UNUSED written = 0; | |
4080 | IADDR UNUSED pc = abuf->addr; | |
4081 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4082 | ||
4083 | { | |
4084 | BI tmp_t; | |
4085 | tmp_t = SRLSI (GET_H_GRC (FLD (f_rn)), 31); | |
4086 | { | |
4087 | SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 1); | |
4088 | SET_H_GRC (FLD (f_rn), opval); | |
4089 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
4090 | } | |
4091 | { | |
4092 | BI opval = ((tmp_t) ? (1) : (0)); | |
4093 | SET_H_TBIT (opval); | |
4094 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); | |
4095 | } | |
4096 | } | |
4097 | ||
4098 | #undef FLD | |
4099 | } | |
4100 | NEXT (vpc); | |
4101 | ||
4102 | CASE (sem, INSN_SHAR_COMPACT) : /* shar $rn */ | |
4103 | { | |
4104 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4105 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4106 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
4107 | int UNUSED written = 0; | |
4108 | IADDR UNUSED pc = abuf->addr; | |
4109 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4110 | ||
4111 | { | |
4112 | BI tmp_t; | |
4113 | tmp_t = ANDSI (GET_H_GRC (FLD (f_rn)), 1); | |
4114 | { | |
4115 | SI opval = SRASI (GET_H_GRC (FLD (f_rn)), 1); | |
4116 | SET_H_GRC (FLD (f_rn), opval); | |
4117 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
4118 | } | |
4119 | { | |
4120 | BI opval = ((tmp_t) ? (1) : (0)); | |
4121 | SET_H_TBIT (opval); | |
4122 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); | |
4123 | } | |
4124 | } | |
4125 | ||
4126 | #undef FLD | |
4127 | } | |
4128 | NEXT (vpc); | |
4129 | ||
4130 | CASE (sem, INSN_SHLD_COMPACT) : /* shld $rm, $rn */ | |
4131 | { | |
4132 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4133 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4134 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
4135 | int UNUSED written = 0; | |
4136 | IADDR UNUSED pc = abuf->addr; | |
4137 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4138 | ||
4139 | { | |
4140 | QI tmp_shamt; | |
4141 | tmp_shamt = ANDQI (GET_H_GRC (FLD (f_rm)), 31); | |
4142 | if (GESI (GET_H_GRC (FLD (f_rm)), 0)) { | |
4143 | { | |
4144 | SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), tmp_shamt); | |
4145 | SET_H_GRC (FLD (f_rn), opval); | |
4146 | written |= (1 << 3); | |
4147 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
4148 | } | |
4149 | } else { | |
4150 | if (NEQI (tmp_shamt, 0)) { | |
4151 | { | |
4152 | SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), SUBSI (32, tmp_shamt)); | |
4153 | SET_H_GRC (FLD (f_rn), opval); | |
4154 | written |= (1 << 3); | |
4155 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
4156 | } | |
4157 | } else { | |
4158 | { | |
4159 | SI opval = 0; | |
4160 | SET_H_GRC (FLD (f_rn), opval); | |
4161 | written |= (1 << 3); | |
4162 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
4163 | } | |
4164 | } | |
4165 | } | |
4166 | } | |
4167 | ||
4168 | abuf->written = written; | |
4169 | #undef FLD | |
4170 | } | |
4171 | NEXT (vpc); | |
4172 | ||
4173 | CASE (sem, INSN_SHLL_COMPACT) : /* shll $rn */ | |
4174 | { | |
4175 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4176 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4177 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
4178 | int UNUSED written = 0; | |
4179 | IADDR UNUSED pc = abuf->addr; | |
4180 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4181 | ||
4182 | { | |
4183 | BI tmp_t; | |
4184 | tmp_t = SRLSI (GET_H_GRC (FLD (f_rn)), 31); | |
4185 | { | |
4186 | SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 1); | |
4187 | SET_H_GRC (FLD (f_rn), opval); | |
4188 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
4189 | } | |
4190 | { | |
4191 | BI opval = ((tmp_t) ? (1) : (0)); | |
4192 | SET_H_TBIT (opval); | |
4193 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); | |
4194 | } | |
4195 | } | |
4196 | ||
4197 | #undef FLD | |
4198 | } | |
4199 | NEXT (vpc); | |
4200 | ||
4201 | CASE (sem, INSN_SHLL2_COMPACT) : /* shll2 $rn */ | |
4202 | { | |
4203 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4204 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4205 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
4206 | int UNUSED written = 0; | |
4207 | IADDR UNUSED pc = abuf->addr; | |
4208 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4209 | ||
4210 | { | |
4211 | SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 2); | |
4212 | SET_H_GRC (FLD (f_rn), opval); | |
4213 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
4214 | } | |
4215 | ||
4216 | #undef FLD | |
4217 | } | |
4218 | NEXT (vpc); | |
4219 | ||
4220 | CASE (sem, INSN_SHLL8_COMPACT) : /* shll8 $rn */ | |
4221 | { | |
4222 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4223 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4224 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
4225 | int UNUSED written = 0; | |
4226 | IADDR UNUSED pc = abuf->addr; | |
4227 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4228 | ||
4229 | { | |
4230 | SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 8); | |
4231 | SET_H_GRC (FLD (f_rn), opval); | |
4232 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
4233 | } | |
4234 | ||
4235 | #undef FLD | |
4236 | } | |
4237 | NEXT (vpc); | |
4238 | ||
4239 | CASE (sem, INSN_SHLL16_COMPACT) : /* shll16 $rn */ | |
4240 | { | |
4241 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4242 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4243 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
4244 | int UNUSED written = 0; | |
4245 | IADDR UNUSED pc = abuf->addr; | |
4246 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4247 | ||
4248 | { | |
4249 | SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 16); | |
4250 | SET_H_GRC (FLD (f_rn), opval); | |
4251 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
4252 | } | |
4253 | ||
4254 | #undef FLD | |
4255 | } | |
4256 | NEXT (vpc); | |
4257 | ||
4258 | CASE (sem, INSN_SHLR_COMPACT) : /* shlr $rn */ | |
4259 | { | |
4260 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4261 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4262 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
4263 | int UNUSED written = 0; | |
4264 | IADDR UNUSED pc = abuf->addr; | |
4265 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4266 | ||
4267 | { | |
4268 | BI tmp_t; | |
4269 | tmp_t = ANDSI (GET_H_GRC (FLD (f_rn)), 1); | |
4270 | { | |
4271 | SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 1); | |
4272 | SET_H_GRC (FLD (f_rn), opval); | |
4273 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
4274 | } | |
4275 | { | |
4276 | BI opval = ((tmp_t) ? (1) : (0)); | |
4277 | SET_H_TBIT (opval); | |
4278 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); | |
4279 | } | |
4280 | } | |
4281 | ||
4282 | #undef FLD | |
4283 | } | |
4284 | NEXT (vpc); | |
4285 | ||
4286 | CASE (sem, INSN_SHLR2_COMPACT) : /* shlr2 $rn */ | |
4287 | { | |
4288 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4289 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4290 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
4291 | int UNUSED written = 0; | |
4292 | IADDR UNUSED pc = abuf->addr; | |
4293 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4294 | ||
4295 | { | |
4296 | SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 2); | |
4297 | SET_H_GRC (FLD (f_rn), opval); | |
4298 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
4299 | } | |
4300 | ||
4301 | #undef FLD | |
4302 | } | |
4303 | NEXT (vpc); | |
4304 | ||
4305 | CASE (sem, INSN_SHLR8_COMPACT) : /* shlr8 $rn */ | |
4306 | { | |
4307 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4308 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4309 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
4310 | int UNUSED written = 0; | |
4311 | IADDR UNUSED pc = abuf->addr; | |
4312 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4313 | ||
4314 | { | |
4315 | SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 8); | |
4316 | SET_H_GRC (FLD (f_rn), opval); | |
4317 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
4318 | } | |
4319 | ||
4320 | #undef FLD | |
4321 | } | |
4322 | NEXT (vpc); | |
4323 | ||
4324 | CASE (sem, INSN_SHLR16_COMPACT) : /* shlr16 $rn */ | |
4325 | { | |
4326 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4327 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4328 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
4329 | int UNUSED written = 0; | |
4330 | IADDR UNUSED pc = abuf->addr; | |
4331 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4332 | ||
4333 | { | |
4334 | SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 16); | |
4335 | SET_H_GRC (FLD (f_rn), opval); | |
4336 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
4337 | } | |
4338 | ||
4339 | #undef FLD | |
4340 | } | |
4341 | NEXT (vpc); | |
4342 | ||
4343 | CASE (sem, INSN_STC_GBR_COMPACT) : /* stc gbr, $rn */ | |
4344 | { | |
4345 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4346 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4347 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
4348 | int UNUSED written = 0; | |
4349 | IADDR UNUSED pc = abuf->addr; | |
4350 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4351 | ||
4352 | { | |
4353 | SI opval = GET_H_GBR (); | |
4354 | SET_H_GRC (FLD (f_rn), opval); | |
4355 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
4356 | } | |
4357 | ||
4358 | #undef FLD | |
4359 | } | |
4360 | NEXT (vpc); | |
4361 | ||
4362 | CASE (sem, INSN_STCL_GBR_COMPACT) : /* stc.l gbr, @-$rn */ | |
4363 | { | |
4364 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4365 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4366 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
4367 | int UNUSED written = 0; | |
4368 | IADDR UNUSED pc = abuf->addr; | |
4369 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4370 | ||
4371 | { | |
4372 | DI tmp_addr; | |
4373 | tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4); | |
4374 | { | |
4375 | SI opval = GET_H_GBR (); | |
4376 | SETMEMSI (current_cpu, pc, tmp_addr, opval); | |
4377 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
4378 | } | |
4379 | { | |
4380 | SI opval = tmp_addr; | |
4381 | SET_H_GRC (FLD (f_rn), opval); | |
4382 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
4383 | } | |
4384 | } | |
4385 | ||
4386 | #undef FLD | |
4387 | } | |
4388 | NEXT (vpc); | |
4389 | ||
4390 | CASE (sem, INSN_STS_FPSCR_COMPACT) : /* sts fpscr, $rn */ | |
4391 | { | |
4392 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4393 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4394 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
4395 | int UNUSED written = 0; | |
4396 | IADDR UNUSED pc = abuf->addr; | |
4397 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4398 | ||
4399 | { | |
4400 | SI opval = GET_H_FPCCR (); | |
4401 | SET_H_GRC (FLD (f_rn), opval); | |
4402 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
4403 | } | |
4404 | ||
4405 | #undef FLD | |
4406 | } | |
4407 | NEXT (vpc); | |
4408 | ||
4409 | CASE (sem, INSN_STSL_FPSCR_COMPACT) : /* sts.l fpscr, @-$rn */ | |
4410 | { | |
4411 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4412 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4413 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
4414 | int UNUSED written = 0; | |
4415 | IADDR UNUSED pc = abuf->addr; | |
4416 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4417 | ||
4418 | { | |
4419 | DI tmp_addr; | |
4420 | tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4); | |
4421 | { | |
4422 | SI opval = GET_H_FPCCR (); | |
4423 | SETMEMSI (current_cpu, pc, tmp_addr, opval); | |
4424 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
4425 | } | |
4426 | { | |
4427 | SI opval = tmp_addr; | |
4428 | SET_H_GRC (FLD (f_rn), opval); | |
4429 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
4430 | } | |
4431 | } | |
4432 | ||
4433 | #undef FLD | |
4434 | } | |
4435 | NEXT (vpc); | |
4436 | ||
4437 | CASE (sem, INSN_STS_FPUL_COMPACT) : /* sts fpul, $rn */ | |
4438 | { | |
4439 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4440 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4441 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
4442 | int UNUSED written = 0; | |
4443 | IADDR UNUSED pc = abuf->addr; | |
4444 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4445 | ||
4446 | { | |
4447 | SI opval = SUBWORDSFSI (CPU (h_fr[((UINT) 32)])); | |
4448 | SET_H_GRC (FLD (f_rn), opval); | |
4449 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
4450 | } | |
4451 | ||
4452 | #undef FLD | |
4453 | } | |
4454 | NEXT (vpc); | |
4455 | ||
4456 | CASE (sem, INSN_STSL_FPUL_COMPACT) : /* sts.l fpul, @-$rn */ | |
4457 | { | |
4458 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4459 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4460 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
4461 | int UNUSED written = 0; | |
4462 | IADDR UNUSED pc = abuf->addr; | |
4463 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4464 | ||
4465 | { | |
4466 | DI tmp_addr; | |
4467 | tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4); | |
4468 | { | |
4469 | SF opval = CPU (h_fr[((UINT) 32)]); | |
4470 | SETMEMSF (current_cpu, pc, tmp_addr, opval); | |
4471 | TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); | |
4472 | } | |
4473 | { | |
4474 | SI opval = tmp_addr; | |
4475 | SET_H_GRC (FLD (f_rn), opval); | |
4476 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
4477 | } | |
4478 | } | |
4479 | ||
4480 | #undef FLD | |
4481 | } | |
4482 | NEXT (vpc); | |
4483 | ||
4484 | CASE (sem, INSN_STS_MACH_COMPACT) : /* sts mach, $rn */ | |
4485 | { | |
4486 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4487 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4488 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
4489 | int UNUSED written = 0; | |
4490 | IADDR UNUSED pc = abuf->addr; | |
4491 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4492 | ||
4493 | { | |
4494 | SI opval = GET_H_MACH (); | |
4495 | SET_H_GRC (FLD (f_rn), opval); | |
4496 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
4497 | } | |
4498 | ||
4499 | #undef FLD | |
4500 | } | |
4501 | NEXT (vpc); | |
4502 | ||
4503 | CASE (sem, INSN_STSL_MACH_COMPACT) : /* sts.l mach, @-$rn */ | |
4504 | { | |
4505 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4506 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4507 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
4508 | int UNUSED written = 0; | |
4509 | IADDR UNUSED pc = abuf->addr; | |
4510 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4511 | ||
4512 | { | |
4513 | DI tmp_addr; | |
4514 | tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4); | |
4515 | { | |
4516 | SI opval = GET_H_MACH (); | |
4517 | SETMEMSI (current_cpu, pc, tmp_addr, opval); | |
4518 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
4519 | } | |
4520 | { | |
4521 | SI opval = tmp_addr; | |
4522 | SET_H_GRC (FLD (f_rn), opval); | |
4523 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
4524 | } | |
4525 | } | |
4526 | ||
4527 | #undef FLD | |
4528 | } | |
4529 | NEXT (vpc); | |
4530 | ||
4531 | CASE (sem, INSN_STS_MACL_COMPACT) : /* sts macl, $rn */ | |
4532 | { | |
4533 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4534 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4535 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
4536 | int UNUSED written = 0; | |
4537 | IADDR UNUSED pc = abuf->addr; | |
4538 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4539 | ||
4540 | { | |
4541 | SI opval = GET_H_MACL (); | |
4542 | SET_H_GRC (FLD (f_rn), opval); | |
4543 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
4544 | } | |
4545 | ||
4546 | #undef FLD | |
4547 | } | |
4548 | NEXT (vpc); | |
4549 | ||
4550 | CASE (sem, INSN_STSL_MACL_COMPACT) : /* sts.l macl, @-$rn */ | |
4551 | { | |
4552 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4553 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4554 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
4555 | int UNUSED written = 0; | |
4556 | IADDR UNUSED pc = abuf->addr; | |
4557 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4558 | ||
4559 | { | |
4560 | DI tmp_addr; | |
4561 | tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4); | |
4562 | { | |
4563 | SI opval = GET_H_MACL (); | |
4564 | SETMEMSI (current_cpu, pc, tmp_addr, opval); | |
4565 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
4566 | } | |
4567 | { | |
4568 | SI opval = tmp_addr; | |
4569 | SET_H_GRC (FLD (f_rn), opval); | |
4570 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
4571 | } | |
4572 | } | |
4573 | ||
4574 | #undef FLD | |
4575 | } | |
4576 | NEXT (vpc); | |
4577 | ||
4578 | CASE (sem, INSN_STS_PR_COMPACT) : /* sts pr, $rn */ | |
4579 | { | |
4580 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4581 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4582 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
4583 | int UNUSED written = 0; | |
4584 | IADDR UNUSED pc = abuf->addr; | |
4585 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4586 | ||
4587 | { | |
4588 | SI opval = GET_H_PR (); | |
4589 | SET_H_GRC (FLD (f_rn), opval); | |
4590 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
4591 | } | |
4592 | ||
4593 | #undef FLD | |
4594 | } | |
4595 | NEXT (vpc); | |
4596 | ||
4597 | CASE (sem, INSN_STSL_PR_COMPACT) : /* sts.l pr, @-$rn */ | |
4598 | { | |
4599 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4600 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4601 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
4602 | int UNUSED written = 0; | |
4603 | IADDR UNUSED pc = abuf->addr; | |
4604 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4605 | ||
4606 | { | |
4607 | DI tmp_addr; | |
4608 | tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4); | |
4609 | { | |
4610 | SI opval = GET_H_PR (); | |
4611 | SETMEMSI (current_cpu, pc, tmp_addr, opval); | |
4612 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
4613 | } | |
4614 | { | |
4615 | SI opval = tmp_addr; | |
4616 | SET_H_GRC (FLD (f_rn), opval); | |
4617 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
4618 | } | |
4619 | } | |
4620 | ||
4621 | #undef FLD | |
4622 | } | |
4623 | NEXT (vpc); | |
4624 | ||
4625 | CASE (sem, INSN_SUB_COMPACT) : /* sub $rm, $rn */ | |
4626 | { | |
4627 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4628 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4629 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
4630 | int UNUSED written = 0; | |
4631 | IADDR UNUSED pc = abuf->addr; | |
4632 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4633 | ||
4634 | { | |
4635 | SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm))); | |
4636 | SET_H_GRC (FLD (f_rn), opval); | |
4637 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
4638 | } | |
4639 | ||
4640 | #undef FLD | |
4641 | } | |
4642 | NEXT (vpc); | |
4643 | ||
4644 | CASE (sem, INSN_SUBC_COMPACT) : /* subc $rm, $rn */ | |
4645 | { | |
4646 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4647 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4648 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
4649 | int UNUSED written = 0; | |
4650 | IADDR UNUSED pc = abuf->addr; | |
4651 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4652 | ||
4653 | { | |
4654 | BI tmp_flag; | |
4655 | tmp_flag = SUBCFSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), GET_H_TBIT ()); | |
4656 | { | |
4657 | SI opval = SUBCSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), GET_H_TBIT ()); | |
4658 | SET_H_GRC (FLD (f_rn), opval); | |
4659 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
4660 | } | |
4661 | { | |
4662 | BI opval = tmp_flag; | |
4663 | SET_H_TBIT (opval); | |
4664 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); | |
4665 | } | |
4666 | } | |
4667 | ||
4668 | #undef FLD | |
4669 | } | |
4670 | NEXT (vpc); | |
4671 | ||
4672 | CASE (sem, INSN_SUBV_COMPACT) : /* subv $rm, $rn */ | |
4673 | { | |
4674 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4675 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4676 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
4677 | int UNUSED written = 0; | |
4678 | IADDR UNUSED pc = abuf->addr; | |
4679 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4680 | ||
4681 | { | |
4682 | BI tmp_t; | |
4683 | tmp_t = SUBOFSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), 0); | |
4684 | { | |
4685 | SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm))); | |
4686 | SET_H_GRC (FLD (f_rn), opval); | |
4687 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
4688 | } | |
4689 | { | |
4690 | BI opval = ((tmp_t) ? (1) : (0)); | |
4691 | SET_H_TBIT (opval); | |
4692 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); | |
4693 | } | |
4694 | } | |
4695 | ||
4696 | #undef FLD | |
4697 | } | |
4698 | NEXT (vpc); | |
4699 | ||
4700 | CASE (sem, INSN_SWAPB_COMPACT) : /* swap.b $rm, $rn */ | |
4701 | { | |
4702 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4703 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4704 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
4705 | int UNUSED written = 0; | |
4706 | IADDR UNUSED pc = abuf->addr; | |
4707 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4708 | ||
4709 | { | |
4710 | UHI tmp_top_half; | |
4711 | UQI tmp_byte1; | |
4712 | UQI tmp_byte0; | |
4713 | tmp_top_half = SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 0); | |
4714 | tmp_byte1 = SUBWORDSIQI (GET_H_GRC (FLD (f_rm)), 2); | |
4715 | tmp_byte0 = SUBWORDSIQI (GET_H_GRC (FLD (f_rm)), 3); | |
4716 | { | |
4717 | SI opval = ORSI (SLLSI (tmp_top_half, 16), ORSI (SLLSI (tmp_byte0, 8), tmp_byte1)); | |
4718 | SET_H_GRC (FLD (f_rn), opval); | |
4719 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
4720 | } | |
4721 | } | |
4722 | ||
4723 | #undef FLD | |
4724 | } | |
4725 | NEXT (vpc); | |
4726 | ||
4727 | CASE (sem, INSN_SWAPW_COMPACT) : /* swap.w $rm, $rn */ | |
4728 | { | |
4729 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4730 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4731 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
4732 | int UNUSED written = 0; | |
4733 | IADDR UNUSED pc = abuf->addr; | |
4734 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4735 | ||
4736 | { | |
4737 | SI opval = ORSI (SRLSI (GET_H_GRC (FLD (f_rm)), 16), SLLSI (GET_H_GRC (FLD (f_rm)), 16)); | |
4738 | SET_H_GRC (FLD (f_rn), opval); | |
4739 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
4740 | } | |
4741 | ||
4742 | #undef FLD | |
4743 | } | |
4744 | NEXT (vpc); | |
4745 | ||
4746 | CASE (sem, INSN_TASB_COMPACT) : /* tas.b @$rn */ | |
4747 | { | |
4748 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4749 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4750 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f | |
4751 | int UNUSED written = 0; | |
4752 | IADDR UNUSED pc = abuf->addr; | |
4753 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4754 | ||
4755 | { | |
4756 | UQI tmp_byte; | |
4757 | tmp_byte = GETMEMUQI (current_cpu, pc, GET_H_GRC (FLD (f_rn))); | |
4758 | { | |
4759 | BI opval = ((EQQI (tmp_byte, 0)) ? (1) : (0)); | |
4760 | SET_H_TBIT (opval); | |
4761 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); | |
4762 | } | |
4763 | tmp_byte = ORQI (tmp_byte, 128); | |
4764 | { | |
4765 | UQI opval = tmp_byte; | |
4766 | SETMEMUQI (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval); | |
4767 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
4768 | } | |
4769 | } | |
4770 | ||
4771 | #undef FLD | |
4772 | } | |
4773 | NEXT (vpc); | |
4774 | ||
4775 | CASE (sem, INSN_TRAPA_COMPACT) : /* trapa #$uimm8 */ | |
4776 | { | |
4777 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4778 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4779 | #define FLD(f) abuf->fields.sfmt_addi_compact.f | |
4780 | int UNUSED written = 0; | |
4781 | IADDR UNUSED pc = abuf->addr; | |
4782 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4783 | ||
4784 | sh64_compact_trapa (current_cpu, FLD (f_imm8), pc); | |
4785 | ||
4786 | #undef FLD | |
4787 | } | |
4788 | NEXT (vpc); | |
4789 | ||
4790 | CASE (sem, INSN_TST_COMPACT) : /* tst $rm, $rn */ | |
4791 | { | |
4792 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4793 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4794 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
4795 | int UNUSED written = 0; | |
4796 | IADDR UNUSED pc = abuf->addr; | |
4797 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4798 | ||
4799 | { | |
4800 | BI opval = ((EQSI (ANDSI (GET_H_GRC (FLD (f_rm)), GET_H_GRC (FLD (f_rn))), 0)) ? (1) : (0)); | |
4801 | SET_H_TBIT (opval); | |
4802 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); | |
4803 | } | |
4804 | ||
4805 | #undef FLD | |
4806 | } | |
4807 | NEXT (vpc); | |
4808 | ||
4809 | CASE (sem, INSN_TSTI_COMPACT) : /* tst #$uimm8, r0 */ | |
4810 | { | |
4811 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4812 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4813 | #define FLD(f) abuf->fields.sfmt_addi_compact.f | |
4814 | int UNUSED written = 0; | |
4815 | IADDR UNUSED pc = abuf->addr; | |
4816 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4817 | ||
4818 | { | |
4819 | BI opval = ((EQSI (ANDSI (GET_H_GRC (((UINT) 0)), ZEXTSISI (FLD (f_imm8))), 0)) ? (1) : (0)); | |
4820 | SET_H_TBIT (opval); | |
4821 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); | |
4822 | } | |
4823 | ||
4824 | #undef FLD | |
4825 | } | |
4826 | NEXT (vpc); | |
4827 | ||
4828 | CASE (sem, INSN_TSTB_COMPACT) : /* tst.b #$imm8, @(r0, gbr) */ | |
4829 | { | |
4830 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4831 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4832 | #define FLD(f) abuf->fields.sfmt_addi_compact.f | |
4833 | int UNUSED written = 0; | |
4834 | IADDR UNUSED pc = abuf->addr; | |
4835 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4836 | ||
4837 | { | |
4838 | DI tmp_addr; | |
4839 | tmp_addr = ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GBR ()); | |
4840 | { | |
4841 | BI opval = ((EQQI (ANDQI (GETMEMUQI (current_cpu, pc, tmp_addr), FLD (f_imm8)), 0)) ? (1) : (0)); | |
4842 | SET_H_TBIT (opval); | |
4843 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); | |
4844 | } | |
4845 | } | |
4846 | ||
4847 | #undef FLD | |
4848 | } | |
4849 | NEXT (vpc); | |
4850 | ||
4851 | CASE (sem, INSN_XOR_COMPACT) : /* xor $rm64, $rn64 */ | |
4852 | { | |
4853 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4854 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4855 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
4856 | int UNUSED written = 0; | |
4857 | IADDR UNUSED pc = abuf->addr; | |
4858 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4859 | ||
4860 | { | |
4861 | DI opval = XORDI (GET_H_GR (FLD (f_rn)), GET_H_GR (FLD (f_rm))); | |
4862 | SET_H_GR (FLD (f_rn), opval); | |
4863 | TRACE_RESULT (current_cpu, abuf, "rn64", 'D', opval); | |
4864 | } | |
4865 | ||
4866 | #undef FLD | |
4867 | } | |
4868 | NEXT (vpc); | |
4869 | ||
4870 | CASE (sem, INSN_XORI_COMPACT) : /* xor #$uimm8, r0 */ | |
4871 | { | |
4872 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4873 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4874 | #define FLD(f) abuf->fields.sfmt_addi_compact.f | |
4875 | int UNUSED written = 0; | |
4876 | IADDR UNUSED pc = abuf->addr; | |
4877 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4878 | ||
4879 | { | |
4880 | DI opval = XORDI (GET_H_GR (((UINT) 0)), ZEXTSIDI (FLD (f_imm8))); | |
4881 | SET_H_GR (((UINT) 0), opval); | |
4882 | TRACE_RESULT (current_cpu, abuf, "gr-0", 'D', opval); | |
4883 | } | |
4884 | ||
4885 | #undef FLD | |
4886 | } | |
4887 | NEXT (vpc); | |
4888 | ||
4889 | CASE (sem, INSN_XORB_COMPACT) : /* xor.b #$imm8, @(r0, gbr) */ | |
4890 | { | |
4891 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4892 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4893 | #define FLD(f) abuf->fields.sfmt_addi_compact.f | |
4894 | int UNUSED written = 0; | |
4895 | IADDR UNUSED pc = abuf->addr; | |
4896 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4897 | ||
4898 | { | |
4899 | DI tmp_addr; | |
4900 | UQI tmp_data; | |
4901 | tmp_addr = ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GBR ()); | |
4902 | tmp_data = XORQI (GETMEMUQI (current_cpu, pc, tmp_addr), FLD (f_imm8)); | |
4903 | { | |
4904 | UQI opval = tmp_data; | |
4905 | SETMEMUQI (current_cpu, pc, tmp_addr, opval); | |
4906 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
4907 | } | |
4908 | } | |
4909 | ||
4910 | #undef FLD | |
4911 | } | |
4912 | NEXT (vpc); | |
4913 | ||
4914 | CASE (sem, INSN_XTRCT_COMPACT) : /* xtrct $rm, $rn */ | |
4915 | { | |
4916 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4917 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4918 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f | |
4919 | int UNUSED written = 0; | |
4920 | IADDR UNUSED pc = abuf->addr; | |
4921 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4922 | ||
4923 | { | |
4924 | SI opval = ORSI (SLLSI (GET_H_GRC (FLD (f_rm)), 16), SRLSI (GET_H_GRC (FLD (f_rn)), 16)); | |
4925 | SET_H_GRC (FLD (f_rn), opval); | |
4926 | TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); | |
4927 | } | |
4928 | ||
4929 | #undef FLD | |
4930 | } | |
4931 | NEXT (vpc); | |
4932 | ||
4933 | ||
4934 | } | |
4935 | ENDSWITCH (sem) /* End of semantic switch. */ | |
4936 | ||
4937 | /* At this point `vpc' contains the next insn to execute. */ | |
4938 | } | |
4939 | ||
4940 | #undef DEFINE_SWITCH | |
4941 | #endif /* DEFINE_SWITCH */ |