Commit | Line | Data |
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cbb38b47 BE |
1 | /* CPU data header for sh. |
2 | ||
3 | THIS FILE IS MACHINE GENERATED WITH CGEN. | |
4 | ||
c7e628df | 5 | Copyright 1996-2005 Free Software Foundation, Inc. |
cbb38b47 BE |
6 | |
7 | This file is part of the GNU Binutils and/or GDB, the GNU debugger. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
4744ac1b JB |
11 | the Free Software Foundation; either version 3 of the License, or |
12 | (at your option) any later version. | |
cbb38b47 BE |
13 | |
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
4744ac1b JB |
19 | You should have received a copy of the GNU General Public License |
20 | along with this program. If not, see <http://www.gnu.org/licenses/>. | |
cbb38b47 BE |
21 | |
22 | */ | |
23 | ||
24 | #ifndef SH_CPU_H | |
25 | #define SH_CPU_H | |
26 | ||
c7e628df DB |
27 | #include "opcode/cgen-bitset.h" |
28 | ||
cbb38b47 BE |
29 | #define CGEN_ARCH sh |
30 | ||
31 | /* Given symbol S, return sh_cgen_<S>. */ | |
32 | #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) | |
33 | #define CGEN_SYM(s) sh##_cgen_##s | |
34 | #else | |
35 | #define CGEN_SYM(s) sh/**/_cgen_/**/s | |
36 | #endif | |
37 | ||
38 | ||
39 | /* Selected cpu families. */ | |
40 | #define HAVE_CPU_SH64 | |
41 | ||
c7e628df | 42 | #define CGEN_INSN_LSB0_P 0 |
cbb38b47 BE |
43 | |
44 | /* Minimum size of any insn (in bytes). */ | |
45 | #define CGEN_MIN_INSN_SIZE 2 | |
46 | ||
47 | /* Maximum size of any insn (in bytes). */ | |
48 | #define CGEN_MAX_INSN_SIZE 4 | |
49 | ||
50 | #define CGEN_INT_INSN_P 1 | |
51 | ||
c7e628df DB |
52 | /* Maximum number of syntax elements in an instruction. */ |
53 | #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 22 | |
cbb38b47 BE |
54 | |
55 | /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. | |
56 | e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands | |
57 | we can't hash on everything up to the space. */ | |
58 | #define CGEN_MNEMONIC_OPERANDS | |
59 | ||
60 | /* Maximum number of fields in an instruction. */ | |
61 | #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 8 | |
62 | ||
63 | /* Enums. */ | |
64 | ||
65 | /* Enum declaration for . */ | |
66 | typedef enum frc_names { | |
67 | H_FRC_FR0, H_FRC_FR1, H_FRC_FR2, H_FRC_FR3 | |
68 | , H_FRC_FR4, H_FRC_FR5, H_FRC_FR6, H_FRC_FR7 | |
69 | , H_FRC_FR8, H_FRC_FR9, H_FRC_FR10, H_FRC_FR11 | |
70 | , H_FRC_FR12, H_FRC_FR13, H_FRC_FR14, H_FRC_FR15 | |
71 | } FRC_NAMES; | |
72 | ||
73 | /* Enum declaration for . */ | |
74 | typedef enum drc_names { | |
75 | H_DRC_DR0 = 0, H_DRC_DR2 = 2, H_DRC_DR4 = 4, H_DRC_DR6 = 6 | |
76 | , H_DRC_DR8 = 8, H_DRC_DR10 = 10, H_DRC_DR12 = 12, H_DRC_DR14 = 14 | |
77 | } DRC_NAMES; | |
78 | ||
79 | /* Enum declaration for . */ | |
80 | typedef enum xf_names { | |
81 | H_XF_XF0, H_XF_XF1, H_XF_XF2, H_XF_XF3 | |
82 | , H_XF_XF4, H_XF_XF5, H_XF_XF6, H_XF_XF7 | |
83 | , H_XF_XF8, H_XF_XF9, H_XF_XF10, H_XF_XF11 | |
84 | , H_XF_XF12, H_XF_XF13, H_XF_XF14, H_XF_XF15 | |
85 | } XF_NAMES; | |
86 | ||
87 | /* Attributes. */ | |
88 | ||
89 | /* Enum declaration for machine type selection. */ | |
90 | typedef enum mach_attr { | |
c7e628df DB |
91 | MACH_BASE, MACH_SH2, MACH_SH2E, MACH_SH2A_FPU |
92 | , MACH_SH2A_NOFPU, MACH_SH3, MACH_SH3E, MACH_SH4_NOFPU | |
93 | , MACH_SH4, MACH_SH4A_NOFPU, MACH_SH4A, MACH_SH4AL | |
94 | , MACH_SH5, MACH_MAX | |
cbb38b47 BE |
95 | } MACH_ATTR; |
96 | ||
97 | /* Enum declaration for instruction set selection. */ | |
98 | typedef enum isa_attr { | |
99 | ISA_COMPACT, ISA_MEDIA, ISA_MAX | |
100 | } ISA_ATTR; | |
101 | ||
c7e628df DB |
102 | /* Enum declaration for sh4 insn groups. */ |
103 | typedef enum sh4_group_attr { | |
104 | SH4_GROUP_NONE, SH4_GROUP_MT, SH4_GROUP_EX, SH4_GROUP_BR | |
105 | , SH4_GROUP_LS, SH4_GROUP_FE, SH4_GROUP_CO, SH4_GROUP_MAX | |
106 | } SH4_GROUP_ATTR; | |
107 | ||
108 | /* Enum declaration for sh4a insn groups. */ | |
109 | typedef enum sh4a_group_attr { | |
110 | SH4A_GROUP_NONE, SH4A_GROUP_MT, SH4A_GROUP_EX, SH4A_GROUP_BR | |
111 | , SH4A_GROUP_LS, SH4A_GROUP_FE, SH4A_GROUP_CO, SH4A_GROUP_MAX | |
112 | } SH4A_GROUP_ATTR; | |
113 | ||
cbb38b47 BE |
114 | /* Number of architecture variants. */ |
115 | #define MAX_ISAS ((int) ISA_MAX) | |
116 | #define MAX_MACHS ((int) MACH_MAX) | |
117 | ||
c7e628df DB |
118 | /* Ifield support. */ |
119 | ||
cbb38b47 BE |
120 | /* Ifield attribute indices. */ |
121 | ||
122 | /* Enum declaration for cgen_ifld attrs. */ | |
123 | typedef enum cgen_ifld_attr { | |
124 | CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED | |
125 | , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 | |
126 | , CGEN_IFLD_MACH, CGEN_IFLD_ISA, CGEN_IFLD_END_NBOOLS | |
127 | } CGEN_IFLD_ATTR; | |
128 | ||
129 | /* Number of non-boolean elements in cgen_ifld_attr. */ | |
130 | #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) | |
131 | ||
c7e628df DB |
132 | /* cgen_ifld attribute accessor macros. */ |
133 | #define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) | |
134 | #define CGEN_ATTR_CGEN_IFLD_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_ISA-CGEN_IFLD_START_NBOOLS-1].bitset) | |
135 | #define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0) | |
136 | #define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) | |
137 | #define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0) | |
138 | #define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0) | |
139 | #define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0) | |
140 | #define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0) | |
141 | ||
cbb38b47 BE |
142 | /* Enum declaration for sh ifield types. */ |
143 | typedef enum ifield_type { | |
144 | SH_F_NIL, SH_F_ANYOF, SH_F_OP4, SH_F_OP8 | |
145 | , SH_F_OP16, SH_F_SUB4, SH_F_SUB8, SH_F_SUB10 | |
c7e628df DB |
146 | , SH_F_RN, SH_F_RM, SH_F_7_1, SH_F_11_1 |
147 | , SH_F_16_4, SH_F_DISP8, SH_F_DISP12, SH_F_IMM8 | |
148 | , SH_F_IMM4, SH_F_IMM4X2, SH_F_IMM4X4, SH_F_IMM8X2 | |
149 | , SH_F_IMM8X4, SH_F_IMM12X4, SH_F_IMM12X8, SH_F_DN | |
cbb38b47 | 150 | , SH_F_DM, SH_F_VN, SH_F_VM, SH_F_XN |
c7e628df DB |
151 | , SH_F_XM, SH_F_IMM20_HI, SH_F_IMM20_LO, SH_F_IMM20 |
152 | , SH_F_OP, SH_F_EXT, SH_F_RSVD, SH_F_LEFT | |
153 | , SH_F_RIGHT, SH_F_DEST, SH_F_LEFT_RIGHT, SH_F_TRA | |
154 | , SH_F_TRB, SH_F_LIKELY, SH_F_6_3, SH_F_23_2 | |
155 | , SH_F_IMM6, SH_F_IMM10, SH_F_IMM16, SH_F_UIMM6 | |
156 | , SH_F_UIMM16, SH_F_DISP6, SH_F_DISP6X32, SH_F_DISP10 | |
157 | , SH_F_DISP10X8, SH_F_DISP10X4, SH_F_DISP10X2, SH_F_DISP16 | |
158 | , SH_F_MAX | |
cbb38b47 BE |
159 | } IFIELD_TYPE; |
160 | ||
161 | #define MAX_IFLD ((int) SH_F_MAX) | |
162 | ||
163 | /* Hardware attribute indices. */ | |
164 | ||
165 | /* Enum declaration for cgen_hw attrs. */ | |
166 | typedef enum cgen_hw_attr { | |
167 | CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE | |
c7e628df DB |
168 | , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_ISA |
169 | , CGEN_HW_END_NBOOLS | |
cbb38b47 BE |
170 | } CGEN_HW_ATTR; |
171 | ||
172 | /* Number of non-boolean elements in cgen_hw_attr. */ | |
173 | #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) | |
174 | ||
c7e628df DB |
175 | /* cgen_hw attribute accessor macros. */ |
176 | #define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) | |
177 | #define CGEN_ATTR_CGEN_HW_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_ISA-CGEN_HW_START_NBOOLS-1].bitset) | |
178 | #define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0) | |
179 | #define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0) | |
180 | #define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0) | |
181 | #define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0) | |
182 | ||
cbb38b47 BE |
183 | /* Enum declaration for sh hardware types. */ |
184 | typedef enum cgen_hw_type { | |
185 | HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR | |
186 | , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_GRC | |
187 | , HW_H_CR, HW_H_SR, HW_H_FPSCR, HW_H_FRBIT | |
188 | , HW_H_SZBIT, HW_H_PRBIT, HW_H_SBIT, HW_H_MBIT | |
189 | , HW_H_QBIT, HW_H_FR, HW_H_FP, HW_H_FV | |
c7e628df DB |
190 | , HW_H_FMTX, HW_H_DR, HW_H_FSD, HW_H_FMOV |
191 | , HW_H_TR, HW_H_ENDIAN, HW_H_ISM, HW_H_FRC | |
192 | , HW_H_DRC, HW_H_XF, HW_H_XD, HW_H_FVC | |
193 | , HW_H_GBR, HW_H_VBR, HW_H_PR, HW_H_MACL | |
194 | , HW_H_MACH, HW_H_TBIT, HW_MAX | |
cbb38b47 BE |
195 | } CGEN_HW_TYPE; |
196 | ||
197 | #define MAX_HW ((int) HW_MAX) | |
198 | ||
199 | /* Operand attribute indices. */ | |
200 | ||
201 | /* Enum declaration for cgen_operand attrs. */ | |
202 | typedef enum cgen_operand_attr { | |
203 | CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT | |
204 | , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY | |
205 | , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_ISA | |
206 | , CGEN_OPERAND_END_NBOOLS | |
207 | } CGEN_OPERAND_ATTR; | |
208 | ||
209 | /* Number of non-boolean elements in cgen_operand_attr. */ | |
210 | #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) | |
211 | ||
c7e628df DB |
212 | /* cgen_operand attribute accessor macros. */ |
213 | #define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) | |
214 | #define CGEN_ATTR_CGEN_OPERAND_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_ISA-CGEN_OPERAND_START_NBOOLS-1].bitset) | |
215 | #define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0) | |
216 | #define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) | |
217 | #define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) | |
218 | #define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) | |
219 | #define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0) | |
220 | #define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0) | |
221 | #define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0) | |
222 | #define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) | |
223 | ||
cbb38b47 BE |
224 | /* Enum declaration for sh operand types. */ |
225 | typedef enum cgen_operand_type { | |
226 | SH_OPERAND_PC, SH_OPERAND_ENDIAN, SH_OPERAND_ISM, SH_OPERAND_RM | |
227 | , SH_OPERAND_RN, SH_OPERAND_R0, SH_OPERAND_FRN, SH_OPERAND_FRM | |
c7e628df DB |
228 | , SH_OPERAND_FR0, SH_OPERAND_FMOVN, SH_OPERAND_FMOVM, SH_OPERAND_FVN |
229 | , SH_OPERAND_FVM, SH_OPERAND_DRN, SH_OPERAND_DRM, SH_OPERAND_IMM4 | |
230 | , SH_OPERAND_IMM8, SH_OPERAND_UIMM8, SH_OPERAND_IMM20, SH_OPERAND_IMM4X2 | |
cbb38b47 | 231 | , SH_OPERAND_IMM4X4, SH_OPERAND_IMM8X2, SH_OPERAND_IMM8X4, SH_OPERAND_DISP8 |
c7e628df DB |
232 | , SH_OPERAND_DISP12, SH_OPERAND_IMM12X4, SH_OPERAND_IMM12X8, SH_OPERAND_RM64 |
233 | , SH_OPERAND_RN64, SH_OPERAND_GBR, SH_OPERAND_VBR, SH_OPERAND_PR | |
234 | , SH_OPERAND_FPSCR, SH_OPERAND_TBIT, SH_OPERAND_SBIT, SH_OPERAND_MBIT | |
235 | , SH_OPERAND_QBIT, SH_OPERAND_FPUL, SH_OPERAND_FRBIT, SH_OPERAND_SZBIT | |
236 | , SH_OPERAND_PRBIT, SH_OPERAND_MACL, SH_OPERAND_MACH, SH_OPERAND_FSDM | |
237 | , SH_OPERAND_FSDN, SH_OPERAND_RD, SH_OPERAND_FRG, SH_OPERAND_FRH | |
238 | , SH_OPERAND_FRF, SH_OPERAND_FRGH, SH_OPERAND_FPF, SH_OPERAND_FVG | |
239 | , SH_OPERAND_FVH, SH_OPERAND_FVF, SH_OPERAND_MTRXG, SH_OPERAND_DRG | |
240 | , SH_OPERAND_DRH, SH_OPERAND_DRF, SH_OPERAND_DRGH, SH_OPERAND_CRJ | |
241 | , SH_OPERAND_CRK, SH_OPERAND_TRA, SH_OPERAND_TRB, SH_OPERAND_DISP6 | |
242 | , SH_OPERAND_DISP6X32, SH_OPERAND_DISP10, SH_OPERAND_DISP10X2, SH_OPERAND_DISP10X4 | |
243 | , SH_OPERAND_DISP10X8, SH_OPERAND_DISP16, SH_OPERAND_IMM6, SH_OPERAND_IMM10 | |
244 | , SH_OPERAND_IMM16, SH_OPERAND_UIMM6, SH_OPERAND_UIMM16, SH_OPERAND_LIKELY | |
245 | , SH_OPERAND_MAX | |
cbb38b47 BE |
246 | } CGEN_OPERAND_TYPE; |
247 | ||
248 | /* Number of operands types. */ | |
c7e628df | 249 | #define MAX_OPERANDS 79 |
cbb38b47 BE |
250 | |
251 | /* Maximum number of operands referenced by any insn. */ | |
252 | #define MAX_OPERAND_INSTANCES 8 | |
253 | ||
254 | /* Insn attribute indices. */ | |
255 | ||
256 | /* Enum declaration for cgen_insn attrs. */ | |
257 | typedef enum cgen_insn_attr { | |
258 | CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI | |
c7e628df | 259 | , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED |
cbb38b47 | 260 | , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_ILLSLOT, CGEN_INSN_FP_INSN |
c7e628df DB |
261 | , CGEN_INSN_32_BIT_INSN, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH |
262 | , CGEN_INSN_ISA, CGEN_INSN_SH4_GROUP, CGEN_INSN_SH4A_GROUP, CGEN_INSN_END_NBOOLS | |
cbb38b47 BE |
263 | } CGEN_INSN_ATTR; |
264 | ||
265 | /* Number of non-boolean elements in cgen_insn_attr. */ | |
266 | #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) | |
267 | ||
c7e628df DB |
268 | /* cgen_insn attribute accessor macros. */ |
269 | #define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) | |
270 | #define CGEN_ATTR_CGEN_INSN_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_ISA-CGEN_INSN_START_NBOOLS-1].bitset) | |
271 | #define CGEN_ATTR_CGEN_INSN_SH4_GROUP_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_SH4_GROUP-CGEN_INSN_START_NBOOLS-1].nonbitset) | |
272 | #define CGEN_ATTR_CGEN_INSN_SH4A_GROUP_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_SH4A_GROUP-CGEN_INSN_START_NBOOLS-1].nonbitset) | |
273 | #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0) | |
274 | #define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0) | |
275 | #define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0) | |
276 | #define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0) | |
277 | #define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0) | |
278 | #define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0) | |
279 | #define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0) | |
280 | #define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0) | |
281 | #define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0) | |
282 | #define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0) | |
283 | #define CGEN_ATTR_CGEN_INSN_ILLSLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ILLSLOT)) != 0) | |
284 | #define CGEN_ATTR_CGEN_INSN_FP_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_FP_INSN)) != 0) | |
285 | #define CGEN_ATTR_CGEN_INSN_32_BIT_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_32_BIT_INSN)) != 0) | |
286 | ||
cbb38b47 BE |
287 | /* cgen.h uses things we just defined. */ |
288 | #include "opcode/cgen.h" | |
289 | ||
c7e628df DB |
290 | extern const struct cgen_ifld sh_cgen_ifld_table[]; |
291 | ||
cbb38b47 BE |
292 | /* Attributes. */ |
293 | extern const CGEN_ATTR_TABLE sh_cgen_hardware_attr_table[]; | |
294 | extern const CGEN_ATTR_TABLE sh_cgen_ifield_attr_table[]; | |
295 | extern const CGEN_ATTR_TABLE sh_cgen_operand_attr_table[]; | |
296 | extern const CGEN_ATTR_TABLE sh_cgen_insn_attr_table[]; | |
297 | ||
298 | /* Hardware decls. */ | |
299 | ||
300 | extern CGEN_KEYWORD sh_cgen_opval_h_gr; | |
301 | extern CGEN_KEYWORD sh_cgen_opval_h_grc; | |
302 | extern CGEN_KEYWORD sh_cgen_opval_h_cr; | |
303 | extern CGEN_KEYWORD sh_cgen_opval_h_fr; | |
304 | extern CGEN_KEYWORD sh_cgen_opval_h_fp; | |
305 | extern CGEN_KEYWORD sh_cgen_opval_h_fv; | |
306 | extern CGEN_KEYWORD sh_cgen_opval_h_fmtx; | |
307 | extern CGEN_KEYWORD sh_cgen_opval_h_dr; | |
c7e628df DB |
308 | extern CGEN_KEYWORD sh_cgen_opval_h_fsd; |
309 | extern CGEN_KEYWORD sh_cgen_opval_h_fmov; | |
cbb38b47 BE |
310 | extern CGEN_KEYWORD sh_cgen_opval_h_tr; |
311 | extern CGEN_KEYWORD sh_cgen_opval_frc_names; | |
312 | extern CGEN_KEYWORD sh_cgen_opval_drc_names; | |
313 | extern CGEN_KEYWORD sh_cgen_opval_xf_names; | |
314 | extern CGEN_KEYWORD sh_cgen_opval_frc_names; | |
315 | extern CGEN_KEYWORD sh_cgen_opval_h_fvc; | |
316 | ||
c7e628df | 317 | extern const CGEN_HW_ENTRY sh_cgen_hw_table[]; |
cbb38b47 BE |
318 | |
319 | ||
320 | ||
321 | #endif /* SH_CPU_H */ |