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cbb38b47 | 1 | /* Main simulator entry points specific to the SH5. |
ecd75fc8 | 2 | Copyright (C) 2000-2014 Free Software Foundation, Inc. |
cbb38b47 BE |
3 | Contributed by Cygnus Solutions. |
4 | ||
5 | This file is part of the GNU simulators. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
4744ac1b JB |
9 | the Free Software Foundation; either version 3 of the License, or |
10 | (at your option) any later version. | |
cbb38b47 BE |
11 | |
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
4744ac1b JB |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
cbb38b47 | 19 | |
a6ff997c | 20 | #include "config.h" |
cbb38b47 BE |
21 | #include "libiberty.h" |
22 | #include "bfd.h" | |
23 | #include "sim-main.h" | |
24 | #ifdef HAVE_STDLIB_H | |
25 | #include <stdlib.h> | |
26 | #endif | |
27 | #include "sim-options.h" | |
28 | #include "dis-asm.h" | |
29 | ||
30 | static void free_state (SIM_DESC); | |
31 | ||
32 | /* Since we don't build the cgen-opcode table, we use a wrapper around | |
33 | the existing disassembler from libopcodes. */ | |
34 | static CGEN_DISASSEMBLER sh64_disassemble_insn; | |
35 | ||
36 | /* Records simulator descriptor so utilities like sh5_dump_regs can be | |
37 | called from gdb. */ | |
38 | SIM_DESC current_state; | |
39 | \f | |
40 | /* Cover function of sim_state_free to free the cpu buffers as well. */ | |
41 | ||
42 | static void | |
43 | free_state (SIM_DESC sd) | |
44 | { | |
45 | if (STATE_MODULES (sd) != NULL) | |
46 | sim_module_uninstall (sd); | |
47 | sim_cpu_free_all (sd); | |
48 | sim_state_free (sd); | |
49 | } | |
50 | ||
51 | /* Create an instance of the simulator. */ | |
52 | ||
53 | SIM_DESC | |
54 | sim_open (kind, callback, abfd, argv) | |
55 | SIM_OPEN_KIND kind; | |
56 | host_callback *callback; | |
21bc7567 | 57 | struct bfd *abfd; |
cbb38b47 BE |
58 | char **argv; |
59 | { | |
60 | char c; | |
61 | int i; | |
62 | SIM_DESC sd = sim_state_alloc (kind, callback); | |
63 | ||
64 | /* The cpu data is kept in a separately allocated chunk of memory. */ | |
65 | if (sim_cpu_alloc_all (sd, 1, cgen_cpu_max_extra_bytes ()) != SIM_RC_OK) | |
66 | { | |
67 | free_state (sd); | |
68 | return 0; | |
69 | } | |
70 | ||
71 | #if 0 /* FIXME: pc is in mach-specific struct */ | |
72 | /* FIXME: watchpoints code shouldn't need this */ | |
73 | { | |
74 | SIM_CPU *current_cpu = STATE_CPU (sd, 0); | |
75 | STATE_WATCHPOINTS (sd)->pc = &(PC); | |
76 | STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC); | |
77 | } | |
78 | #endif | |
79 | ||
80 | if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) | |
81 | { | |
82 | free_state (sd); | |
83 | return 0; | |
84 | } | |
85 | ||
86 | #if 0 /* FIXME: 'twould be nice if we could do this */ | |
87 | /* These options override any module options. | |
88 | Obviously ambiguity should be avoided, however the caller may wish to | |
89 | augment the meaning of an option. */ | |
90 | if (extra_options != NULL) | |
91 | sim_add_option_table (sd, extra_options); | |
92 | #endif | |
93 | ||
94 | /* getopt will print the error message so we just have to exit if this fails. | |
95 | FIXME: Hmmm... in the case of gdb we need getopt to call | |
96 | print_filtered. */ | |
97 | if (sim_parse_args (sd, argv) != SIM_RC_OK) | |
98 | { | |
99 | free_state (sd); | |
100 | return 0; | |
101 | } | |
102 | ||
103 | /* Allocate core managed memory if none specified by user. | |
104 | Use address 4 here in case the user wanted address 0 unmapped. */ | |
105 | if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0) | |
106 | sim_do_commandf (sd, "memory region 0,0x%x", SH64_DEFAULT_MEM_SIZE); | |
107 | ||
108 | /* Add a small memory region way up in the address space to handle | |
109 | writes to invalidate an instruction cache line. This is used for | |
110 | trampolines. Since we don't simulate the cache, this memory just | |
111 | avoids bus errors. 64K ought to do. */ | |
112 | sim_do_command (sd," memory region 0xf0000000,0x10000"); | |
113 | ||
114 | /* check for/establish the reference program image */ | |
115 | if (sim_analyze_program (sd, | |
116 | (STATE_PROG_ARGV (sd) != NULL | |
117 | ? *STATE_PROG_ARGV (sd) | |
118 | : NULL), | |
119 | abfd) != SIM_RC_OK) | |
120 | { | |
121 | free_state (sd); | |
122 | return 0; | |
123 | } | |
124 | ||
125 | /* Establish any remaining configuration options. */ | |
126 | if (sim_config (sd) != SIM_RC_OK) | |
127 | { | |
128 | free_state (sd); | |
129 | return 0; | |
130 | } | |
131 | ||
132 | if (sim_post_argv_init (sd) != SIM_RC_OK) | |
133 | { | |
134 | free_state (sd); | |
135 | return 0; | |
136 | } | |
137 | ||
138 | /* Open a copy of the cpu descriptor table. */ | |
139 | { | |
140 | CGEN_CPU_DESC cd = sh_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name, | |
141 | CGEN_ENDIAN_BIG); | |
142 | ||
143 | for (i = 0; i < MAX_NR_PROCESSORS; ++i) | |
144 | { | |
145 | SIM_CPU *cpu = STATE_CPU (sd, i); | |
146 | CPU_CPU_DESC (cpu) = cd; | |
147 | CPU_DISASSEMBLER (cpu) = sh64_disassemble_insn; | |
148 | } | |
149 | } | |
150 | ||
151 | /* Clear idesc table pointers for good measure. */ | |
152 | sh64_idesc_media = sh64_idesc_compact = NULL; | |
153 | ||
154 | /* Initialize various cgen things not done by common framework. | |
155 | Must be done after sh_cgen_cpu_open. */ | |
156 | cgen_init (sd); | |
157 | ||
158 | /* Store in a global so things like sparc32_dump_regs can be invoked | |
159 | from the gdb command line. */ | |
160 | current_state = sd; | |
161 | ||
162 | return sd; | |
163 | } | |
164 | ||
165 | void | |
166 | sim_close (sd, quitting) | |
167 | SIM_DESC sd; | |
168 | int quitting; | |
169 | { | |
170 | sh_cgen_cpu_close (CPU_CPU_DESC (STATE_CPU (sd, 0))); | |
171 | sim_module_uninstall (sd); | |
172 | } | |
173 | \f | |
174 | SIM_RC | |
175 | sim_create_inferior (sd, abfd, argv, envp) | |
176 | SIM_DESC sd; | |
21bc7567 | 177 | struct bfd *abfd; |
cbb38b47 BE |
178 | char **argv; |
179 | char **envp; | |
180 | { | |
181 | SIM_CPU *current_cpu = STATE_CPU (sd, 0); | |
182 | SIM_ADDR addr; | |
183 | ||
184 | if (abfd != NULL) | |
185 | addr = bfd_get_start_address (abfd); | |
186 | else | |
187 | addr = 0; | |
188 | sim_pc_set (current_cpu, addr); | |
189 | ||
190 | #if 0 | |
191 | STATE_ARGV (sd) = sim_copy_argv (argv); | |
192 | STATE_ENVP (sd) = sim_copy_argv (envp); | |
193 | #endif | |
194 | ||
195 | return SIM_RC_OK; | |
196 | } | |
cbb38b47 BE |
197 | \f |
198 | /* Disassemble an instruction. */ | |
199 | ||
200 | static void | |
201 | sh64_disassemble_insn (SIM_CPU *cpu, const CGEN_INSN *insn, | |
202 | const ARGBUF *abuf, IADDR pc, char *buf) | |
203 | { | |
204 | struct disassemble_info disasm_info; | |
205 | SFILE sfile; | |
206 | SIM_DESC sd = CPU_STATE (cpu); | |
207 | ||
208 | sfile.buffer = sfile.current = buf; | |
209 | INIT_DISASSEMBLE_INFO (disasm_info, (FILE *) &sfile, | |
210 | (fprintf_ftype) sim_disasm_sprintf); | |
211 | ||
212 | disasm_info.arch = bfd_get_arch (STATE_PROG_BFD (sd)); | |
213 | disasm_info.mach = bfd_get_mach (STATE_PROG_BFD (sd)); | |
214 | disasm_info.endian = | |
215 | (bfd_big_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_BIG | |
216 | : bfd_little_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_LITTLE | |
217 | : BFD_ENDIAN_UNKNOWN); | |
218 | disasm_info.read_memory_func = sim_disasm_read_memory; | |
219 | disasm_info.memory_error_func = sim_disasm_perror_memory; | |
220 | disasm_info.application_data = (PTR) cpu; | |
221 | ||
222 | if (sh64_h_ism_get (cpu) == ISM_MEDIA) | |
223 | print_insn_sh64x_media (pc, &disasm_info); | |
224 | else | |
1c509ca8 | 225 | print_insn_sh (pc, &disasm_info); |
cbb38b47 | 226 | } |