projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 0ab7df8a DB |
1 | 2000-11-01 Dave Brolley <brolley@cygnus.com> |
| 2 | ||
| 3 | * lib/sim-defs.exp (run_sm_test): Correct comment. "output" and | |
| 4 | "xerror" options do not use a list of machines. Clear options from | |
| 5 | previous test case. Use "$cpu_option" to identify the machine to the | |
| 6 | assembler, if specified. | |
| 7 | ||
| eb2d80b4 AC |
8 | Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com> |
| 9 | ||
| 10 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 11 | ||
| c2c6d25f JM |
12 | 1999-09-15 Doug Evans <devans@casey.cygnus.com> |
| 13 | ||
| 14 | * sim/arm/b.cgs: New testcase. | |
| 15 | * sim/arm/bic.cgs: New testcase. | |
| 16 | * sim/arm/bl.cgs: New testcase. | |
| 17 | ||
| d4f3574e SS |
18 | Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com> |
| 19 | ||
| 20 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 21 | ||
| 104c1213 JM |
22 | 1999-08-30 Doug Evans <devans@casey.cygnus.com> |
| 23 | ||
| 104c1213 JM |
24 | * lib/sim-defs.exp (run_sim_test): Rename all_machs arg to |
| 25 | requested_machs, now is list of machs to run tests for. | |
| 26 | Delete locals AS,ASFLAGS,LD,LDFLAGS. Use target_assemble | |
| 27 | and target_link instead. | |
| 28 | ||
| 7a292a7a SS |
29 | 1999-04-21 Doug Evans <devans@casey.cygnus.com> |
| 30 | ||
| 31 | * sim/m32r/nop.cgs: Add missing nop insn. | |
| 32 | ||
| 33 | Mon Mar 22 13:28:56 1999 Dave Brolley <brolley@cygnus.com> | |
| 34 | ||
| 35 | * sim/fr30/stb.cgs: Correct for unaligned access. | |
| 36 | * sim/fr30/sth.cgs: Correct for unaligned access. | |
| 37 | * sim/fr30/ldub.cgs: Fix typo: lduh->ldub. Correct | |
| 38 | for unaligned access. | |
| 39 | * sim/fr30/and.cgs: Test unaligned access. | |
| 40 | ||
| c906108c SS |
41 | Fri Feb 5 12:41:11 1999 Doug Evans <devans@canuck.cygnus.com> |
| 42 | ||
| 43 | * lib/sim-defs.exp (sim_run): Print simulator arguments log message. | |
| 44 | ||
| 45 | 1999-01-05 Doug Evans <devans@casey.cygnus.com> | |
| 46 | ||
| 47 | * lib/sim-defs.exp (run_sim_test): New arg all_machs. | |
| 48 | * sim/fr30/allinsn.exp: Update. | |
| 49 | * sim/fr30/misc.exp: Update. | |
| 50 | * sim/m32r/allinsn.exp: Update. | |
| 51 | * sim/m32r/misc.exp: Update. | |
| 52 | ||
| 53 | Fri Dec 18 17:19:34 1998 Dave Brolley <brolley@cygnus.com> | |
| 54 | ||
| 55 | * sim/fr30/ldres.cgs: New testcase. | |
| 56 | * sim/fr30/copld.cgs: New testcase. | |
| 57 | * sim/fr30/copst.cgs: New testcase. | |
| 58 | * sim/fr30/copsv.cgs: New testcase. | |
| 59 | * sim/fr30/nop.cgs: New testcase. | |
| 60 | * sim/fr30/andccr.cgs: New testcase. | |
| 61 | * sim/fr30/orccr.cgs: New testcase. | |
| 62 | * sim/fr30/addsp.cgs: New testcase. | |
| 63 | * sim/fr30/stilm.cgs: New testcase. | |
| 64 | * sim/fr30/extsb.cgs: New testcase. | |
| 65 | * sim/fr30/extub.cgs: New testcase. | |
| 66 | * sim/fr30/extsh.cgs: New testcase. | |
| 67 | * sim/fr30/extuh.cgs: New testcase. | |
| 68 | * sim/fr30/enter.cgs: New testcase. | |
| 69 | * sim/fr30/leave.cgs: New testcase. | |
| 70 | * sim/fr30/xchb.cgs: New testcase. | |
| 71 | * sim/fr30/dmovb.cgs: New testcase. | |
| 72 | * sim/fr30/dmov.cgs: New testcase. | |
| 73 | * sim/fr30/dmovh.cgs: New testcase. | |
| 74 | ||
| 75 | Thu Dec 17 17:18:43 1998 Dave Brolley <brolley@cygnus.com> | |
| 76 | ||
| 77 | * sim/fr30/testutils.inc (take_branch{_d},no_branch{_d}): New macros. | |
| 78 | * sim/fr30/ret.cgs: Add tests fir ret:d. | |
| 79 | * sim/fr30/inte.cgs: New testcase. | |
| 80 | * sim/fr30/reti.cgs: New testcase. | |
| 81 | * sim/fr30/bra.cgs: New testcase. | |
| 82 | * sim/fr30/bno.cgs: New testcase. | |
| 83 | * sim/fr30/beq.cgs: New testcase. | |
| 84 | * sim/fr30/bne.cgs: New testcase. | |
| 85 | * sim/fr30/bc.cgs: New testcase. | |
| 86 | * sim/fr30/bnc.cgs: New testcase. | |
| 87 | * sim/fr30/bn.cgs: New testcase. | |
| 88 | * sim/fr30/bp.cgs: New testcase. | |
| 89 | * sim/fr30/bv.cgs: New testcase. | |
| 90 | * sim/fr30/bnv.cgs: New testcase. | |
| 91 | * sim/fr30/blt.cgs: New testcase. | |
| 92 | * sim/fr30/bge.cgs: New testcase. | |
| 93 | * sim/fr30/ble.cgs: New testcase. | |
| 94 | * sim/fr30/bgt.cgs: New testcase. | |
| 95 | * sim/fr30/bls.cgs: New testcase. | |
| 96 | * sim/fr30/bhi.cgs: New testcase. | |
| 97 | ||
| 98 | Tue Dec 15 17:47:13 1998 Dave Brolley <brolley@cygnus.com> | |
| 99 | ||
| 100 | * sim/fr30/div.cgs (int): Add signed division scenario. | |
| 101 | * sim/fr30/int.cgs (int): Complete testcase. | |
| 102 | * sim/fr30/testutils.inc (_start): Initialize tbr. | |
| 103 | (test_s_user,test_s_system,set_i,test_i): New macros. | |
| 104 | ||
| 105 | 1998-12-14 Doug Evans <devans@casey.cygnus.com> | |
| 106 | ||
| 107 | * lib/sim-defs.exp (run_sim_test): New option xerror, for expected | |
| 108 | errors. Translate \n sequences in expected output to newline char. | |
| 109 | (slurp_options): Make parentheses optional. | |
| 110 | (sim_run): Look for board_info sim,options. | |
| 111 | * sim/fr30/hello.ms: Add trailing \n to expected output. | |
| 112 | * sim/m32r/hello.ms: Ditto. | |
| 113 | * sim/m32r/hw-trap.ms: Ditto. | |
| 114 | ||
| 115 | * sim/m32r/trap.cgs: Properly align trap2_handler. | |
| 116 | ||
| 117 | * sim/m32r/uread16.ms: New testcase. | |
| 118 | * sim/m32r/uread32.ms: New testcase. | |
| 119 | * sim/m32r/uwrite16.ms: New testcase. | |
| 120 | * sim/m32r/uwrite32.ms: New testcase. | |
| 121 | ||
| 122 | 1998-12-14 Dave Brolley <brolley@cygnus.com> | |
| 123 | ||
| 124 | * sim/fr30/call.cgs: Test ret here as well. | |
| 125 | * sim/fr30/ld.cgs: Remove bogus comment. | |
| 126 | * sim/fr30/testutils.inc (save_rp,restore_rp): New macros. | |
| 127 | * sim/fr30/div.ms: New testcase. | |
| 128 | * sim/fr30/st.cgs: New testcase. | |
| 129 | * sim/fr30/sth.cgs: New testcase. | |
| 130 | * sim/fr30/stb.cgs: New testcase. | |
| 131 | * sim/fr30/mov.cgs: New testcase. | |
| 132 | * sim/fr30/jmp.cgs: New testcase. | |
| 133 | * sim/fr30/ret.cgs: New testcase. | |
| 134 | * sim/fr30/int.cgs: New testcase. | |
| 135 | ||
| 136 | Thu Dec 10 18:46:25 1998 Dave Brolley <brolley@cygnus.com> | |
| 137 | ||
| 138 | * sim/fr30/div0s.cgs: New testcase. | |
| 139 | * sim/fr30/div0u.cgs: New testcase. | |
| 140 | * sim/fr30/div1.cgs: New testcase. | |
| 141 | * sim/fr30/div2.cgs: New testcase. | |
| 142 | * sim/fr30/div3.cgs: New testcase. | |
| 143 | * sim/fr30/div4s.cgs: New testcase. | |
| 144 | * sim/fr30/testutils.inc (mvi_h_dr,set_dbits,test_dbits): New Macros. | |
| 145 | ||
| 146 | Tue Dec 8 13:16:53 1998 Dave Brolley <brolley@cygnus.com> | |
| 147 | ||
| 148 | * sim/fr30/testutils.inc (set_s_user): Correct Mask. | |
| 149 | (set_s_system): Correct Mask. | |
| 150 | * sim/fr30/ld.cgs (ld): Move previously failing test back | |
| 151 | into place. | |
| 152 | * sim/fr30/ldm0.cgs: New testcase. | |
| 153 | * sim/fr30/ldm1.cgs: New testcase. | |
| 154 | * sim/fr30/stm0.cgs: New testcase. | |
| 155 | * sim/fr30/stm1.cgs: New testcase. | |
| 156 | ||
| 157 | Thu Dec 3 14:20:03 1998 Dave Brolley <brolley@cygnus.com> | |
| 158 | ||
| 159 | * sim/fr30/ld.cgs: Implement more loads. | |
| 160 | * sim/fr30/call.cgs: New testcase. | |
| 161 | * sim/fr30/testutils.inc (testr_h_dr): New macro. | |
| 162 | (set_s_user,set_s_system): New macros. | |
| 163 | ||
| 164 | * sim/fr30: New Directory. | |
| 165 | ||
| 166 | Wed Nov 18 10:50:19 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 167 | ||
| 168 | * common/bits-gen.c (main): Add BYTE_ORDER so that it matches | |
| 169 | recent sim/common/sim-basics.h changes. | |
| 170 | * common/Makefile.in: Update. | |
| 171 | ||
| 172 | Fri Oct 30 00:37:31 1998 Felix Lee <flee@cygnus.com> | |
| 173 | ||
| 174 | * lib/sim-defs.exp (sim_run): download target program to remote | |
| 175 | host, if necessary. for unix-driven win32 testing. | |
| 176 | ||
| 177 | Tue Sep 15 14:56:22 1998 Doug Evans <devans@canuck.cygnus.com> | |
| 178 | ||
| 179 | * sim/m32r/testutils.inc (test_h_gr): Use mvaddr_h_gr. | |
| 180 | * sim/m32r/rte.cgs: Test bbpc,bbpsw. | |
| 181 | * sim/m32r/trap.cgs: Test bbpc,bbpsw. | |
| 182 | ||
| 7a292a7a SS |
183 | Fri Jul 31 17:49:13 1998 Felix Lee <flee@cygnus.com> |
| 184 | ||
| 185 | * lib/sim-defs.exp (sim_run): remote_spawn, use writeto instead of | |
| 186 | writeonly. | |
| 187 | ||
| c906108c SS |
188 | Fri Jul 24 09:40:34 1998 Doug Evans <devans@canuck.cygnus.com> |
| 189 | ||
| 190 | * Makefile.in (clean,mostlyclean): Change leading spaces to a tab. | |
| 191 | ||
| 192 | Wed Jul 1 15:57:54 1998 Doug Evans <devans@seba.cygnus.com> | |
| 193 | ||
| 194 | * sim/m32r/hw-trap.ms: New testcase. | |
| 195 | ||
| 7a292a7a SS |
196 | Tue Jun 16 15:44:01 1998 Jillian Ye <jillian@cygnus.com> |
| 197 | ||
| 198 | * lib/sim-defs.exp: Print out timeout setting info when "-v" is used. | |
| 199 | ||
| 200 | Thu Jun 11 15:24:53 1998 Doug Evans <devans@canuck.cygnus.com> | |
| 201 | ||
| 202 | * lib/sim-defs.exp (sim_run): Argument env_vals renamed to options, | |
| 203 | which is now a list of options controlling the behaviour of sim_run. | |
| 204 | ||
| c906108c SS |
205 | Wed Jun 10 10:53:20 1998 Doug Evans <devans@seba.cygnus.com> |
| 206 | ||
| 207 | * sim/m32r/addx.cgs: Add another test. | |
| 208 | * sim/m32r/jmp.cgs: Add another test. | |
| 209 | ||
| 210 | Mon Jun 8 16:08:27 1998 Doug Evans <devans@canuck.cygnus.com> | |
| 211 | ||
| 212 | * sim/m32r/trap.cgs: Test trap 2. | |
| 213 | ||
| 214 | Mon Jun 1 18:54:22 1998 Frank Ch. Eigler <fche@cygnus.com> | |
| 215 | ||
| 216 | * lib/sim-defs.exp (sim_run): Add possible environment variable | |
| 217 | list to simulator run. | |
| 218 | ||
| 219 | Thu May 28 14:59:46 1998 Jillian Ye <jillian@cygnus.com> | |
| 220 | ||
| 221 | * Makefile.in: Take RUNTEST out of FLAG_TO_PASS | |
| 222 | so that make check can be invoked recursively. | |
| 223 | ||
| 224 | Thu May 14 11:48:35 1998 Doug Evans <devans@canuck.cygnus.com> | |
| 225 | ||
| 226 | * config/default.exp (CC,SIM): Delete. | |
| 227 | ||
| 228 | * lib/sim-defs.exp (sim_run): Fix handling of output redirection. | |
| 229 | New arg prog_opts. All callers updated. | |
| 230 | ||
| 231 | Fri May 8 18:10:28 1998 Jillian Ye <jillian@cygnus.com> | |
| 232 | ||
| 233 | * Makefile.in: Made "check" the target of two | |
| 234 | dependencies (test1, test2) so that test2 get a chance to | |
| 235 | run even when test1 failed if "make -k check" is used. | |
| 236 | ||
| 237 | Fri May 8 14:41:28 1998 Doug Evans <devans@canuck.cygnus.com> | |
| 238 | ||
| 239 | * lib/sim-defs.exp (sim_version): Simplify. | |
| 240 | (sim_run): Implement. | |
| 241 | (run_sim_test): Use sim_run. | |
| 242 | (sim_compile): New proc. | |
| 243 | ||
| 244 | Mon May 4 17:59:11 1998 Frank Ch. Eigler <fche@cygnus.com> | |
| 245 | ||
| 246 | * config/default.exp: Added C compiler settings. | |
| 247 | ||
| 248 | Wed Apr 22 12:26:28 1998 Doug Evans <devans@canuck.cygnus.com> | |
| 249 | ||
| 250 | * Makefile.in (TARGET_FLAGS_TO_PASS): Delete LIBS, LDFLAGS. | |
| 251 | ||
| 252 | Tue Apr 21 10:49:03 1998 Doug Evans <devans@canuck.cygnus.com> | |
| 253 | ||
| 254 | * lib/sim-defs.exp (run_sim_test): Don't exit early if one mach fails, | |
| 255 | try all machs. | |
| 256 | ||
| 257 | * sim/m32r/addx.cgs: Test (-1)+(-1)+1. | |
| 258 | ||
| 259 | Fri Apr 17 16:00:52 1998 Doug Evans <devans@canuck.cygnus.com> | |
| 260 | ||
| 261 | * sim/m32r/mv[ft]achi.cgs: Fix expected result | |
| 262 | (sign extension of top 8 bits). | |
| 263 | ||
| 264 | Wed Feb 25 11:01:17 1998 Doug Evans <devans@canuck.cygnus.com> | |
| 265 | ||
| 266 | * Makefile.in (RUNTEST): Fix path to runtest. | |
| 267 | ||
| c906108c SS |
268 | Fri Feb 20 11:00:02 1998 Nick Clifton <nickc@cygnus.com> |
| 269 | ||
| 270 | * sim/m32r/unlock.cgs: Fixed test. | |
| 271 | * sim/m32r/mvfc.cgs: Fixed test. | |
| 272 | * sim/m32r/remu.cgs: Fixed test. | |
| c906108c SS |
273 | * sim/m32r/bnc24.cgs: Test long BNC instruction. |
| 274 | * sim/m32r/bnc8.cgs: Test short BNC instruction. | |
| 275 | * sim/m32r/ld-plus.cgs: Test LD instruction. | |
| 276 | * sim/m32r/macwhi.cgs: Test MACWHI instruction. | |
| 277 | * sim/m32r/macwlo.cgs: Test MACWLO instruction. | |
| 278 | * sim/m32r/mulwhi.cgs: Test MULWHI instruction. | |
| 279 | * sim/m32r/mulwlo.cgs: Test MULWLO instruction. | |
| 280 | * sim/m32r/mvfachi.cgs: Test MVFACHI instruction. | |
| 281 | * sim/m32r/mvfaclo.cgs: Test MVFACLO instruction. | |
| 282 | * sim/m32r/mvtaclo.cgs: Test MVTACLO instruction. | |
| 283 | * sim/m32r/addv.cgs: Test ADDV instruction. | |
| 284 | * sim/m32r/addv3.cgs: Test ADDV3 instruction. | |
| 285 | * sim/m32r/addx.cgs: Test ADDX instruction. | |
| 286 | * sim/m32r/lock.cgs: Test LOCK instruction. | |
| 287 | * sim/m32r/neg.cgs: Test NEG instruction. | |
| 288 | * sim/m32r/not.cgs: Test NOT instruction. | |
| 289 | * sim/m32r/unlock.cgs: Test UNLOCK instruction. | |
| 58fddbac | 290 | |
| c906108c SS |
291 | Thu Feb 19 11:15:45 1998 Nick Clifton <nickc@cygnus.com> |
| 292 | ||
| 293 | * sim/m32r/testutils.inc (mvaddr_h_gr): new macro to load an | |
| 294 | address into a general register. | |
| 295 | ||
| 296 | * sim/m32r/or3.cgs: Test OR3 instruction. | |
| 297 | * sim/m32r/rach.cgs: Test RACH instruction. | |
| 298 | * sim/m32r/rem.cgs: Test REM instruction. | |
| 299 | * sim/m32r/sub.cgs: Test SUB instruction. | |
| 300 | * sim/m32r/mv.cgs: Test MV instruction. | |
| 301 | * sim/m32r/mul.cgs: Test MUL instruction. | |
| 302 | * sim/m32r/bl24.cgs: Test long BL instruction. | |
| 303 | * sim/m32r/bl8.cgs: Test short BL instruction. | |
| 304 | * sim/m32r/blez.cgs: Test BLEZ instruction. | |
| 305 | * sim/m32r/bltz.cgs: Test BLTZ instruction. | |
| 306 | * sim/m32r/bne.cgs: Test BNE instruction. | |
| 307 | * sim/m32r/bnez.cgs: Test BNEZ instruction. | |
| 308 | * sim/m32r/bra24.cgs: Test long BRA instruction. | |
| 309 | * sim/m32r/bra8.cgs: Test short BRA instruction. | |
| 310 | * sim/m32r/jl.cgs: Test JL instruction. | |
| 311 | * sim/m32r/or.cgs: Test OR instruction. | |
| 312 | * sim/m32r/jmp.cgs: Test JMP instruction. | |
| 313 | * sim/m32r/and.cgs: Test AND instruction. | |
| 314 | * sim/m32r/and3.cgs: Test AND3 instruction. | |
| 315 | * sim/m32r/beq.cgs: Test BEQ instruction. | |
| 316 | * sim/m32r/beqz.cgs: Test BEQZ instruction. | |
| 317 | * sim/m32r/bgez.cgs: Test BGEZ instruction. | |
| 318 | * sim/m32r/bgtz.cgs: Test BGTZ instruction. | |
| 319 | * sim/m32r/cmp.cgs: Test CMP instruction. | |
| 320 | * sim/m32r/cmpi.cgs: Test CMPI instruction. | |
| 321 | * sim/m32r/cmpu.cgs: Test CMPU instruction. | |
| 322 | * sim/m32r/cmpui.cgs: Test CMPUI instruction. | |
| 323 | * sim/m32r/div.cgs: Test DIV instruction. | |
| 324 | * sim/m32r/divu.cgs: Test DIVU instruction. | |
| 325 | * sim/m32r/cmpeq.cgs: Test CMPEQ instruction. | |
| 326 | * sim/m32r/sll.cgs: Test SLL instruction. | |
| 327 | * sim/m32r/sll3.cgs: Test SLL3 instruction. | |
| 328 | * sim/m32r/slli.cgs: Test SLLI instruction. | |
| 329 | * sim/m32r/sra.cgs: Test SRA instruction. | |
| 330 | * sim/m32r/sra3.cgs: Test SRA3 instruction. | |
| 331 | * sim/m32r/srai.cgs: Test SRAI instruction. | |
| 332 | * sim/m32r/srl.cgs: Test SRL instruction. | |
| 333 | * sim/m32r/srl3.cgs: Test SRL3 instruction. | |
| 334 | * sim/m32r/srli.cgs: Test SRLI instruction. | |
| 335 | * sim/m32r/xor3.cgs: Test XOR3 instruction. | |
| 336 | * sim/m32r/xor.cgs: Test XOR instruction. | |
| 58fddbac | 337 | |
| c906108c SS |
338 | Tue Feb 17 12:46:05 1998 Doug Evans <devans@seba.cygnus.com> |
| 339 | ||
| 340 | * config/default.exp: New file. | |
| 341 | * lib/sim-defs.exp: New file. | |
| 342 | * sim/m32r/*: m32r dejagnu simulator testsuite. | |
| 343 | ||
| 344 | * Makefile.in (build_alias): Define. | |
| 345 | (arch): Define. | |
| 346 | (RUNTEST_FOR_TARGET): Delete. | |
| 347 | (RUNTEST): Fix. | |
| 348 | (check): Depend on site.exp. Run dejagnu. | |
| 349 | (site.exp): New target. | |
| 350 | * configure.in (arch): Define from target_cpu. | |
| 351 | * configure: Regenerate. | |
| 352 | ||
| 353 | Wed Sep 17 10:21:26 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 354 | ||
| 355 | * common/bits-gen.c (gen_bit): Pass in the full name of the macro. | |
| 356 | (gen_mask): Ditto. | |
| 357 | ||
| 358 | * common/bits-tst.c (main): Add tests for LSSEXT, MSSEXT. | |
| 359 | (calc): Add support for 8 bit version of macros. | |
| 360 | (main): Add tests for 8 bit versions of macros. | |
| 361 | (check_sext): Check SEXT of zero clears bits. | |
| 362 | ||
| 363 | * common/bits-gen.c (main): Generate tests for 8 bit versions of | |
| 364 | macros. | |
| 365 | ||
| 366 | Thu Sep 11 13:04:40 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 367 | ||
| 368 | * common/Make-common.in: New file, provide generic rules for | |
| 369 | running checks. | |
| 370 | ||
| 371 | Mon Sep 1 16:43:55 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 372 | ||
| 373 | * configure.in (configdirs): Test for the target directory instead | |
| 374 | of matching on a target. | |
| 375 |