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Implement .func/.endfunc pseudo-ops.
[deliverable/binutils-gdb.git] / sim / testsuite / ChangeLog
CommitLineData
496b3694
DE		 1start-sanitize-sky
2Mon May 18 10:37:47 1998 Doug Evans <devans@canuck.cygnus.com>
3
4 * sim/sky/sky.ld: Delete file.
5
6end-sanitize-sky
882d99e4
DE		 7start-sanitize-m32rx
8Fri May 15 17:31:15 1998 Doug Evans <devans@seba.cygnus.com>
9
10 * sim/m32r/allinsn.exp: Pass --m32rx-enable-special to gas.
11 * sim/m32r/misc.exp: Ditto.
12
13end-sanitize-m32rx
41ab9a4b
DE		 14Thu May 14 11:48:35 1998 Doug Evans <devans@canuck.cygnus.com>
15
90ef07f2 16 * config/default.exp (CC,SIM): Delete.
1461afc6 17start-sanitize-sky
02a0ec91 18 * sim/sky/sky-defs.tcl (LDSCRIPT,SIM): Delete.
90ef07f2
DE		 19 (run_trc_test): Use sim_compile, sim_run. Only delete temp files
20 if testcase passed.
21 (run_brn_test): Ditto.
1461afc6
DE		 22 * sim/sky/sky.exp: Add runtest_file_p support. Don't print
23 unsupported message if not sky.
24 * sim/sky/sky_sce.exp: Likewise.
1461afc6 25end-sanitize-sky
90ef07f2 26
41ab9a4b
DE		 27 * lib/sim-defs.exp (sim_run): Fix handling of output redirection.
28 New arg prog_opts. All callers updated.
29
30Fri May 8 18:10:28 1998 Jillian Ye <jillian@cygnus.com>
31
32 * Makefile.in: Made "check" the target of two
33 dependencies (test1, test2) so that test2 get a chance to
34 run even when test1 failed if "make -k check" is used.
35
801354e7
DE		 36Fri May 8 14:41:28 1998 Doug Evans <devans@canuck.cygnus.com>
37
38 * lib/sim-defs.exp (sim_version): Simplify.
39 (sim_run): Implement.
40 (run_sim_test): Use sim_run.
41 (sim_compile): New proc.
42
43Mon May 4 17:59:11 1998 Frank Ch. Eigler <fche@cygnus.com>
44
45start-sanitize-sky
46 * configure.in (testdir): Don't use old sky test directory.
47 * configure: Regenerated
48 * sky/Makefile.in: swallow stderr on buggy tests
49end-sanitize-sky
50 * config/default.exp: Added C compiler settings.
51
dca2d4f4
DE		 52Wed Apr 22 12:26:28 1998 Doug Evans <devans@canuck.cygnus.com>
53
54 * Makefile.in (TARGET_FLAGS_TO_PASS): Delete LIBS, LDFLAGS.
55
aa467704
DE		 56Tue Apr 21 10:49:03 1998 Doug Evans <devans@canuck.cygnus.com>
57
58 * lib/sim-defs.exp (run_sim_test): Don't exit early if one mach fails,
59 try all machs.
60
581fd042
DE		 61 * sim/m32r/addx.cgs: Test (-1)+(-1)+1.
62
aa467704
DE		 63Fri Apr 17 16:00:52 1998 Doug Evans <devans@canuck.cygnus.com>
64
65 * sim/m32r/mv[ft]achi.cgs: Fix expected result
66 (sign extension of top 8 bits).
67start-sanitize-m32rx
68 * sim/m32r/mv[ft]achi-a.cgs: Ditto.
69end-sanitize-m32rx
70
489564e2
DE		 71start-sanitize-m32rx
72Tue Apr 14 14:06:34 1998 Doug Evans <devans@canuck.cygnus.com>
73
74 * sim/m32r/maclh1.cgs: Fix testcase.
75 * sim/m32r/maclh1-2.cgs: New testcase.
76
77Tue Mar 3 19:09:09 1998 Doug Evans <devans@canuck.cygnus.com>
78
79 * sim/m32r/sat.cgs: Change sath to sat.
80
81end-sanitize-m32rx
9495a61e
DE		 82Wed Feb 25 11:01:17 1998 Doug Evans <devans@canuck.cygnus.com>
83
84 * Makefile.in (RUNTEST): Fix path to runtest.
85
559eba20
FCE		 86start-sanitize-sky
87Tue Feb 24 19:47:56 1998 Frank Ch. Eigler <fche@cygnus.com>
88
89 * configure.in (testdir): Added sky subdir for mips64r5900-sky-elf
90 target.
91 * configure: Regenerate.
92end-sanitize-sky
93
f83a90c4
NC		 94Fri Feb 20 11:00:02 1998 Nick Clifton <nickc@cygnus.com>
95
c801e51b 96 * sim/m32r/unlock.cgs: Fixed test.
ab361c35 97 * sim/m32r/mvfc.cgs: Fixed test.
78cbe8f6
NC		 98 * sim/m32r/remu.cgs: Fixed test.
99
caa71f09
NC		 100 * sim/m32r/bnc24.cgs: Test long BNC instruction.
101 * sim/m32r/bnc8.cgs: Test short BNC instruction.
102 * sim/m32r/ld-plus.cgs: Test LD instruction.
103 * sim/m32r/macwhi.cgs: Test MACWHI instruction.
104 * sim/m32r/macwlo.cgs: Test MACWLO instruction.
105 * sim/m32r/mulwhi.cgs: Test MULWHI instruction.
106 * sim/m32r/mulwlo.cgs: Test MULWLO instruction.
107 * sim/m32r/mvfachi.cgs: Test MVFACHI instruction.
108 * sim/m32r/mvfaclo.cgs: Test MVFACLO instruction.
109 * sim/m32r/mvtaclo.cgs: Test MVTACLO instruction.
f83a90c4
NC		 110 * sim/m32r/addv.cgs: Test ADDV instruction.
111 * sim/m32r/addv3.cgs: Test ADDV3 instruction.
112 * sim/m32r/addx.cgs: Test ADDX instruction.
113 * sim/m32r/lock.cgs: Test LOCK instruction.
114 * sim/m32r/neg.cgs: Test NEG instruction.
115 * sim/m32r/not.cgs: Test NOT instruction.
116 * sim/m32r/unlock.cgs: Test UNLOCK instruction.
caa71f09
NC		 117start-sanitize-m32rx
118 * sim/m32r/mvfachi-a.cgs: Test extended MVFACHI instruction.
aa467704 119 * sim/m32r/mvfaclo-a.cgs: Test extended MVFACLO instruction.
caa71f09
NC		 120 * sim/m32r/mvtachi-a.cgs: Test extended MVTACHI instruction.
121 * sim/m32r/mvtaclo-a.cgs: Test extended MVTACLO instruction.
122end-sanitize-m32rx
d03da19e
NC		 123Thu Feb 19 11:15:45 1998 Nick Clifton <nickc@cygnus.com>
124
e843e28b
NC		 125 * sim/m32r/testutils.inc (mvaddr_h_gr): new macro to load an
126 address into a general register.
127
c4448eec
NC		 128 * sim/m32r/or3.cgs: Test OR3 instruction.
129 * sim/m32r/rach.cgs: Test RACH instruction.
130 * sim/m32r/rem.cgs: Test REM instruction.
131 * sim/m32r/sub.cgs: Test SUB instruction.
132 * sim/m32r/mv.cgs: Test MV instruction.
133 * sim/m32r/mul.cgs: Test MUL instruction.
67dfe6e8
NC		 134 * sim/m32r/bl24.cgs: Test long BL instruction.
135 * sim/m32r/bl8.cgs: Test short BL instruction.
136 * sim/m32r/blez.cgs: Test BLEZ instruction.
137 * sim/m32r/bltz.cgs: Test BLTZ instruction.
138 * sim/m32r/bne.cgs: Test BNE instruction.
139 * sim/m32r/bnez.cgs: Test BNEZ instruction.
140 * sim/m32r/bra24.cgs: Test long BRA instruction.
141 * sim/m32r/bra8.cgs: Test short BRA instruction.
142 * sim/m32r/jl.cgs: Test JL instruction.
143 * sim/m32r/or.cgs: Test OR instruction.
144 * sim/m32r/jmp.cgs: Test JMP instruction.
dfe9df58
NC		 145 * sim/m32r/and.cgs: Test AND instruction.
146 * sim/m32r/and3.cgs: Test AND3 instruction.
147 * sim/m32r/beq.cgs: Test BEQ instruction.
148 * sim/m32r/beqz.cgs: Test BEQZ instruction.
149 * sim/m32r/bgez.cgs: Test BGEZ instruction.
150 * sim/m32r/bgtz.cgs: Test BGTZ instruction.
151 * sim/m32r/cmp.cgs: Test CMP instruction.
152 * sim/m32r/cmpi.cgs: Test CMPI instruction.
153 * sim/m32r/cmpu.cgs: Test CMPU instruction.
154 * sim/m32r/cmpui.cgs: Test CMPUI instruction.
155 * sim/m32r/div.cgs: Test DIV instruction.
67dfe6e8 156 * sim/m32r/divu.cgs: Test DIVU instruction.
dfe9df58 157 * sim/m32r/cmpeq.cgs: Test CMPEQ instruction.
dfe9df58
NC		 158 * sim/m32r/sll.cgs: Test SLL instruction.
159 * sim/m32r/sll3.cgs: Test SLL3 instruction.
160 * sim/m32r/slli.cgs: Test SLLI instruction.
0a2f6d93
NC		 161 * sim/m32r/sra.cgs: Test SRA instruction.
162 * sim/m32r/sra3.cgs: Test SRA3 instruction.
163 * sim/m32r/srai.cgs: Test SRAI instruction.
164 * sim/m32r/srl.cgs: Test SRL instruction.
165 * sim/m32r/srl3.cgs: Test SRL3 instruction.
166 * sim/m32r/srli.cgs: Test SRLI instruction.
167 * sim/m32r/xor3.cgs: Test XOR3 instruction.
168 * sim/m32r/xor.cgs: Test XOR instruction.
489564e2 169start-sanitize-m32rx
67dfe6e8
NC		 170 * sim/m32r/jnc.cgs: Test JNC instruction.
171 * sim/m32r/jc.cgs: Test JC instruction.
172 * sim/m32r/cmpz.cgs: Test CMPZ instruction.
173 * sim/m32r/bcl24.cgs: Test long version of BCL instruction
174 * sim/m32r/bcl8.cgs: Test short BCL instruction.
175 * sim/m32r/bncl24.cgs: Test long BNCL instruction.
176 * sim/m32r/bncl8.cgs: Test short BNCL instruction.
177 * sim/m32r/divh.cgs: Test DIVH instruction.
c4448eec 178 * sim/m32r/rach-dsi.cgs: Test extended RACH instruction.
489564e2 179end-sanitize-m32rx
ed063d52
DE		 180Tue Feb 17 12:46:05 1998 Doug Evans <devans@seba.cygnus.com>
181
fdad7ba5
DE		 182 * config/default.exp: New file.
183 * lib/sim-defs.exp: New file.
184 * sim/m32r/*: m32r dejagnu simulator testsuite.
185
ed063d52
DE		 186 * Makefile.in (build_alias): Define.
187 (arch): Define.
188 (RUNTEST_FOR_TARGET): Delete.
189 (RUNTEST): Fix.
d03da19e 190 (SCHEME,SCHEMEFLAGS,CGENDIR,CGENFLAGS): Define.
ed063d52
DE		 191 (check): Depend on site.exp. Run dejagnu.
192 (site.exp): New target.
193 (cgen): New target.
194 * configure.in: Call AC_CHECK_PROG(SCHEME) if using cgen.
195 (arch): Define from target_cpu.
196 * configure: Regenerate.
197
1a6eb36b
AC		 198Wed Sep 17 10:21:26 1997 Andrew Cagney <cagney@b1.cygnus.com>
199
200 * common/bits-gen.c (gen_bit): Pass in the full name of the macro.
201 (gen_mask): Ditto.
202
203 * common/bits-tst.c (main): Add tests for LSSEXT, MSSEXT.
204 (calc): Add support for 8 bit version of macros.
205 (main): Add tests for 8 bit versions of macros.
206 (check_sext): Check SEXT of zero clears bits.
207
208 * common/bits-gen.c (main): Generate tests for 8 bit versions of
209 macros.
210
a2ab5e65
AC		 211Thu Sep 11 13:04:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
212
213 * common/Make-common.in: New file, provide generic rules for
214 running checks.
215
52352d38
AC		 216Mon Sep 1 16:43:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
217
218 * configure.in (configdirs): Test for the target directory instead
219 of matching on a target.
220
ed063d52 221start-sanitize-r5900
52352d38
AC		 222Tue Jul 15 13:43:20 1997 Andrew Cagney <cagney@sendai.cygnus.com>
223
ed063d52 224 * configure.in (configdirs): Configure mips64vr5900el
52352d38
AC		 225 directory.
226 * configure: Regenerate.
227
ed063d52 228end-sanitize-r5900
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