projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| f83a90c4 NC |
1 | Fri Feb 20 11:00:02 1998 Nick Clifton <nickc@cygnus.com> |
| 2 | ||
| 78cbe8f6 NC |
3 | * sim/m32r/remu.cgs: Fixed test. |
| 4 | ||
| caa71f09 NC |
5 | * sim/m32r/bnc24.cgs: Test long BNC instruction. |
| 6 | * sim/m32r/bnc8.cgs: Test short BNC instruction. | |
| 7 | * sim/m32r/ld-plus.cgs: Test LD instruction. | |
| 8 | * sim/m32r/macwhi.cgs: Test MACWHI instruction. | |
| 9 | * sim/m32r/macwlo.cgs: Test MACWLO instruction. | |
| 10 | * sim/m32r/mulwhi.cgs: Test MULWHI instruction. | |
| 11 | * sim/m32r/mulwlo.cgs: Test MULWLO instruction. | |
| 12 | * sim/m32r/mvfachi.cgs: Test MVFACHI instruction. | |
| 13 | * sim/m32r/mvfaclo.cgs: Test MVFACLO instruction. | |
| 14 | * sim/m32r/mvtaclo.cgs: Test MVTACLO instruction. | |
| f83a90c4 NC |
15 | * sim/m32r/addv.cgs: Test ADDV instruction. |
| 16 | * sim/m32r/addv3.cgs: Test ADDV3 instruction. | |
| 17 | * sim/m32r/addx.cgs: Test ADDX instruction. | |
| 18 | * sim/m32r/lock.cgs: Test LOCK instruction. | |
| 19 | * sim/m32r/neg.cgs: Test NEG instruction. | |
| 20 | * sim/m32r/not.cgs: Test NOT instruction. | |
| 21 | * sim/m32r/unlock.cgs: Test UNLOCK instruction. | |
| caa71f09 NC |
22 | start-sanitize-m32rx |
| 23 | * sim/m32r/mvfachi-a.cgs: Test extended MVFACHI instruction. | |
| 24 | * sim/m32r/mvfaclo-a.cgs: Test extended MVFACLO.cgs instruction. | |
| 25 | * sim/m32r/mvtachi-a.cgs: Test extended MVTACHI instruction. | |
| 26 | * sim/m32r/mvtaclo-a.cgs: Test extended MVTACLO instruction. | |
| 27 | end-sanitize-m32rx | |
| d03da19e NC |
28 | Thu Feb 19 11:15:45 1998 Nick Clifton <nickc@cygnus.com> |
| 29 | ||
| e843e28b NC |
30 | * sim/m32r/testutils.inc (mvaddr_h_gr): new macro to load an |
| 31 | address into a general register. | |
| 32 | ||
| c4448eec NC |
33 | * sim/m32r/or3.cgs: Test OR3 instruction. |
| 34 | * sim/m32r/rach.cgs: Test RACH instruction. | |
| 35 | * sim/m32r/rem.cgs: Test REM instruction. | |
| 36 | * sim/m32r/sub.cgs: Test SUB instruction. | |
| 37 | * sim/m32r/mv.cgs: Test MV instruction. | |
| 38 | * sim/m32r/mul.cgs: Test MUL instruction. | |
| 67dfe6e8 NC |
39 | * sim/m32r/bl24.cgs: Test long BL instruction. |
| 40 | * sim/m32r/bl8.cgs: Test short BL instruction. | |
| 41 | * sim/m32r/blez.cgs: Test BLEZ instruction. | |
| 42 | * sim/m32r/bltz.cgs: Test BLTZ instruction. | |
| 43 | * sim/m32r/bne.cgs: Test BNE instruction. | |
| 44 | * sim/m32r/bnez.cgs: Test BNEZ instruction. | |
| 45 | * sim/m32r/bra24.cgs: Test long BRA instruction. | |
| 46 | * sim/m32r/bra8.cgs: Test short BRA instruction. | |
| 47 | * sim/m32r/jl.cgs: Test JL instruction. | |
| 48 | * sim/m32r/or.cgs: Test OR instruction. | |
| 49 | * sim/m32r/jmp.cgs: Test JMP instruction. | |
| dfe9df58 NC |
50 | * sim/m32r/and.cgs: Test AND instruction. |
| 51 | * sim/m32r/and3.cgs: Test AND3 instruction. | |
| 52 | * sim/m32r/beq.cgs: Test BEQ instruction. | |
| 53 | * sim/m32r/beqz.cgs: Test BEQZ instruction. | |
| 54 | * sim/m32r/bgez.cgs: Test BGEZ instruction. | |
| 55 | * sim/m32r/bgtz.cgs: Test BGTZ instruction. | |
| 56 | * sim/m32r/cmp.cgs: Test CMP instruction. | |
| 57 | * sim/m32r/cmpi.cgs: Test CMPI instruction. | |
| 58 | * sim/m32r/cmpu.cgs: Test CMPU instruction. | |
| 59 | * sim/m32r/cmpui.cgs: Test CMPUI instruction. | |
| 60 | * sim/m32r/div.cgs: Test DIV instruction. | |
| 67dfe6e8 | 61 | * sim/m32r/divu.cgs: Test DIVU instruction. |
| dfe9df58 | 62 | * sim/m32r/cmpeq.cgs: Test CMPEQ instruction. |
| dfe9df58 NC |
63 | * sim/m32r/sll.cgs: Test SLL instruction. |
| 64 | * sim/m32r/sll3.cgs: Test SLL3 instruction. | |
| 65 | * sim/m32r/slli.cgs: Test SLLI instruction. | |
| 0a2f6d93 NC |
66 | * sim/m32r/sra.cgs: Test SRA instruction. |
| 67 | * sim/m32r/sra3.cgs: Test SRA3 instruction. | |
| 68 | * sim/m32r/srai.cgs: Test SRAI instruction. | |
| 69 | * sim/m32r/srl.cgs: Test SRL instruction. | |
| 70 | * sim/m32r/srl3.cgs: Test SRL3 instruction. | |
| 71 | * sim/m32r/srli.cgs: Test SRLI instruction. | |
| 72 | * sim/m32r/xor3.cgs: Test XOR3 instruction. | |
| 73 | * sim/m32r/xor.cgs: Test XOR instruction. | |
| 67dfe6e8 NC |
74 | start-sanitize-m342rx |
| 75 | * sim/m32r/jnc.cgs: Test JNC instruction. | |
| 76 | * sim/m32r/jc.cgs: Test JC instruction. | |
| 77 | * sim/m32r/cmpz.cgs: Test CMPZ instruction. | |
| 78 | * sim/m32r/bcl24.cgs: Test long version of BCL instruction | |
| 79 | * sim/m32r/bcl8.cgs: Test short BCL instruction. | |
| 80 | * sim/m32r/bncl24.cgs: Test long BNCL instruction. | |
| 81 | * sim/m32r/bncl8.cgs: Test short BNCL instruction. | |
| 82 | * sim/m32r/divh.cgs: Test DIVH instruction. | |
| c4448eec | 83 | * sim/m32r/rach-dsi.cgs: Test extended RACH instruction. |
| 67dfe6e8 | 84 | end-sanitize-m342rx |
| ed063d52 DE |
85 | Tue Feb 17 12:46:05 1998 Doug Evans <devans@seba.cygnus.com> |
| 86 | ||
| fdad7ba5 DE |
87 | * config/default.exp: New file. |
| 88 | * lib/sim-defs.exp: New file. | |
| 89 | * sim/m32r/*: m32r dejagnu simulator testsuite. | |
| 90 | ||
| ed063d52 DE |
91 | * Makefile.in (build_alias): Define. |
| 92 | (arch): Define. | |
| 93 | (RUNTEST_FOR_TARGET): Delete. | |
| 94 | (RUNTEST): Fix. | |
| d03da19e | 95 | (SCHEME,SCHEMEFLAGS,CGENDIR,CGENFLAGS): Define. |
| ed063d52 DE |
96 | (check): Depend on site.exp. Run dejagnu. |
| 97 | (site.exp): New target. | |
| 98 | (cgen): New target. | |
| 99 | * configure.in: Call AC_CHECK_PROG(SCHEME) if using cgen. | |
| 100 | (arch): Define from target_cpu. | |
| 101 | * configure: Regenerate. | |
| 102 | ||
| 1a6eb36b AC |
103 | Wed Sep 17 10:21:26 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 104 | ||
| 105 | * common/bits-gen.c (gen_bit): Pass in the full name of the macro. | |
| 106 | (gen_mask): Ditto. | |
| 107 | ||
| 108 | * common/bits-tst.c (main): Add tests for LSSEXT, MSSEXT. | |
| 109 | (calc): Add support for 8 bit version of macros. | |
| 110 | (main): Add tests for 8 bit versions of macros. | |
| 111 | (check_sext): Check SEXT of zero clears bits. | |
| 112 | ||
| 113 | * common/bits-gen.c (main): Generate tests for 8 bit versions of | |
| 114 | macros. | |
| 115 | ||
| a2ab5e65 AC |
116 | Thu Sep 11 13:04:40 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 117 | ||
| 118 | * common/Make-common.in: New file, provide generic rules for | |
| 119 | running checks. | |
| 120 | ||
| 52352d38 AC |
121 | Mon Sep 1 16:43:55 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 122 | ||
| 123 | * configure.in (configdirs): Test for the target directory instead | |
| 124 | of matching on a target. | |
| 125 | ||
| ed063d52 | 126 | start-sanitize-r5900 |
| 52352d38 AC |
127 | Tue Jul 15 13:43:20 1997 Andrew Cagney <cagney@sendai.cygnus.com> |
| 128 | ||
| ed063d52 | 129 | * configure.in (configdirs): Configure mips64vr5900el |
| 52352d38 AC |
130 | directory. |
| 131 | * configure: Regenerate. | |
| 132 | ||
| ed063d52 | 133 | end-sanitize-r5900 |