Commit | Line | Data |
---|---|---|
aa467704 DE |
1 | Tue Apr 21 10:49:03 1998 Doug Evans <devans@canuck.cygnus.com> |
2 | ||
3 | * lib/sim-defs.exp (run_sim_test): Don't exit early if one mach fails, | |
4 | try all machs. | |
5 | ||
6 | Fri Apr 17 16:00:52 1998 Doug Evans <devans@canuck.cygnus.com> | |
7 | ||
8 | * sim/m32r/mv[ft]achi.cgs: Fix expected result | |
9 | (sign extension of top 8 bits). | |
10 | start-sanitize-m32rx | |
11 | * sim/m32r/mv[ft]achi-a.cgs: Ditto. | |
12 | end-sanitize-m32rx | |
13 | ||
489564e2 DE |
14 | start-sanitize-m32rx |
15 | Tue Apr 14 14:06:34 1998 Doug Evans <devans@canuck.cygnus.com> | |
16 | ||
17 | * sim/m32r/maclh1.cgs: Fix testcase. | |
18 | * sim/m32r/maclh1-2.cgs: New testcase. | |
19 | ||
20 | Tue Mar 3 19:09:09 1998 Doug Evans <devans@canuck.cygnus.com> | |
21 | ||
22 | * sim/m32r/sat.cgs: Change sath to sat. | |
23 | ||
24 | end-sanitize-m32rx | |
9495a61e DE |
25 | Wed Feb 25 11:01:17 1998 Doug Evans <devans@canuck.cygnus.com> |
26 | ||
27 | * Makefile.in (RUNTEST): Fix path to runtest. | |
28 | ||
559eba20 FCE |
29 | start-sanitize-sky |
30 | Tue Feb 24 19:47:56 1998 Frank Ch. Eigler <fche@cygnus.com> | |
31 | ||
32 | * configure.in (testdir): Added sky subdir for mips64r5900-sky-elf | |
33 | target. | |
34 | * configure: Regenerate. | |
35 | end-sanitize-sky | |
36 | ||
f83a90c4 NC |
37 | Fri Feb 20 11:00:02 1998 Nick Clifton <nickc@cygnus.com> |
38 | ||
c801e51b | 39 | * sim/m32r/unlock.cgs: Fixed test. |
ab361c35 | 40 | * sim/m32r/mvfc.cgs: Fixed test. |
78cbe8f6 NC |
41 | * sim/m32r/remu.cgs: Fixed test. |
42 | ||
caa71f09 NC |
43 | * sim/m32r/bnc24.cgs: Test long BNC instruction. |
44 | * sim/m32r/bnc8.cgs: Test short BNC instruction. | |
45 | * sim/m32r/ld-plus.cgs: Test LD instruction. | |
46 | * sim/m32r/macwhi.cgs: Test MACWHI instruction. | |
47 | * sim/m32r/macwlo.cgs: Test MACWLO instruction. | |
48 | * sim/m32r/mulwhi.cgs: Test MULWHI instruction. | |
49 | * sim/m32r/mulwlo.cgs: Test MULWLO instruction. | |
50 | * sim/m32r/mvfachi.cgs: Test MVFACHI instruction. | |
51 | * sim/m32r/mvfaclo.cgs: Test MVFACLO instruction. | |
52 | * sim/m32r/mvtaclo.cgs: Test MVTACLO instruction. | |
f83a90c4 NC |
53 | * sim/m32r/addv.cgs: Test ADDV instruction. |
54 | * sim/m32r/addv3.cgs: Test ADDV3 instruction. | |
55 | * sim/m32r/addx.cgs: Test ADDX instruction. | |
56 | * sim/m32r/lock.cgs: Test LOCK instruction. | |
57 | * sim/m32r/neg.cgs: Test NEG instruction. | |
58 | * sim/m32r/not.cgs: Test NOT instruction. | |
59 | * sim/m32r/unlock.cgs: Test UNLOCK instruction. | |
caa71f09 NC |
60 | start-sanitize-m32rx |
61 | * sim/m32r/mvfachi-a.cgs: Test extended MVFACHI instruction. | |
aa467704 | 62 | * sim/m32r/mvfaclo-a.cgs: Test extended MVFACLO instruction. |
caa71f09 NC |
63 | * sim/m32r/mvtachi-a.cgs: Test extended MVTACHI instruction. |
64 | * sim/m32r/mvtaclo-a.cgs: Test extended MVTACLO instruction. | |
65 | end-sanitize-m32rx | |
d03da19e NC |
66 | Thu Feb 19 11:15:45 1998 Nick Clifton <nickc@cygnus.com> |
67 | ||
e843e28b NC |
68 | * sim/m32r/testutils.inc (mvaddr_h_gr): new macro to load an |
69 | address into a general register. | |
70 | ||
c4448eec NC |
71 | * sim/m32r/or3.cgs: Test OR3 instruction. |
72 | * sim/m32r/rach.cgs: Test RACH instruction. | |
73 | * sim/m32r/rem.cgs: Test REM instruction. | |
74 | * sim/m32r/sub.cgs: Test SUB instruction. | |
75 | * sim/m32r/mv.cgs: Test MV instruction. | |
76 | * sim/m32r/mul.cgs: Test MUL instruction. | |
67dfe6e8 NC |
77 | * sim/m32r/bl24.cgs: Test long BL instruction. |
78 | * sim/m32r/bl8.cgs: Test short BL instruction. | |
79 | * sim/m32r/blez.cgs: Test BLEZ instruction. | |
80 | * sim/m32r/bltz.cgs: Test BLTZ instruction. | |
81 | * sim/m32r/bne.cgs: Test BNE instruction. | |
82 | * sim/m32r/bnez.cgs: Test BNEZ instruction. | |
83 | * sim/m32r/bra24.cgs: Test long BRA instruction. | |
84 | * sim/m32r/bra8.cgs: Test short BRA instruction. | |
85 | * sim/m32r/jl.cgs: Test JL instruction. | |
86 | * sim/m32r/or.cgs: Test OR instruction. | |
87 | * sim/m32r/jmp.cgs: Test JMP instruction. | |
dfe9df58 NC |
88 | * sim/m32r/and.cgs: Test AND instruction. |
89 | * sim/m32r/and3.cgs: Test AND3 instruction. | |
90 | * sim/m32r/beq.cgs: Test BEQ instruction. | |
91 | * sim/m32r/beqz.cgs: Test BEQZ instruction. | |
92 | * sim/m32r/bgez.cgs: Test BGEZ instruction. | |
93 | * sim/m32r/bgtz.cgs: Test BGTZ instruction. | |
94 | * sim/m32r/cmp.cgs: Test CMP instruction. | |
95 | * sim/m32r/cmpi.cgs: Test CMPI instruction. | |
96 | * sim/m32r/cmpu.cgs: Test CMPU instruction. | |
97 | * sim/m32r/cmpui.cgs: Test CMPUI instruction. | |
98 | * sim/m32r/div.cgs: Test DIV instruction. | |
67dfe6e8 | 99 | * sim/m32r/divu.cgs: Test DIVU instruction. |
dfe9df58 | 100 | * sim/m32r/cmpeq.cgs: Test CMPEQ instruction. |
dfe9df58 NC |
101 | * sim/m32r/sll.cgs: Test SLL instruction. |
102 | * sim/m32r/sll3.cgs: Test SLL3 instruction. | |
103 | * sim/m32r/slli.cgs: Test SLLI instruction. | |
0a2f6d93 NC |
104 | * sim/m32r/sra.cgs: Test SRA instruction. |
105 | * sim/m32r/sra3.cgs: Test SRA3 instruction. | |
106 | * sim/m32r/srai.cgs: Test SRAI instruction. | |
107 | * sim/m32r/srl.cgs: Test SRL instruction. | |
108 | * sim/m32r/srl3.cgs: Test SRL3 instruction. | |
109 | * sim/m32r/srli.cgs: Test SRLI instruction. | |
110 | * sim/m32r/xor3.cgs: Test XOR3 instruction. | |
111 | * sim/m32r/xor.cgs: Test XOR instruction. | |
489564e2 | 112 | start-sanitize-m32rx |
67dfe6e8 NC |
113 | * sim/m32r/jnc.cgs: Test JNC instruction. |
114 | * sim/m32r/jc.cgs: Test JC instruction. | |
115 | * sim/m32r/cmpz.cgs: Test CMPZ instruction. | |
116 | * sim/m32r/bcl24.cgs: Test long version of BCL instruction | |
117 | * sim/m32r/bcl8.cgs: Test short BCL instruction. | |
118 | * sim/m32r/bncl24.cgs: Test long BNCL instruction. | |
119 | * sim/m32r/bncl8.cgs: Test short BNCL instruction. | |
120 | * sim/m32r/divh.cgs: Test DIVH instruction. | |
c4448eec | 121 | * sim/m32r/rach-dsi.cgs: Test extended RACH instruction. |
489564e2 | 122 | end-sanitize-m32rx |
ed063d52 DE |
123 | Tue Feb 17 12:46:05 1998 Doug Evans <devans@seba.cygnus.com> |
124 | ||
fdad7ba5 DE |
125 | * config/default.exp: New file. |
126 | * lib/sim-defs.exp: New file. | |
127 | * sim/m32r/*: m32r dejagnu simulator testsuite. | |
128 | ||
ed063d52 DE |
129 | * Makefile.in (build_alias): Define. |
130 | (arch): Define. | |
131 | (RUNTEST_FOR_TARGET): Delete. | |
132 | (RUNTEST): Fix. | |
d03da19e | 133 | (SCHEME,SCHEMEFLAGS,CGENDIR,CGENFLAGS): Define. |
ed063d52 DE |
134 | (check): Depend on site.exp. Run dejagnu. |
135 | (site.exp): New target. | |
136 | (cgen): New target. | |
137 | * configure.in: Call AC_CHECK_PROG(SCHEME) if using cgen. | |
138 | (arch): Define from target_cpu. | |
139 | * configure: Regenerate. | |
140 | ||
1a6eb36b AC |
141 | Wed Sep 17 10:21:26 1997 Andrew Cagney <cagney@b1.cygnus.com> |
142 | ||
143 | * common/bits-gen.c (gen_bit): Pass in the full name of the macro. | |
144 | (gen_mask): Ditto. | |
145 | ||
146 | * common/bits-tst.c (main): Add tests for LSSEXT, MSSEXT. | |
147 | (calc): Add support for 8 bit version of macros. | |
148 | (main): Add tests for 8 bit versions of macros. | |
149 | (check_sext): Check SEXT of zero clears bits. | |
150 | ||
151 | * common/bits-gen.c (main): Generate tests for 8 bit versions of | |
152 | macros. | |
153 | ||
a2ab5e65 AC |
154 | Thu Sep 11 13:04:40 1997 Andrew Cagney <cagney@b1.cygnus.com> |
155 | ||
156 | * common/Make-common.in: New file, provide generic rules for | |
157 | running checks. | |
158 | ||
52352d38 AC |
159 | Mon Sep 1 16:43:55 1997 Andrew Cagney <cagney@b1.cygnus.com> |
160 | ||
161 | * configure.in (configdirs): Test for the target directory instead | |
162 | of matching on a target. | |
163 | ||
ed063d52 | 164 | start-sanitize-r5900 |
52352d38 AC |
165 | Tue Jul 15 13:43:20 1997 Andrew Cagney <cagney@sendai.cygnus.com> |
166 | ||
ed063d52 | 167 | * configure.in (configdirs): Configure mips64vr5900el |
52352d38 AC |
168 | directory. |
169 | * configure: Regenerate. | |
170 | ||
ed063d52 | 171 | end-sanitize-r5900 |