projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| f83a90c4 NC |
1 | Fri Feb 20 11:00:02 1998 Nick Clifton <nickc@cygnus.com> |
| 2 | ||
| 3 | * sim/m32r/addv.cgs: Test ADDV instruction. | |
| 4 | * sim/m32r/addv3.cgs: Test ADDV3 instruction. | |
| 5 | * sim/m32r/addx.cgs: Test ADDX instruction. | |
| 6 | * sim/m32r/lock.cgs: Test LOCK instruction. | |
| 7 | * sim/m32r/neg.cgs: Test NEG instruction. | |
| 8 | * sim/m32r/not.cgs: Test NOT instruction. | |
| 9 | * sim/m32r/unlock.cgs: Test UNLOCK instruction. | |
| 10 | ||
| d03da19e NC |
11 | Thu Feb 19 11:15:45 1998 Nick Clifton <nickc@cygnus.com> |
| 12 | ||
| e843e28b NC |
13 | * sim/m32r/testutils.inc (mvaddr_h_gr): new macro to load an |
| 14 | address into a general register. | |
| 15 | ||
| c4448eec NC |
16 | * sim/m32r/or3.cgs: Test OR3 instruction. |
| 17 | * sim/m32r/rach.cgs: Test RACH instruction. | |
| 18 | * sim/m32r/rem.cgs: Test REM instruction. | |
| 19 | * sim/m32r/sub.cgs: Test SUB instruction. | |
| 20 | * sim/m32r/mv.cgs: Test MV instruction. | |
| 21 | * sim/m32r/mul.cgs: Test MUL instruction. | |
| 67dfe6e8 NC |
22 | * sim/m32r/bl24.cgs: Test long BL instruction. |
| 23 | * sim/m32r/bl8.cgs: Test short BL instruction. | |
| 24 | * sim/m32r/blez.cgs: Test BLEZ instruction. | |
| 25 | * sim/m32r/bltz.cgs: Test BLTZ instruction. | |
| 26 | * sim/m32r/bne.cgs: Test BNE instruction. | |
| 27 | * sim/m32r/bnez.cgs: Test BNEZ instruction. | |
| 28 | * sim/m32r/bra24.cgs: Test long BRA instruction. | |
| 29 | * sim/m32r/bra8.cgs: Test short BRA instruction. | |
| 30 | * sim/m32r/jl.cgs: Test JL instruction. | |
| 31 | * sim/m32r/or.cgs: Test OR instruction. | |
| 32 | * sim/m32r/jmp.cgs: Test JMP instruction. | |
| dfe9df58 NC |
33 | * sim/m32r/and.cgs: Test AND instruction. |
| 34 | * sim/m32r/and3.cgs: Test AND3 instruction. | |
| 35 | * sim/m32r/beq.cgs: Test BEQ instruction. | |
| 36 | * sim/m32r/beqz.cgs: Test BEQZ instruction. | |
| 37 | * sim/m32r/bgez.cgs: Test BGEZ instruction. | |
| 38 | * sim/m32r/bgtz.cgs: Test BGTZ instruction. | |
| 39 | * sim/m32r/cmp.cgs: Test CMP instruction. | |
| 40 | * sim/m32r/cmpi.cgs: Test CMPI instruction. | |
| 41 | * sim/m32r/cmpu.cgs: Test CMPU instruction. | |
| 42 | * sim/m32r/cmpui.cgs: Test CMPUI instruction. | |
| 43 | * sim/m32r/div.cgs: Test DIV instruction. | |
| 67dfe6e8 | 44 | * sim/m32r/divu.cgs: Test DIVU instruction. |
| dfe9df58 | 45 | * sim/m32r/cmpeq.cgs: Test CMPEQ instruction. |
| dfe9df58 NC |
46 | * sim/m32r/sll.cgs: Test SLL instruction. |
| 47 | * sim/m32r/sll3.cgs: Test SLL3 instruction. | |
| 48 | * sim/m32r/slli.cgs: Test SLLI instruction. | |
| 0a2f6d93 NC |
49 | * sim/m32r/sra.cgs: Test SRA instruction. |
| 50 | * sim/m32r/sra3.cgs: Test SRA3 instruction. | |
| 51 | * sim/m32r/srai.cgs: Test SRAI instruction. | |
| 52 | * sim/m32r/srl.cgs: Test SRL instruction. | |
| 53 | * sim/m32r/srl3.cgs: Test SRL3 instruction. | |
| 54 | * sim/m32r/srli.cgs: Test SRLI instruction. | |
| 55 | * sim/m32r/xor3.cgs: Test XOR3 instruction. | |
| 56 | * sim/m32r/xor.cgs: Test XOR instruction. | |
| 67dfe6e8 NC |
57 | start-sanitize-m342rx |
| 58 | * sim/m32r/jnc.cgs: Test JNC instruction. | |
| 59 | * sim/m32r/jc.cgs: Test JC instruction. | |
| 60 | * sim/m32r/cmpz.cgs: Test CMPZ instruction. | |
| 61 | * sim/m32r/bcl24.cgs: Test long version of BCL instruction | |
| 62 | * sim/m32r/bcl8.cgs: Test short BCL instruction. | |
| 63 | * sim/m32r/bncl24.cgs: Test long BNCL instruction. | |
| 64 | * sim/m32r/bncl8.cgs: Test short BNCL instruction. | |
| 65 | * sim/m32r/divh.cgs: Test DIVH instruction. | |
| c4448eec | 66 | * sim/m32r/rach-dsi.cgs: Test extended RACH instruction. |
| 67dfe6e8 | 67 | end-sanitize-m342rx |
| ed063d52 DE |
68 | Tue Feb 17 12:46:05 1998 Doug Evans <devans@seba.cygnus.com> |
| 69 | ||
| fdad7ba5 DE |
70 | * config/default.exp: New file. |
| 71 | * lib/sim-defs.exp: New file. | |
| 72 | * sim/m32r/*: m32r dejagnu simulator testsuite. | |
| 73 | ||
| ed063d52 DE |
74 | * Makefile.in (build_alias): Define. |
| 75 | (arch): Define. | |
| 76 | (RUNTEST_FOR_TARGET): Delete. | |
| 77 | (RUNTEST): Fix. | |
| d03da19e | 78 | (SCHEME,SCHEMEFLAGS,CGENDIR,CGENFLAGS): Define. |
| ed063d52 DE |
79 | (check): Depend on site.exp. Run dejagnu. |
| 80 | (site.exp): New target. | |
| 81 | (cgen): New target. | |
| 82 | * configure.in: Call AC_CHECK_PROG(SCHEME) if using cgen. | |
| 83 | (arch): Define from target_cpu. | |
| 84 | * configure: Regenerate. | |
| 85 | ||
| 1a6eb36b AC |
86 | Wed Sep 17 10:21:26 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 87 | ||
| 88 | * common/bits-gen.c (gen_bit): Pass in the full name of the macro. | |
| 89 | (gen_mask): Ditto. | |
| 90 | ||
| 91 | * common/bits-tst.c (main): Add tests for LSSEXT, MSSEXT. | |
| 92 | (calc): Add support for 8 bit version of macros. | |
| 93 | (main): Add tests for 8 bit versions of macros. | |
| 94 | (check_sext): Check SEXT of zero clears bits. | |
| 95 | ||
| 96 | * common/bits-gen.c (main): Generate tests for 8 bit versions of | |
| 97 | macros. | |
| 98 | ||
| a2ab5e65 AC |
99 | Thu Sep 11 13:04:40 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 100 | ||
| 101 | * common/Make-common.in: New file, provide generic rules for | |
| 102 | running checks. | |
| 103 | ||
| 52352d38 AC |
104 | Mon Sep 1 16:43:55 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 105 | ||
| 106 | * configure.in (configdirs): Test for the target directory instead | |
| 107 | of matching on a target. | |
| 108 | ||
| ed063d52 | 109 | start-sanitize-r5900 |
| 52352d38 AC |
110 | Tue Jul 15 13:43:20 1997 Andrew Cagney <cagney@sendai.cygnus.com> |
| 111 | ||
| ed063d52 | 112 | * configure.in (configdirs): Configure mips64vr5900el |
| 52352d38 AC |
113 | directory. |
| 114 | * configure: Regenerate. | |
| 115 | ||
| ed063d52 | 116 | end-sanitize-r5900 |