projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 1d7b4a70 MF |
1 | # mach: bfin |
| 2 | ||
| 3 | #include "test.h" | |
| 4 | .include "testutils.inc" | |
| 5 | start | |
| 6 | ||
| 7 | // 0xfffffe371c | |
| 8 | r0 = 0; | |
| 9 | r1 = 0; | |
| 10 | r2 = 0; | |
| 11 | r3 = 0; | |
| 12 | r4 = 0; | |
| 13 | r5 = 0; | |
| 14 | r6 = 0; | |
| 15 | r7 = 0; | |
| 16 | a1 = a0 =0; | |
| 17 | astat = R0; | |
| 18 | ||
| 19 | R6.L = 0x8000; | |
| 20 | R5.H = 0x8000; | |
| 21 | ||
| 22 | // load acc with values; | |
| 23 | R0.L = 0xc062; | |
| 24 | R0.H = 0xffee; | |
| 25 | A0.w = R0; | |
| 26 | R0.L = 0xc52c; | |
| 27 | A0.x = R0; | |
| 28 | R0.L = 0x8d10; | |
| 29 | R0.H = 0x34c; | |
| 30 | A1.w = R0; | |
| 31 | R0.L = 0xe10c; | |
| 32 | A1.x = R0; | |
| 33 | // load regs with values; | |
| 34 | R0.L = 0xe844; | |
| 35 | R0.H = 0x4aba; | |
| 36 | R1.L = 0xa294; | |
| 37 | R1.H = 0x52ea; | |
| 38 | R2.L = 0xafda; | |
| 39 | R2.H = 0x5c32; | |
| 40 | // end load regs and acc; | |
| 41 | R0.H = (A1 = R5.L * R6.H), R0.L = (A0 += R5.L * R6.H) (FU); | |
| 42 | P0 = ASTAT; | |
| 43 | CHECKREG P0, (_VS|_V|_V_COPY); | |
| 44 | ||
| 45 | CHECKREG R0, 0xffff; | |
| 46 | R0 = A1.w | |
| 47 | CHECKREG R0, 0; | |
| 48 | R0 = A1.x | |
| 49 | CHECKREG R0, 0; | |
| 50 | R0 = A0.w | |
| 51 | CHECKREG R0, 0xffeec062; | |
| 52 | R0 = A0.x | |
| 53 | CHECKREG R0, 0x2c; | |
| 54 | P0 = ASTAT; | |
| 55 | CHECKREG P0, (_VS|_V|_V_COPY); | |
| 56 | R4 = R6 +|- R5 , R3 = R6 -|+ R5; | |
| 57 | CHECKREG R3, 0x80008000; | |
| 58 | CHECKREG R4, 0x80008000; | |
| 59 | P0 = ASTAT; | |
| 60 | CHECKREG P0, (_VS|_V|_V_COPY|_AN); | |
| 61 | A1 = R7.L * R2.L (M), A0 -= R7.L * R2.H (IS); | |
| 62 | P0 = ASTAT; | |
| 63 | CHECKREG P0, (_VS|_V|_V_COPY|_AN); | |
| 64 | R7.H = R1.H * R3.L (TFU); | |
| 65 | CHECKREG R7, 0x29750000; | |
| 66 | P0 = ASTAT; | |
| 67 | CHECKREG P0, (_VS|_AN); | |
| 68 | R7.H = ( A1 -= R2.L * R5.H ), A0 = R2.L * R5.H; | |
| 69 | CHECKREG R7, 0xafda0000; | |
| 70 | R0 = A1.w | |
| 71 | CHECKREG R0, 0xafda0000; | |
| 72 | R0 = A1.x | |
| 73 | CHECKREG R0, 0xffffffff; | |
| 74 | R0 = A0.w | |
| 75 | CHECKREG R0, 0x50260000; | |
| 76 | R0 = A0.x | |
| 77 | CHECKREG R0, 0x0; | |
| 78 | P0 = ASTAT; | |
| 79 | CHECKREG P0, (_VS|_AN); | |
| 80 | R3 = R7.L * R6.H, R2 = R7.L * R6.H (IS); | |
| 81 | CHECKREG R3, 0; | |
| 82 | CHECKREG R2, 0; | |
| 83 | P0 = ASTAT; | |
| 84 | CHECKREG P0, (_VS|_AN); | |
| 85 | R1.H = (A1 += R7.L * R4.H) (M), R1.L = (A0 = R7.H * R4.H) (FU); | |
| 86 | CHECKREG R1, 0xafda57ed; | |
| 87 | P0 = ASTAT; | |
| 88 | R0 = A1.w | |
| 89 | CHECKREG R0, 0xafda0000; | |
| 90 | R0 = A1.x | |
| 91 | CHECKREG R0, 0xffffffff; | |
| 92 | R0 = A0.w | |
| 93 | CHECKREG R0, 0x57ed0000; | |
| 94 | R0 = A0.x | |
| 95 | CHECKREG R0, 0x0; | |
| 96 | CHECKREG P0, (_VS|_AN); | |
| 97 | R3 = R6.H * R5.L (FU); | |
| 98 | CHECKREG R3, 0; | |
| 99 | P0 = ASTAT; | |
| 100 | CHECKREG P0, (_VS|_AN); | |
| 101 | R5.H = ( A1 += R3.L * R1.L ) (M), A0 -= R3.H * R1.H (ISS2); | |
| 102 | CHECKREG R5, 0x80000000; | |
| 103 | R0 = A1.w | |
| 104 | CHECKREG R0, 0xafda0000; | |
| 105 | R0 = A1.x | |
| 106 | CHECKREG R0, 0xffffffff; | |
| 107 | R0 = A0.w | |
| 108 | CHECKREG R0, 0x57ed0000; | |
| 109 | R0 = A0.x | |
| 110 | CHECKREG R0, 0x0; | |
| 111 | P0 = ASTAT; | |
| 112 | CHECKREG P0, (_VS|_V|_V_COPY|_AN); | |
| 113 | R3 = R3 +|- R5 , R6 = R3 -|+ R5 (CO); | |
| 114 | CHECKREG R3, 0x80000000; | |
| 115 | CHECKREG R6, 0x00008000; | |
| 116 | P0 = ASTAT; | |
| 117 | CHECKREG P0, (_VS|_V|_V_COPY|_AN|_AZ); | |
| 118 | R7 = ( A1 += R4.L * R1.L ) (M), R6 = ( A0 += R4.L * R1.H ); | |
| 119 | R0 = A1.w | |
| 120 | CHECKREG R0, 0x83e38000; | |
| 121 | R0 = A1.x | |
| 122 | CHECKREG R0, 0xffffffff; | |
| 123 | R0 = A0.w | |
| 124 | CHECKREG R0, 0xa8130000; | |
| 125 | R0 = A0.x | |
| 126 | CHECKREG R0, 0x0; | |
| 127 | CHECKREG R6, 0x7fffffff | |
| 128 | CHECKREG R7, 0x83e38000 | |
| 129 | P0 = ASTAT; | |
| 130 | CHECKREG P0, (_VS|_V|_V_COPY|_AN|_AZ); | |
| 131 | IF CC P2 = R1; | |
| 132 | R2.H = (A1 = R7.L * R5.H) (M), R2.L = (A0 = R7.L * R5.H) (ISS2); | |
| 133 | CHECKREG R2, 0x80007fff | |
| 134 | P0 = ASTAT; | |
| 135 | CHECKREG P0, (_VS|_V|_V_COPY|_AN|_AZ); | |
| 136 | R3.H = R4.H * R2.H, R3.L = R4.L * R2.L (T); | |
| 137 | CHECKREG R3, 0x7fff8001 | |
| 138 | P0 = ASTAT; | |
| 139 | CHECKREG P0, (_VS|_V|_V_COPY|_AN|_AZ); | |
| 140 | R7 = ( A1 = R7.H * R1.H ) (M), A0 -= R7.H * R1.H (FU); | |
| 141 | CHECKREG R7, 0xaabe7c4e | |
| 142 | P0 = ASTAT; | |
| 143 | CHECKREG P0, (_VS|_AV0S|_AV0|_AN|_AZ); | |
| 144 | R0.H = R7.L * R4.H (M), R0.L = R7.L * R4.H (TFU); | |
| 145 | CHECKREG R0, 0x3e273e27 | |
| 146 | P0 = ASTAT; | |
| 147 | CHECKREG P0, (_VS|_AV0S|_AV0|_AN|_AZ); | |
| 148 | R5 = ( A1 = R7.L * R7.L ), R4 = ( A0 -= R7.H * R7.H ) (ISS2); | |
| 149 | CHECKREG R5, 0x78b74f88 | |
| 150 | CHECKREG R4, 0xc73635f8 | |
| 151 | R0 = A1.w | |
| 152 | CHECKREG R0, 0x3c5ba7c4; | |
| 153 | R0 = A1.x | |
| 154 | CHECKREG R0, 0x0; | |
| 155 | R0 = A0.w | |
| 156 | CHECKREG R0, 0xe39b1afc; | |
| 157 | R0 = A0.x | |
| 158 | CHECKREG R0, 0xffffffff; | |
| 159 | R0 = ASTAT; | |
| 160 | CHECKREG r0, (_VS|_AV0S|_AZ|_AN); | |
| 161 | A0 = A0 >> 2; | |
| 162 | R0 = ASTAT; | |
| 163 | checkreg r0, (_VS|_AV0S); | |
| 164 | R0 = A0.x; | |
| 165 | DBGA (R0.L, 0x3f); | |
| 166 | R0 = A0.w; | |
| 167 | checkreg r0, 0xF8E6C6BF; | |
| 168 | ||
| 169 | pass |