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1d7b4a70 MF |
1 | //Original:/testcases/core/c_dsp32alu_rrpmmp/c_dsp32alu_rrpmmp.dsp |
2 | // Spec Reference: dsp32alu (dreg, dreg) = +/-, -/+ (dreg, dreg) amod0 | |
3 | # mach: bfin | |
4 | ||
5 | .include "testutils.inc" | |
6 | start | |
7 | ||
8 | ||
9 | ||
10 | ||
11 | imm32 r0, 0x35678911; | |
12 | imm32 r1, 0x2489ab1d; | |
13 | imm32 r2, 0x34545515; | |
14 | imm32 r3, 0x46667717; | |
15 | imm32 r0, 0x5567891b; | |
16 | imm32 r1, 0x67889b1d; | |
17 | imm32 r2, 0x74445915; | |
18 | imm32 r3, 0x86667797; | |
19 | R0 = R0 +|- R0 , R7 = R0 -|+ R0; | |
20 | R1 = R0 +|- R1 , R6 = R0 -|+ R1; | |
21 | R2 = R0 +|- R2 , R5 = R0 -|+ R2; | |
22 | R3 = R0 +|- R3 , R4 = R0 -|+ R3; | |
23 | R4 = R0 +|- R4 , R3 = R0 -|+ R4; | |
24 | R5 = R0 +|- R5 , R2 = R0 -|+ R5; | |
25 | R6 = R0 +|- R6 , R1 = R0 -|+ R6; | |
26 | R7 = R0 +|- R7 , R0 = R0 -|+ R7; | |
27 | CHECKREG r0, 0xAACE1236; | |
28 | CHECKREG r1, 0x67889B1D; | |
29 | CHECKREG r2, 0x74445915; | |
30 | CHECKREG r3, 0x86667797; | |
31 | CHECKREG r4, 0xCF368869; | |
32 | CHECKREG r5, 0xE158A6EB; | |
33 | CHECKREG r6, 0xEE1464E3; | |
34 | CHECKREG r7, 0xAACEEDCA; | |
35 | ||
36 | imm32 r0, 0xe5678911; | |
37 | imm32 r1, 0x2e89ab1d; | |
38 | imm32 r2, 0x34e45515; | |
39 | imm32 r3, 0x466e7717; | |
40 | imm32 r0, 0x5567ee1b; | |
41 | imm32 r1, 0x6789abed; | |
42 | imm32 r2, 0x7444551e; | |
43 | imm32 r3, 0x86e67777; | |
44 | R0 = R1 +|- R0 , R7 = R1 -|+ R0; | |
45 | R1 = R1 +|- R1 , R6 = R1 -|+ R1; | |
46 | R2 = R1 +|- R2 , R5 = R1 -|+ R2; | |
47 | R3 = R1 +|- R3 , R4 = R1 -|+ R3; | |
48 | R4 = R1 +|- R4 , R3 = R1 -|+ R4; | |
49 | R5 = R1 +|- R5 , R2 = R1 -|+ R5; | |
50 | R6 = R1 +|- R6 , R1 = R1 -|+ R6; | |
51 | R7 = R1 +|- R7 , R0 = R1 -|+ R7; | |
52 | CHECKREG r0, 0xBCF0F1E2; | |
53 | CHECKREG r1, 0xCF1257DA; | |
54 | CHECKREG r2, 0x7444551E; | |
55 | CHECKREG r3, 0x86E67777; | |
56 | CHECKREG r4, 0x173E8889; | |
57 | CHECKREG r5, 0x29E0AAE2; | |
58 | CHECKREG r6, 0xCF12A826; | |
59 | CHECKREG r7, 0xE134BDD2; | |
60 | ||
61 | imm32 r0, 0x15678911; | |
62 | imm32 r1, 0x2789ab1d; | |
63 | imm32 r2, 0x34445515; | |
64 | imm32 r3, 0x46667717; | |
65 | imm32 r0, 0x5567891b; | |
66 | imm32 r1, 0x6789ab1d; | |
67 | imm32 r2, 0x74445515; | |
68 | imm32 r3, 0x86667777; | |
69 | R0 = R2 +|- R0 , R7 = R2 -|+ R0; | |
70 | R1 = R2 +|- R1 , R6 = R2 -|+ R1; | |
71 | R2 = R2 +|- R2 , R5 = R2 -|+ R2; | |
72 | R3 = R2 +|- R3 , R4 = R2 -|+ R3; | |
73 | R4 = R2 +|- R4 , R3 = R2 -|+ R4; | |
74 | R5 = R2 +|- R5 , R2 = R2 -|+ R5; | |
75 | R6 = R2 +|- R6 , R1 = R2 -|+ R6; | |
76 | R7 = R2 +|- R7 , R0 = R2 -|+ R7; | |
77 | CHECKREG r0, 0xC9AB885A; | |
78 | CHECKREG r1, 0xDBCDAA5C; | |
79 | CHECKREG r2, 0xE888AA2A; | |
80 | CHECKREG r3, 0x86667777; | |
81 | CHECKREG r4, 0x4AAA8889; | |
82 | CHECKREG r5, 0xE88855D6; | |
83 | CHECKREG r6, 0xF543A9F8; | |
84 | CHECKREG r7, 0x0765CBFA; | |
85 | ||
86 | imm32 r0, 0x85678911; | |
87 | imm32 r1, 0x2889ab1d; | |
88 | imm32 r2, 0x34445515; | |
89 | imm32 r3, 0x46667717; | |
90 | imm32 r0, 0x5587891b; | |
91 | imm32 r1, 0x6788ab1d; | |
92 | imm32 r2, 0x74448515; | |
93 | imm32 r3, 0x86667877; | |
94 | R0 = R3 +|- R0 , R7 = R3 -|+ R0; | |
95 | R1 = R3 +|- R1 , R6 = R3 -|+ R1; | |
96 | R2 = R3 +|- R2 , R5 = R3 -|+ R2; | |
97 | R3 = R3 +|- R3 , R4 = R3 -|+ R3; | |
98 | R4 = R3 +|- R4 , R3 = R3 -|+ R4; | |
99 | R5 = R3 +|- R5 , R2 = R3 -|+ R5; | |
100 | R6 = R3 +|- R6 , R1 = R3 -|+ R6; | |
101 | R7 = R3 +|- R7 , R0 = R3 -|+ R7; | |
102 | CHECKREG r0, 0xDBEDF280; | |
103 | CHECKREG r1, 0xEDEE1482; | |
104 | CHECKREG r2, 0xFAAAEE7A; | |
105 | CHECKREG r3, 0x0CCCF0EE; | |
106 | CHECKREG r4, 0x0CCC0F12; | |
107 | CHECKREG r5, 0x1EEEF362; | |
108 | CHECKREG r6, 0x2BAACD5A; | |
109 | CHECKREG r7, 0x3DABEF5C; | |
110 | ||
111 | imm32 r0, 0x15678911; | |
112 | imm32 r1, 0x2789ab1d; | |
113 | imm32 r2, 0x34445515; | |
114 | imm32 r3, 0x46667717; | |
115 | imm32 r0, 0x5567891b; | |
116 | imm32 r1, 0x6789ab1d; | |
117 | imm32 r2, 0x74445515; | |
118 | imm32 r3, 0x86667777; | |
119 | R0 = R4 +|- R0 , R7 = R4 -|+ R0; | |
120 | R1 = R4 +|- R1 , R6 = R4 -|+ R1; | |
121 | R2 = R4 +|- R2 , R5 = R4 -|+ R2; | |
122 | R3 = R4 +|- R3 , R4 = R4 -|+ R3; | |
123 | R4 = R4 +|- R4 , R3 = R4 -|+ R4; | |
124 | R5 = R4 +|- R5 , R2 = R4 -|+ R5; | |
125 | R6 = R4 +|- R6 , R1 = R4 -|+ R6; | |
126 | R7 = R4 +|- R7 , R0 = R4 -|+ R7; | |
127 | CHECKREG r0, 0x5567982D; | |
128 | CHECKREG r1, 0x6789BA2F; | |
129 | CHECKREG r2, 0x74446427; | |
130 | CHECKREG r3, 0x00000D12; | |
131 | CHECKREG r4, 0x0CCC0000; | |
132 | CHECKREG r5, 0xA5549BD9; | |
133 | CHECKREG r6, 0xB20F45D1; | |
134 | CHECKREG r7, 0xC43167D3; | |
135 | ||
136 | imm32 r0, 0x95678911; | |
137 | imm32 r1, 0x2789ab1d; | |
138 | imm32 r2, 0x39445515; | |
139 | imm32 r3, 0x46967717; | |
140 | imm32 r0, 0x5567891b; | |
141 | imm32 r1, 0x6789ab1d; | |
142 | imm32 r2, 0x74495515; | |
143 | imm32 r3, 0x86669777; | |
144 | R0 = R5 +|- R0 , R7 = R5 -|+ R0; | |
145 | R1 = R5 +|- R1 , R6 = R5 -|+ R1; | |
146 | R2 = R5 +|- R2 , R5 = R5 -|+ R2; | |
147 | R3 = R5 +|- R3 , R4 = R5 -|+ R3; | |
148 | R4 = R5 +|- R4 , R3 = R5 -|+ R4; | |
149 | R5 = R5 +|- R5 , R2 = R5 -|+ R5; | |
150 | R6 = R5 +|- R6 , R1 = R5 -|+ R6; | |
151 | R7 = R5 +|- R7 , R0 = R5 -|+ R7; | |
152 | CHECKREG r0, 0x122924F4; | |
153 | CHECKREG r1, 0x244B46F6; | |
154 | CHECKREG r2, 0x0000E1DC; | |
155 | CHECKREG r3, 0x86667953; | |
156 | CHECKREG r4, 0xDBB06889; | |
157 | CHECKREG r5, 0x62160000; | |
158 | CHECKREG r6, 0x9FE1B90A; | |
159 | CHECKREG r7, 0xB203DB0C; | |
160 | ||
161 | imm32 r0, 0x15678911; | |
162 | imm32 r1, 0x2789ab1d; | |
163 | imm32 r2, 0x34445515; | |
164 | imm32 r3, 0x46667717; | |
165 | imm32 r0, 0x5567891b; | |
166 | imm32 r1, 0x6789ab1d; | |
167 | imm32 r2, 0x74445515; | |
168 | imm32 r3, 0x86667777; | |
169 | R0 = R6 +|- R0 , R7 = R6 -|+ R0; | |
170 | R1 = R6 +|- R1 , R6 = R6 -|+ R1; | |
171 | R2 = R6 +|- R2 , R5 = R6 -|+ R2; | |
172 | R3 = R6 +|- R3 , R4 = R6 -|+ R3; | |
173 | R4 = R6 +|- R4 , R3 = R6 -|+ R4; | |
174 | R5 = R6 +|- R5 , R2 = R6 -|+ R5; | |
175 | R6 = R6 +|- R6 , R1 = R6 -|+ R6; | |
176 | R7 = R6 +|- R7 , R0 = R6 -|+ R7; | |
177 | CHECKREG r0, 0x26364225; | |
178 | CHECKREG r1, 0x0000C84E; | |
179 | CHECKREG r2, 0x74441D63; | |
180 | CHECKREG r3, 0x86663FC5; | |
181 | CHECKREG r4, 0xEA4A8889; | |
182 | CHECKREG r5, 0xFC6CAAEB; | |
183 | CHECKREG r6, 0x70B00000; | |
184 | CHECKREG r7, 0xBB2ABDDB; | |
185 | ||
186 | imm32 r0, 0x67898911; | |
187 | imm32 r1, 0xb789ab1d; | |
188 | imm32 r2, 0x3b445515; | |
189 | imm32 r3, 0x46b67717; | |
190 | imm32 r0, 0x5567891b; | |
191 | imm32 r1, 0x678bab1d; | |
192 | imm32 r2, 0x7444b515; | |
193 | imm32 r3, 0x86667b77; | |
194 | R0 = R7 +|- R0 , R7 = R7 -|+ R0; | |
195 | R1 = R7 +|- R1 , R6 = R7 -|+ R1; | |
196 | R2 = R7 +|- R2 , R5 = R7 -|+ R2; | |
197 | R3 = R7 +|- R3 , R4 = R7 -|+ R3; | |
198 | R4 = R7 +|- R4 , R3 = R7 -|+ R4; | |
199 | R5 = R7 +|- R5 , R2 = R7 -|+ R5; | |
200 | R6 = R7 +|- R6 , R1 = R7 -|+ R6; | |
201 | R7 = R7 +|- R7 , R0 = R7 -|+ R7; | |
202 | CHECKREG r0, 0x00008DEC; | |
203 | CHECKREG r1, 0x678B3909; | |
204 | CHECKREG r2, 0x74444301; | |
205 | CHECKREG r3, 0x86660963; | |
206 | CHECKREG r4, 0x45208489; | |
207 | CHECKREG r5, 0x57424AEB; | |
208 | CHECKREG r6, 0x63FB54E3; | |
209 | CHECKREG r7, 0xCB860000; | |
210 | ||
211 | imm32 r0, 0xe5678911; | |
212 | imm32 r1, 0x2e89ab1d; | |
213 | imm32 r2, 0x34ee5515; | |
214 | imm32 r3, 0x4666e717; | |
215 | imm32 r0, 0x5567891b; | |
216 | imm32 r1, 0x6789ae1d; | |
217 | imm32 r2, 0x744455e5; | |
218 | imm32 r3, 0x8666777e; | |
219 | R4 = R2 +|- R5 , R3 = R2 -|+ R5 (S); | |
220 | R0 = R5 +|- R3 , R5 = R5 -|+ R3 (CO); | |
221 | R2 = R6 +|- R2 , R0 = R6 -|+ R2 (SCO); | |
222 | R3 = R4 +|- R0 , R2 = R4 -|+ R0 (S); | |
223 | R7 = R7 +|- R6 , R6 = R7 -|+ R6 (CO); | |
224 | R6 = R1 +|- R7 , R1 = R1 -|+ R7 (SCO); | |
225 | R5 = R0 +|- R4 , R7 = R0 -|+ R4 (S); | |
226 | R1 = R3 +|- R1 , R4 = R3 -|+ R1 (CO); | |
227 | CHECKREG r0, 0x7FFFEFB7; | |
228 | CHECKREG r1, 0xFFFFE33B; | |
229 | CHECKREG r2, 0x0000FAB1; | |
230 | CHECKREG r3, 0x7FFF1B43; | |
231 | CHECKREG r4, 0x534BFFFF; | |
232 | CHECKREG r5, 0x7FFFE4BD; | |
233 | CHECKREG r6, 0x7FFF0300; | |
234 | CHECKREG r7, 0x0000FAB1; | |
235 | ||
236 | imm32 r0, 0xff678911; | |
237 | imm32 r1, 0x2789ab1d; | |
238 | imm32 r2, 0x3f445515; | |
239 | imm32 r3, 0x46f67717; | |
240 | imm32 r0, 0x556f891b; | |
241 | imm32 r1, 0x6789fb1d; | |
242 | imm32 r2, 0x74445f15; | |
243 | imm32 r3, 0x866677f7; | |
244 | R4 = R3 +|- R3 , R5 = R3 -|+ R3 (SCO); | |
245 | R1 = R6 +|- R1 , R6 = R6 -|+ R1 (SCO); | |
246 | R6 = R1 +|- R4 , R4 = R1 -|+ R4 (S); | |
247 | R7 = R4 +|- R2 , R0 = R4 -|+ R2 (S); | |
248 | R2 = R2 +|- R6 , R1 = R2 -|+ R6 (CO); | |
249 | R3 = R5 +|- R5 , R7 = R5 -|+ R5 (CO); | |
250 | R5 = R7 +|- R7 , R3 = R7 -|+ R7 (SCO); | |
251 | R0 = R0 +|- R0 , R2 = R0 -|+ R0 (SCO); | |
252 | CHECKREG r0, 0x17760000; | |
253 | CHECKREG r1, 0x66F87445; | |
254 | CHECKREG r2, 0x7FFF0000; | |
255 | CHECKREG r3, 0x00000000; | |
256 | CHECKREG r4, 0x7FFF07E3; | |
257 | CHECKREG r5, 0x00000000; | |
258 | CHECKREG r6, 0xFFFF07E3; | |
259 | CHECKREG r7, 0x00000000; | |
260 | ||
261 | ||
262 | ||
263 | pass |