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1d7b4a70 MF |
1 | //Original:/proj/frio/dv/testcases/seq/se_misaligned_fetch/se_misaligned_fetch.dsp |
2 | // Description: attempt to fetch code from misaligned address | |
3 | # mach: bfin | |
4 | # sim: --environment operating | |
5 | ||
6 | #include "test.h" | |
7 | .include "testutils.inc" | |
8 | start | |
9 | ||
10 | // | |
11 | // Constants and Defines | |
12 | // | |
13 | ||
14 | include(gen_int.inc) | |
15 | include(selfcheck.inc) | |
16 | include(std.inc) | |
17 | include(symtable.inc) | |
18 | ||
19 | #ifndef STACKSIZE | |
20 | #define STACKSIZE 0x10 | |
21 | #endif | |
22 | #ifndef EVT | |
23 | #define EVT 0xFFE02000 | |
24 | #endif | |
25 | #ifndef EVT15 | |
26 | #define EVT15 0xFFE0203C | |
27 | #endif | |
28 | #ifndef EVT_OVERRIDE | |
29 | #define EVT_OVERRIDE 0xFFE02100 | |
30 | #endif | |
31 | #ifndef ITABLE | |
32 | #define ITABLE 0xF0000000 | |
33 | #endif | |
34 | ||
35 | GEN_INT_INIT(ITABLE) // set location for interrupt table | |
36 | ||
37 | // | |
38 | // Reset/Bootstrap Code | |
39 | // (Here we should set the processor operating modes, initialize registers, | |
40 | // etc.) | |
41 | // | |
42 | ||
43 | BOOT: | |
44 | INIT_R_REGS(0); // initialize general purpose regs | |
45 | ||
46 | INIT_P_REGS(0); // initialize the pointers | |
47 | ||
48 | INIT_I_REGS(0); // initialize the dsp address regs | |
49 | INIT_M_REGS(0); | |
50 | INIT_L_REGS(0); | |
51 | INIT_B_REGS(0); | |
52 | ||
53 | LD32_LABEL(sp, KSTACK); // setup the stack pointer | |
54 | FP = SP; // and frame pointer | |
55 | ||
56 | LD32(p0, EVT); // Setup Event Vectors and Handlers | |
57 | ||
58 | CLI R0; // hold off nonmaskables while writing EVTs | |
59 | ||
60 | LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) | |
61 | ||
62 | [ P0 ++ ] = R0; | |
63 | ||
64 | LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) | |
65 | [ P0 ++ ] = R0; | |
66 | ||
67 | LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) | |
68 | [ P0 ++ ] = R0; | |
69 | ||
70 | LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) | |
71 | [ P0 ++ ] = R0; | |
72 | ||
73 | [ P0 ++ ] = R0; // IVT4 not used | |
74 | ||
75 | LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) | |
76 | [ P0 ++ ] = R0; | |
77 | ||
78 | LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) | |
79 | [ P0 ++ ] = R0; | |
80 | ||
81 | LD32_LABEL(r0, I7HANDLE); // IVG7 Handler | |
82 | [ P0 ++ ] = R0; | |
83 | ||
84 | LD32_LABEL(r0, I8HANDLE); // IVG8 Handler | |
85 | [ P0 ++ ] = R0; | |
86 | ||
87 | LD32_LABEL(r0, I9HANDLE); // IVG9 Handler | |
88 | [ P0 ++ ] = R0; | |
89 | ||
90 | LD32_LABEL(r0, I10HANDLE);// IVG10 Handler | |
91 | [ P0 ++ ] = R0; | |
92 | ||
93 | LD32_LABEL(r0, I11HANDLE);// IVG11 Handler | |
94 | [ P0 ++ ] = R0; | |
95 | ||
96 | LD32_LABEL(r0, I12HANDLE);// IVG12 Handler | |
97 | [ P0 ++ ] = R0; | |
98 | ||
99 | LD32_LABEL(r0, I13HANDLE);// IVG13 Handler | |
100 | [ P0 ++ ] = R0; | |
101 | ||
102 | LD32_LABEL(r0, I14HANDLE);// IVG14 Handler | |
103 | [ P0 ++ ] = R0; | |
104 | ||
105 | LD32_LABEL(r0, I15HANDLE);// IVG15 Handler | |
106 | [ P0 ++ ] = R0; | |
107 | ||
108 | LD32(p0, EVT_OVERRIDE); | |
109 | R0 = 0; | |
110 | [ P0 ++ ] = R0; | |
111 | R0 = -1; // Change this to mask interrupts (*) | |
112 | [ P0 ] = R0; // IMASK | |
113 | CSYNC; // wait for MMR writes | |
114 | STI R0; // reenable events | |
115 | ||
116 | DUMMY: | |
117 | ||
118 | R0 = 0 (Z); | |
119 | ||
120 | LT0 = r0; // set loop counters to something deterministic | |
121 | LB0 = r0; | |
122 | LC0 = r0; | |
123 | LT1 = r0; | |
124 | LB1 = r0; | |
125 | LC1 = r0; | |
126 | ||
127 | ASTAT = r0; // reset other internal regs | |
128 | ||
129 | // The following code sets up the test for running in USER mode | |
130 | ||
131 | LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a | |
132 | // ReturnFromInterrupt (RTI) | |
133 | RETI = r0; // We need to load the return address | |
134 | ||
135 | // Comment the following line for a USER Mode test | |
136 | ||
137 | // JUMP STARTSUP; // jump to code start for SUPERVISOR mode | |
138 | ||
139 | RTI; | |
140 | ||
141 | STARTSUP: | |
142 | LD32_LABEL(p1, BEGIN); | |
143 | ||
144 | LD32(p0, EVT15); | |
145 | [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start | |
146 | ||
147 | RAISE 15; // after we RTI, INT 15 should be taken | |
148 | ||
149 | RTI; | |
150 | ||
151 | // | |
152 | // The Main Program | |
153 | // | |
154 | ||
155 | STARTUSER: | |
156 | LD32_LABEL(sp, USTACK); // setup the stack pointer | |
157 | FP = SP; // set frame pointer | |
158 | JUMP BEGIN; | |
159 | ||
160 | //********************************************************************* | |
161 | ||
162 | BEGIN: | |
163 | ||
164 | // COMMENT the following line for USER MODE tests | |
165 | // [--sp] = RETI; // enable interrupts in supervisor mode | |
166 | ||
167 | // **** YOUR CODE GOES HERE **** | |
168 | CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); | |
169 | ||
170 | LD32_LABEL(p1, TARGET); | |
171 | ||
172 | P1 += 1; // cause access to be misaligned | |
173 | ||
174 | JUMP ( P1 ); // should cause misaligned | |
175 | ||
176 | R1 += 1; | |
177 | R1 += 1; | |
178 | R1 += 1; | |
179 | R1 += 1; | |
180 | R1 += 1; | |
181 | R1 += 1; | |
182 | R1 += 1; | |
183 | R1 += 1; | |
184 | ||
185 | TARGET: | |
186 | NOP; | |
187 | NOP; | |
188 | NOP; | |
189 | ||
190 | // PUT YOUR TEST HERE! | |
191 | ||
192 | ||
193 | END: | |
194 | CHECKREG(r5, 0xFFFFFFFF); // handler sets this if reached | |
195 | ||
196 | dbg_pass; // End the test | |
197 | ||
198 | //********************************************************************* | |
199 | ||
200 | // | |
201 | // Handlers for Events | |
202 | // | |
203 | ||
204 | EHANDLE: // Emulation Handler 0 | |
205 | RTE; | |
206 | ||
207 | RHANDLE: // Reset Handler 1 | |
208 | RTI; | |
209 | ||
210 | NHANDLE: // NMI Handler 2 | |
211 | RTN; | |
212 | ||
213 | XHANDLE: // Exception Handler 3 | |
214 | [ -- SP ] = ASTAT; // save what we damage | |
215 | [ -- SP ] = ( R7:6 ); | |
216 | R7 = SEQSTAT; | |
217 | R7 <<= 26; | |
218 | R7 >>= 26; // only want EXCAUSE | |
219 | R6 = 0x2A; // EXCAUSE 0x2A means I-Fetch Misaligned Access | |
220 | CC = r7 == r6; | |
221 | IF CC JUMP IFETCHMISALIGNED; // If EXCAUSE != 0x2A then leave | |
222 | ||
223 | dbg_pass; // if the EXCAUSE is wrong the test will infinite loop | |
224 | ||
225 | IFETCHMISALIGNED: | |
226 | R7 = P1; // Fix up return address | |
227 | BITCLR(r7, 0); // Strip off errant LSB | |
228 | RETX = r7; // and put back in RETX | |
229 | ||
230 | R5 = -1; // set flag to indicate success | |
231 | ||
232 | OUT: | |
233 | ( R7:6 ) = [ SP ++ ]; | |
234 | ASTAT = [sp++]; | |
235 | RTX; | |
236 | ||
237 | HWHANDLE: // HW Error Handler 5 | |
238 | RTI; | |
239 | ||
240 | THANDLE: // Timer Handler 6 | |
241 | RTI; | |
242 | ||
243 | I7HANDLE: // IVG 7 Handler | |
244 | RTI; | |
245 | ||
246 | I8HANDLE: // IVG 8 Handler | |
247 | RTI; | |
248 | ||
249 | I9HANDLE: // IVG 9 Handler | |
250 | RTI; | |
251 | ||
252 | I10HANDLE: // IVG 10 Handler | |
253 | RTI; | |
254 | ||
255 | I11HANDLE: // IVG 11 Handler | |
256 | RTI; | |
257 | ||
258 | I12HANDLE: // IVG 12 Handler | |
259 | RTI; | |
260 | ||
261 | I13HANDLE: // IVG 13 Handler | |
262 | RTI; | |
263 | ||
264 | I14HANDLE: // IVG 14 Handler | |
265 | RTI; | |
266 | ||
267 | I15HANDLE: // IVG 15 Handler | |
268 | RTI; | |
269 | ||
270 | NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug | |
271 | ||
272 | // | |
273 | // Data Segment | |
274 | // | |
275 | ||
276 | .data | |
277 | DATA: | |
278 | .space (0x10); | |
279 | ||
280 | // Stack Segments (Both Kernel and User) | |
281 | ||
282 | .space (STACKSIZE); | |
283 | KSTACK: | |
284 | ||
285 | .space (STACKSIZE); | |
286 | USTACK: |