[deliverable/binutils-gdb.git] / sim / testsuite / d10v-elf / t-dbt.s

.include "t-macros.i"

	start

	PSW_BITS = PSW_DM
	
;;; Blat our DMAP registers so that they point at on-chip imem

	ldi r2, MAP_INSN | 0xf
	st r2, @(DMAP_REG,r0)
	ldi r2, MAP_INSN
	st r2, @(IMAP1_REG,r0)

;;; Patch the interrupt vector's dbt entry with a jmp to success

	ldi r4, #trap
	ldi r5, (VEC_DBT & DMAP_MASK) + DMAP_BASE
	ld2w r2, @(0,r4)
	st2w r2, @(0,r5)
	ld2w r2, @(4,r4)
	st2w r2, @(4,r5)

test_dbt:
	dbt -> nop
	exit47

success:
	checkpsw2 1 PSW_BITS
	exit0

	.data
trap:	ldi r1, success@word
	jmp r1
Commit	Line	Data
c906108c SS	1	.include "t-macros.i"
	2
	3	start
	4
	5	PSW_BITS = PSW_DM
	6
	7	;;; Blat our DMAP registers so that they point at on-chip imem
	8
	9	ldi r2, MAP_INSN \| 0xf
	10	st r2, @(DMAP_REG,r0)
	11	ldi r2, MAP_INSN
	12	st r2, @(IMAP1_REG,r0)
	13
	14	;;; Patch the interrupt vector's dbt entry with a jmp to success
	15
	16	ldi r4, #trap
	17	ldi r5, (VEC_DBT & DMAP_MASK) + DMAP_BASE
	18	ld2w r2, @(0,r4)
	19	st2w r2, @(0,r5)
	20	ld2w r2, @(4,r4)
	21	st2w r2, @(4,r5)
	22
	23	test_dbt:
	24	dbt -> nop
	25	exit47
	26
	27	success:
	28	checkpsw2 1 PSW_BITS
	29	exit0
	30
	31	.data
	32	trap: ldi r1, success@word
	33	jmp r1