[deliverable/binutils-gdb.git] / sim / testsuite / sim / arm / add.cgs

# arm testcase for add
# mach: all

# ??? Unfinished, more tests needed.

	.include "testutils.inc"

	start

# add$cond${set-cc?} $rd,$rn,$imm12

	.global add_imm
add_imm:
	mvi_h_gr r4,1
	mvi_h_cnvz 0,0,0,0
	add r5,r4,#1
	test_h_cnvz 0,0,0,0
	test_h_gr r5,2

# add$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm}

	.global add_reg_imm_shift
add_reg_imm_shift:
	mvi_h_gr r4,1
	mvi_h_gr r5,1
	mvi_h_cnvz 0,0,0,0
	add r6,r4,r5,lsl #2
	test_h_cnvz 0,0,0,0
	test_h_gr r6,5

# add$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg}

	.global add_reg_reg_shift
add_reg_reg_shift:
	mvi_h_gr r4,1
	mvi_h_gr r5,1
	mvi_h_gr r6,2
	mvi_h_cnvz 0,0,0,0
	add r7,r4,r5,lsl r6
	test_h_cnvz 0,0,0,0
	test_h_gr r7,5

	pass
Commit	Line	Data
49634642 NC	1	# arm testcase for add
	2	# mach: all
	3
	4	# ??? Unfinished, more tests needed.
	5
	6	.include "testutils.inc"
	7
	8	start
	9
	10	# add$cond${set-cc?} $rd,$rn,$imm12
	11
	12	.global add_imm
	13	add_imm:
	14	mvi_h_gr r4,1
	15	mvi_h_cnvz 0,0,0,0
	16	add r5,r4,#1
	17	test_h_cnvz 0,0,0,0
	18	test_h_gr r5,2
	19
	20	# add$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm}
	21
	22	.global add_reg_imm_shift
	23	add_reg_imm_shift:
	24	mvi_h_gr r4,1
	25	mvi_h_gr r5,1
	26	mvi_h_cnvz 0,0,0,0
	27	add r6,r4,r5,lsl #2
	28	test_h_cnvz 0,0,0,0
	29	test_h_gr r6,5
	30
	31	# add$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg}
	32
	33	.global add_reg_reg_shift
	34	add_reg_reg_shift:
	35	mvi_h_gr r4,1
	36	mvi_h_gr r5,1
	37	mvi_h_gr r6,2
	38	mvi_h_cnvz 0,0,0,0
	39	add r7,r4,r5,lsl r6
	40	test_h_cnvz 0,0,0,0
	41	test_h_gr r7,5
	42
	43	pass