[deliverable/binutils-gdb.git] / sim / testsuite / sim / cris / asm / raw12.ms

; Checking read-after-write: swrite-then-nop-nop-read unaffected.
#mach: crisv32
#output: Basic clock cycles, total @: 6\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 0\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=basic
 .include "testutils.inc"
 startnostack
 .lcomm x,4
 .lcomm y,4
 move.d x,$r0
 move.d y,$r1
 clear.d [$r0]
 nop
 nop
 move [$r1],$srp
 break 15
Commit	Line	Data
5e1f6430 HPN	1	; Checking read-after-write: swrite-then-nop-nop-read unaffected.
	2	#mach: crisv32
	3	#output: Basic clock cycles, total @: 6\n
	4	#output: Memory source stall cycles: 0\n
	5	#output: Memory read-after-write stall cycles: 0\n
	6	#output: Movem source stall cycles: 0\n
	7	#output: Movem destination stall cycles: 0\n
	8	#output: Movem address stall cycles: 0\n
	9	#output: Multiplication source stall cycles: 0\n
	10	#output: Jump source stall cycles: 0\n
	11	#output: Branch misprediction stall cycles: 0\n
	12	#output: Jump target stall cycles: 0\n
	13	#sim: --cris-cycles=basic
	14	.include "testutils.inc"
	15	startnostack
	16	.lcomm x,4
	17	.lcomm y,4
	18	move.d x,$r0
	19	move.d y,$r1
	20	clear.d [$r0]
	21	nop
	22	nop
	23	move [$r1],$srp
	24	break 15