[deliverable/binutils-gdb.git] / sim / testsuite / sim / cris / asm / raw7.ms

; Checking read-after-write: movemwrite-then-read 2 cycles.
#mach: crisv32
#ld: --section-start=.text=0
#output: Basic clock cycles, total @: 6\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 2\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 1\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=basic
 .include "testutils.inc"
 startnostack
 .lcomm x,4*11
 .lcomm y,4
 move.d x,$r0
 move.d y,$r1
 nop
 nop
 movem $r10,[$r0]
 move.d [$r1],$r2
 break 15
Commit	Line	Data
5e1f6430 HPN	1	; Checking read-after-write: movemwrite-then-read 2 cycles.
	2	#mach: crisv32
	3	#ld: --section-start=.text=0
	4	#output: Basic clock cycles, total @: 6\n
	5	#output: Memory source stall cycles: 0\n
	6	#output: Memory read-after-write stall cycles: 2\n
	7	#output: Movem source stall cycles: 0\n
	8	#output: Movem destination stall cycles: 0\n
	9	#output: Movem address stall cycles: 1\n
	10	#output: Multiplication source stall cycles: 0\n
	11	#output: Jump source stall cycles: 0\n
	12	#output: Branch misprediction stall cycles: 0\n
	13	#output: Jump target stall cycles: 0\n
	14	#sim: --cris-cycles=basic
	15	.include "testutils.inc"
	16	startnostack
	17	.lcomm x,4*11
	18	.lcomm y,4
	19	move.d x,$r0
	20	move.d y,$r1
	21	nop
	22	nop
	23	movem $r10,[$r0]
	24	move.d [$r1],$r2
	25	break 15