* sim/cris/asm/testutils.inc (test_h_mem): Use register prefix.
[deliverable/binutils-gdb.git] / sim / testsuite / sim / cris / asm / tmvmrv10.ms
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1#mach: crisv10
2#output: Basic clock cycles, total @: 45\n
3#output: Memory source stall cycles: 0\n
4#output: Memory read-after-write stall cycles: 0\n
5#output: Movem source stall cycles: 0\n
6#output: Movem destination stall cycles: 0\n
7#output: Movem address stall cycles: 0\n
8#output: Multiplication source stall cycles: 0\n
9#output: Jump source stall cycles: 0\n
10#output: Branch misprediction stall cycles: 0\n
11#output: Jump target stall cycles: 0\n
12#sim: --cris-cycles=basic
13
14; Check that movem to register basically looks ok cycle-wise.
15; Nothing deep.
16
17 .include "testutils.inc"
18 startnostack
19 move.d 0f,r5
20 moveq 0,r8
21 moveq 0,r9
22
23; Adapted from crisv32 movem-to-memory penalty examples many
24; revisions ago.
25
26 movem [r5],r4
27 test.d [r3] ; 3 cycle penalty on v32 (2 memory source, 1 movem dest).
28 movem [r5],r4
29 subq 1,r8
30 test.d [r3] ; 2 cycle penalty on v32.
31 movem [r5],r4
32 subq 1,r1 ; 3 cycle penalty on v32.
33 movem [r5],r4
34 add.d r8,r9
35 subq 1,r1 ; 2 cycle penalty on v32.
36 movem [r5],r4
37 add.d r8,r9
38 subq 1, r9
39 subq 1, r1 ; 1 cycle penalty on v32.
40 break 15
41
42 .data
43 .p2align 5
440:
45 .dword 0b
46 .dword 0b
47 .dword 0b
48 .dword 0b
49 .dword 0b
50
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