projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 26d01138 HPN |
1 | #mach: crisv10 crisv32 |
| 2 | #sim(crisv10): --hw-device "/rv/trace? true" | |
| 3 | #sim(crisv32): --hw-device "/rv/trace? true" | |
| 4 | #output: /rv: WD\n | |
| 5 | #output: /rv: REG R 0xd0000032\n | |
| 6 | #output: /rv: := 0xabcdef01\n | |
| 7 | #output: /rv: IRQ 0x4\n | |
| 8 | #output: /rv: REG R 0xd0000036\n | |
| 9 | #output: /rv: := 0x76543210\n | |
| 10 | #output: /rv: REG R 0xd0000036\n | |
| 11 | #output: /rv: := 0x76543211\n | |
| 12 | #output: /rv: REG R 0xd0000030\n | |
| 13 | #output: /rv: IRQ 0x0\n | |
| 14 | #output: /rv: := 0xeeff4455\n | |
| 15 | #output: pass\n | |
| 16 | ||
| 17 | # Trivial test of interrupts. | |
| 18 | # Locations of IRQ notifiers above depend on when the simulator is | |
| 19 | # polled; adjustments may be needed (after checking that no poll is | |
| 20 | # gone due to a bug!) | |
| 21 | ||
| 22 | #r W, | |
| 23 | #r r,a8832,abcdef01 | |
| 24 | #r I,4 | |
| 25 | #r r,a8836,76543210 | |
| 26 | #r r,a8836,76543211 | |
| 27 | #r I,0 | |
| 28 | #r r,a8830,eeff4455 | |
| 29 | ||
| 30 | .lcomm dummy,4 | |
| 31 | ||
| 32 | .include "testutils.inc" | |
| 33 | start | |
| 34 | .if ..asm.arch.cris.v32 | |
| 35 | move irqvec1,$ebp | |
| 36 | .else | |
| 37 | move irqvec1,$ibr | |
| 38 | .endif | |
| 39 | test_h_mem 0xabcdef01 0xd0000032 | |
| 40 | nop | |
| 41 | nop | |
| 42 | test_h_mem 0x76543210 0xd0000036 | |
| 43 | ei | |
| 44 | test_h_mem 0,dummy | |
| 45 | wouldreturnhere: | |
| 46 | nop | |
| 47 | killme: | |
| 48 | fail | |
| 49 | ||
| 50 | returnhere: | |
| 51 | test_h_mem 0x76543211 0xd0000036 | |
| 52 | test_h_mem 0xeeff4455 0xd0000030 | |
| 53 | pass | |
| 54 | ||
| 55 | irq0x33: | |
| 56 | .if ..asm.arch.cris.v32 | |
| 57 | test_h_dr wouldreturnhere,$erp | |
| 58 | move returnhere,$erp | |
| 59 | rete | |
| 60 | rfe | |
| 61 | .else | |
| 62 | move $dccr,$r0 | |
| 63 | test_h_dr wouldreturnhere,$irp | |
| 64 | move returnhere,$irp | |
| 65 | reti | |
| 66 | move $r0,$dccr | |
| 67 | .endif | |
| 68 | ||
| 69 | singlevec irqvec1,0x33,irq0x33 |