2004-02-29 Andrew Cagney <cagney@redhat.com>
[deliverable/binutils-gdb.git] / sim / testsuite / sim / frv / break.cgs
CommitLineData
4a306116
DB
1# FRV testcase for break
2# mach: all
3
4 .include "testutils.inc"
5
6 start
7
8 .global tra
9tra:
10 ; Can't test break anymore in the user environment because it is the
11 ; debugger's breakpoint insn. Just pass this test for now.
12 pass
13
14
15
16
17
18 set_gr_spr tbr,gr7
19 and_gr_immed -4081,gr7 ; clear tbr.tt
20 inc_gr_immed 0xff0,gr7 ; break handler
21 set_bctrlr_0_0 gr7
22 set_spr_immed 128,lcr
23
24 test_spr_bits 0x4,2,0x1,psr ; psr.s is set
25 test_spr_bits 0x1,0,0x0,psr ; psr.et is clear
26 set_spr_addr ok1,lr
27 break
28ret:
29 or_spr_immed 0x00000001,psr ; turn on psr.et
30 and_spr_immed 0xfffffffb,psr ; turn off psr.s
31 test_spr_bits 0x4,2,0x0,psr ; psr.s is clear
32 test_spr_bits 0x1,0,0x1,psr ; psr.et is set
33 set_spr_addr ok0,lr
34 break
35ret1:
36 test_spr_bits 0x4,2,0x0,psr ; psr.s is clear
37 test_spr_bits 0x1,0,0x1,psr ; psr.et is set
38 pass
39
40 ; check interrupt for second break
41ok0: test_spr_addr ret1,bpcsr
42 test_spr_bits 0x1000,12,0x0,bpsr ; bpsr.bs is clear
43 test_spr_bits 0x0001,0,0x1,bpsr ; bpsr.et is set
44 test_spr_bits 0x4,2,0x1,psr ; psr.s is set
45 test_spr_bits 0x1,0,0x0,psr ; psr.et is clear
46 rett 0 ; nop
47 rett 1
48
49 ; check interrupt for first break
50ok1: test_spr_addr ret,bpcsr
51 test_spr_bits 0x1000,12,0x1,bpsr ; bpsr.bs is set
52 test_spr_bits 0x0001,0,0x0,bpsr ; bpsr.et is clear
53 test_spr_bits 0x4,2,0x1,psr ; psr.s is set
54 test_spr_bits 0x1,0,0x0,psr ; psr.et is clear
55 rett 0 ; nop
56 rett 1
57
58
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