projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 4a306116 DB |
1 | # frv testcase for cfckgt $FCCi,$CCj_float,$CCi,$cond |
| 2 | # mach: all | |
| 3 | ||
| 4 | .include "testutils.inc" | |
| 5 | ||
| 6 | start | |
| 7 | ||
| 8 | .global cfckgt | |
| 9 | cfckgt: | |
| 10 | set_spr_immed 0x1b5b,cccr | |
| 11 | set_fcc 0x0 0 | |
| 12 | cfckgt fcc0,cc3,cc0,1 | |
| 13 | test_spr_immed 0x1b9b,cccr | |
| 14 | ||
| 15 | set_spr_immed 0x1b5b,cccr | |
| 16 | set_fcc 0x1 0 | |
| 17 | cfckgt fcc0,cc3,cc0,1 | |
| 18 | test_spr_immed 0x1b9b,cccr | |
| 19 | ||
| 20 | set_spr_immed 0x1b5b,cccr | |
| 21 | set_fcc 0x2 0 | |
| 22 | cfckgt fcc0,cc3,cc0,1 | |
| 23 | test_spr_immed 0x1bdb,cccr | |
| 24 | ||
| 25 | set_spr_immed 0x1b5b,cccr | |
| 26 | set_fcc 0x3 0 | |
| 27 | cfckgt fcc0,cc3,cc0,1 | |
| 28 | test_spr_immed 0x1bdb,cccr | |
| 29 | ||
| 30 | set_spr_immed 0x1b5b,cccr | |
| 31 | set_fcc 0x4 0 | |
| 32 | cfckgt fcc0,cc3,cc0,1 | |
| 33 | test_spr_immed 0x1b9b,cccr | |
| 34 | ||
| 35 | set_spr_immed 0x1b5b,cccr | |
| 36 | set_fcc 0x5 0 | |
| 37 | cfckgt fcc0,cc3,cc0,1 | |
| 38 | test_spr_immed 0x1b9b,cccr | |
| 39 | ||
| 40 | set_spr_immed 0x1b5b,cccr | |
| 41 | set_fcc 0x6 0 | |
| 42 | cfckgt fcc0,cc3,cc0,1 | |
| 43 | test_spr_immed 0x1bdb,cccr | |
| 44 | ||
| 45 | set_spr_immed 0x1b5b,cccr | |
| 46 | set_fcc 0x7 0 | |
| 47 | cfckgt fcc0,cc3,cc0,1 | |
| 48 | test_spr_immed 0x1bdb,cccr | |
| 49 | ||
| 50 | set_spr_immed 0x1b5b,cccr | |
| 51 | set_fcc 0x8 0 | |
| 52 | cfckgt fcc0,cc3,cc4,1 | |
| 53 | test_spr_immed 0x1b9b,cccr | |
| 54 | ||
| 55 | set_spr_immed 0x1b5b,cccr | |
| 56 | set_fcc 0x9 0 | |
| 57 | cfckgt fcc0,cc3,cc4,1 | |
| 58 | test_spr_immed 0x1b9b,cccr | |
| 59 | ||
| 60 | set_spr_immed 0x1b5b,cccr | |
| 61 | set_fcc 0xa 0 | |
| 62 | cfckgt fcc0,cc3,cc4,1 | |
| 63 | test_spr_immed 0x1bdb,cccr | |
| 64 | ||
| 65 | set_spr_immed 0x1b5b,cccr | |
| 66 | set_fcc 0xb 0 | |
| 67 | cfckgt fcc0,cc3,cc4,1 | |
| 68 | test_spr_immed 0x1bdb,cccr | |
| 69 | ||
| 70 | set_spr_immed 0x1b5b,cccr | |
| 71 | set_fcc 0xc 0 | |
| 72 | cfckgt fcc0,cc3,cc4,1 | |
| 73 | test_spr_immed 0x1b9b,cccr | |
| 74 | ||
| 75 | set_spr_immed 0x1b5b,cccr | |
| 76 | set_fcc 0xd 0 | |
| 77 | cfckgt fcc0,cc3,cc4,1 | |
| 78 | test_spr_immed 0x1b9b,cccr | |
| 79 | ||
| 80 | set_spr_immed 0x1b5b,cccr | |
| 81 | set_fcc 0xe 0 | |
| 82 | cfckgt fcc0,cc3,cc4,1 | |
| 83 | test_spr_immed 0x1bdb,cccr | |
| 84 | ||
| 85 | set_spr_immed 0x1b5b,cccr | |
| 86 | set_fcc 0xf 0 | |
| 87 | cfckgt fcc0,cc3,cc4,1 | |
| 88 | test_spr_immed 0x1bdb,cccr | |
| 89 | ||
| 90 | set_spr_immed 0x1b5b,cccr | |
| 91 | set_fcc 0x0 0 | |
| 92 | cfckgt fcc0,cc3,cc0,0 | |
| 93 | test_spr_immed 0x1b1b,cccr | |
| 94 | ||
| 95 | set_spr_immed 0x1b5b,cccr | |
| 96 | set_fcc 0x1 0 | |
| 97 | cfckgt fcc0,cc3,cc0,0 | |
| 98 | test_spr_immed 0x1b1b,cccr | |
| 99 | ||
| 100 | set_spr_immed 0x1b5b,cccr | |
| 101 | set_fcc 0x2 0 | |
| 102 | cfckgt fcc0,cc3,cc0,0 | |
| 103 | test_spr_immed 0x1b1b,cccr | |
| 104 | ||
| 105 | set_spr_immed 0x1b5b,cccr | |
| 106 | set_fcc 0x3 0 | |
| 107 | cfckgt fcc0,cc3,cc0,0 | |
| 108 | test_spr_immed 0x1b1b,cccr | |
| 109 | ||
| 110 | set_spr_immed 0x1b5b,cccr | |
| 111 | set_fcc 0x4 0 | |
| 112 | cfckgt fcc0,cc3,cc0,0 | |
| 113 | test_spr_immed 0x1b1b,cccr | |
| 114 | ||
| 115 | set_spr_immed 0x1b5b,cccr | |
| 116 | set_fcc 0x5 0 | |
| 117 | cfckgt fcc0,cc3,cc0,0 | |
| 118 | test_spr_immed 0x1b1b,cccr | |
| 119 | ||
| 120 | set_spr_immed 0x1b5b,cccr | |
| 121 | set_fcc 0x6 0 | |
| 122 | cfckgt fcc0,cc3,cc0,0 | |
| 123 | test_spr_immed 0x1b1b,cccr | |
| 124 | ||
| 125 | set_spr_immed 0x1b5b,cccr | |
| 126 | set_fcc 0x7 0 | |
| 127 | cfckgt fcc0,cc3,cc0,0 | |
| 128 | test_spr_immed 0x1b1b,cccr | |
| 129 | ||
| 130 | set_spr_immed 0x1b5b,cccr | |
| 131 | set_fcc 0x8 0 | |
| 132 | cfckgt fcc0,cc3,cc4,0 | |
| 133 | test_spr_immed 0x1b1b,cccr | |
| 134 | ||
| 135 | set_spr_immed 0x1b5b,cccr | |
| 136 | set_fcc 0x9 0 | |
| 137 | cfckgt fcc0,cc3,cc4,0 | |
| 138 | test_spr_immed 0x1b1b,cccr | |
| 139 | ||
| 140 | set_spr_immed 0x1b5b,cccr | |
| 141 | set_fcc 0xa 0 | |
| 142 | cfckgt fcc0,cc3,cc4,0 | |
| 143 | test_spr_immed 0x1b1b,cccr | |
| 144 | ||
| 145 | set_spr_immed 0x1b5b,cccr | |
| 146 | set_fcc 0xb 0 | |
| 147 | cfckgt fcc0,cc3,cc4,0 | |
| 148 | test_spr_immed 0x1b1b,cccr | |
| 149 | ||
| 150 | set_spr_immed 0x1b5b,cccr | |
| 151 | set_fcc 0xc 0 | |
| 152 | cfckgt fcc0,cc3,cc4,0 | |
| 153 | test_spr_immed 0x1b1b,cccr | |
| 154 | ||
| 155 | set_spr_immed 0x1b5b,cccr | |
| 156 | set_fcc 0xd 0 | |
| 157 | cfckgt fcc0,cc3,cc4,0 | |
| 158 | test_spr_immed 0x1b1b,cccr | |
| 159 | ||
| 160 | set_spr_immed 0x1b5b,cccr | |
| 161 | set_fcc 0xe 0 | |
| 162 | cfckgt fcc0,cc3,cc4,0 | |
| 163 | test_spr_immed 0x1b1b,cccr | |
| 164 | ||
| 165 | set_spr_immed 0x1b5b,cccr | |
| 166 | set_fcc 0xf 0 | |
| 167 | cfckgt fcc0,cc3,cc4,0 | |
| 168 | test_spr_immed 0x1b1b,cccr | |
| 169 | ||
| 170 | set_spr_immed 0x1b5b,cccr | |
| 171 | set_fcc 0x0 0 | |
| 172 | cfckgt fcc0,cc3,cc1,0 | |
| 173 | test_spr_immed 0x1b9b,cccr | |
| 174 | ||
| 175 | set_spr_immed 0x1b5b,cccr | |
| 176 | set_fcc 0x1 0 | |
| 177 | cfckgt fcc0,cc3,cc1,0 | |
| 178 | test_spr_immed 0x1b9b,cccr | |
| 179 | ||
| 180 | set_spr_immed 0x1b5b,cccr | |
| 181 | set_fcc 0x2 0 | |
| 182 | cfckgt fcc0,cc3,cc1,0 | |
| 183 | test_spr_immed 0x1bdb,cccr | |
| 184 | ||
| 185 | set_spr_immed 0x1b5b,cccr | |
| 186 | set_fcc 0x3 0 | |
| 187 | cfckgt fcc0,cc3,cc1,0 | |
| 188 | test_spr_immed 0x1bdb,cccr | |
| 189 | ||
| 190 | set_spr_immed 0x1b5b,cccr | |
| 191 | set_fcc 0x4 0 | |
| 192 | cfckgt fcc0,cc3,cc1,0 | |
| 193 | test_spr_immed 0x1b9b,cccr | |
| 194 | ||
| 195 | set_spr_immed 0x1b5b,cccr | |
| 196 | set_fcc 0x5 0 | |
| 197 | cfckgt fcc0,cc3,cc1,0 | |
| 198 | test_spr_immed 0x1b9b,cccr | |
| 199 | ||
| 200 | set_spr_immed 0x1b5b,cccr | |
| 201 | set_fcc 0x6 0 | |
| 202 | cfckgt fcc0,cc3,cc1,0 | |
| 203 | test_spr_immed 0x1bdb,cccr | |
| 204 | ||
| 205 | set_spr_immed 0x1b5b,cccr | |
| 206 | set_fcc 0x7 0 | |
| 207 | cfckgt fcc0,cc3,cc1,0 | |
| 208 | test_spr_immed 0x1bdb,cccr | |
| 209 | ||
| 210 | set_spr_immed 0x1b5b,cccr | |
| 211 | set_fcc 0x8 0 | |
| 212 | cfckgt fcc0,cc3,cc5,0 | |
| 213 | test_spr_immed 0x1b9b,cccr | |
| 214 | ||
| 215 | set_spr_immed 0x1b5b,cccr | |
| 216 | set_fcc 0x9 0 | |
| 217 | cfckgt fcc0,cc3,cc5,0 | |
| 218 | test_spr_immed 0x1b9b,cccr | |
| 219 | ||
| 220 | set_spr_immed 0x1b5b,cccr | |
| 221 | set_fcc 0xa 0 | |
| 222 | cfckgt fcc0,cc3,cc5,0 | |
| 223 | test_spr_immed 0x1bdb,cccr | |
| 224 | ||
| 225 | set_spr_immed 0x1b5b,cccr | |
| 226 | set_fcc 0xb 0 | |
| 227 | cfckgt fcc0,cc3,cc5,0 | |
| 228 | test_spr_immed 0x1bdb,cccr | |
| 229 | ||
| 230 | set_spr_immed 0x1b5b,cccr | |
| 231 | set_fcc 0xc 0 | |
| 232 | cfckgt fcc0,cc3,cc5,0 | |
| 233 | test_spr_immed 0x1b9b,cccr | |
| 234 | ||
| 235 | set_spr_immed 0x1b5b,cccr | |
| 236 | set_fcc 0xd 0 | |
| 237 | cfckgt fcc0,cc3,cc5,0 | |
| 238 | test_spr_immed 0x1b9b,cccr | |
| 239 | ||
| 240 | set_spr_immed 0x1b5b,cccr | |
| 241 | set_fcc 0xe 0 | |
| 242 | cfckgt fcc0,cc3,cc5,0 | |
| 243 | test_spr_immed 0x1bdb,cccr | |
| 244 | ||
| 245 | set_spr_immed 0x1b5b,cccr | |
| 246 | set_fcc 0xf 0 | |
| 247 | cfckgt fcc0,cc3,cc5,0 | |
| 248 | test_spr_immed 0x1bdb,cccr | |
| 249 | ||
| 250 | set_spr_immed 0x1b5b,cccr | |
| 251 | set_fcc 0x0 0 | |
| 252 | cfckgt fcc0,cc3,cc1,1 | |
| 253 | test_spr_immed 0x1b1b,cccr | |
| 254 | ||
| 255 | set_spr_immed 0x1b5b,cccr | |
| 256 | set_fcc 0x1 0 | |
| 257 | cfckgt fcc0,cc3,cc1,1 | |
| 258 | test_spr_immed 0x1b1b,cccr | |
| 259 | ||
| 260 | set_spr_immed 0x1b5b,cccr | |
| 261 | set_fcc 0x2 0 | |
| 262 | cfckgt fcc0,cc3,cc1,1 | |
| 263 | test_spr_immed 0x1b1b,cccr | |
| 264 | ||
| 265 | set_spr_immed 0x1b5b,cccr | |
| 266 | set_fcc 0x3 0 | |
| 267 | cfckgt fcc0,cc3,cc1,1 | |
| 268 | test_spr_immed 0x1b1b,cccr | |
| 269 | ||
| 270 | set_spr_immed 0x1b5b,cccr | |
| 271 | set_fcc 0x4 0 | |
| 272 | cfckgt fcc0,cc3,cc1,1 | |
| 273 | test_spr_immed 0x1b1b,cccr | |
| 274 | ||
| 275 | set_spr_immed 0x1b5b,cccr | |
| 276 | set_fcc 0x5 0 | |
| 277 | cfckgt fcc0,cc3,cc1,1 | |
| 278 | test_spr_immed 0x1b1b,cccr | |
| 279 | ||
| 280 | set_spr_immed 0x1b5b,cccr | |
| 281 | set_fcc 0x6 0 | |
| 282 | cfckgt fcc0,cc3,cc1,1 | |
| 283 | test_spr_immed 0x1b1b,cccr | |
| 284 | ||
| 285 | set_spr_immed 0x1b5b,cccr | |
| 286 | set_fcc 0x7 0 | |
| 287 | cfckgt fcc0,cc3,cc1,1 | |
| 288 | test_spr_immed 0x1b1b,cccr | |
| 289 | ||
| 290 | set_spr_immed 0x1b5b,cccr | |
| 291 | set_fcc 0x8 0 | |
| 292 | cfckgt fcc0,cc3,cc5,1 | |
| 293 | test_spr_immed 0x1b1b,cccr | |
| 294 | ||
| 295 | set_spr_immed 0x1b5b,cccr | |
| 296 | set_fcc 0x9 0 | |
| 297 | cfckgt fcc0,cc3,cc5,1 | |
| 298 | test_spr_immed 0x1b1b,cccr | |
| 299 | ||
| 300 | set_spr_immed 0x1b5b,cccr | |
| 301 | set_fcc 0xa 0 | |
| 302 | cfckgt fcc0,cc3,cc5,1 | |
| 303 | test_spr_immed 0x1b1b,cccr | |
| 304 | ||
| 305 | set_spr_immed 0x1b5b,cccr | |
| 306 | set_fcc 0xb 0 | |
| 307 | cfckgt fcc0,cc3,cc5,1 | |
| 308 | test_spr_immed 0x1b1b,cccr | |
| 309 | ||
| 310 | set_spr_immed 0x1b5b,cccr | |
| 311 | set_fcc 0xc 0 | |
| 312 | cfckgt fcc0,cc3,cc5,1 | |
| 313 | test_spr_immed 0x1b1b,cccr | |
| 314 | ||
| 315 | set_spr_immed 0x1b5b,cccr | |
| 316 | set_fcc 0xd 0 | |
| 317 | cfckgt fcc0,cc3,cc5,1 | |
| 318 | test_spr_immed 0x1b1b,cccr | |
| 319 | ||
| 320 | set_spr_immed 0x1b5b,cccr | |
| 321 | set_fcc 0xe 0 | |
| 322 | cfckgt fcc0,cc3,cc5,1 | |
| 323 | test_spr_immed 0x1b1b,cccr | |
| 324 | ||
| 325 | set_spr_immed 0x1b5b,cccr | |
| 326 | set_fcc 0xf 0 | |
| 327 | cfckgt fcc0,cc3,cc5,1 | |
| 328 | test_spr_immed 0x1b1b,cccr | |
| 329 | ||
| 330 | set_spr_immed 0x1b5b,cccr | |
| 331 | set_fcc 0x0 0 | |
| 332 | cfckgt fcc0,cc3,cc2,0 | |
| 333 | test_spr_immed 0x1b1b,cccr | |
| 334 | ||
| 335 | set_spr_immed 0x1b5b,cccr | |
| 336 | set_fcc 0x1 0 | |
| 337 | cfckgt fcc0,cc3,cc2,1 | |
| 338 | test_spr_immed 0x1b1b,cccr | |
| 339 | ||
| 340 | set_spr_immed 0x1b5b,cccr | |
| 341 | set_fcc 0x2 0 | |
| 342 | cfckgt fcc0,cc3,cc2,0 | |
| 343 | test_spr_immed 0x1b1b,cccr | |
| 344 | ||
| 345 | set_spr_immed 0x1b5b,cccr | |
| 346 | set_fcc 0x3 0 | |
| 347 | cfckgt fcc0,cc3,cc2,1 | |
| 348 | test_spr_immed 0x1b1b,cccr | |
| 349 | ||
| 350 | set_spr_immed 0x1b5b,cccr | |
| 351 | set_fcc 0x4 0 | |
| 352 | cfckgt fcc0,cc3,cc2,0 | |
| 353 | test_spr_immed 0x1b1b,cccr | |
| 354 | ||
| 355 | set_spr_immed 0x1b5b,cccr | |
| 356 | set_fcc 0x5 0 | |
| 357 | cfckgt fcc0,cc3,cc2,1 | |
| 358 | test_spr_immed 0x1b1b,cccr | |
| 359 | ||
| 360 | set_spr_immed 0x1b5b,cccr | |
| 361 | set_fcc 0x6 0 | |
| 362 | cfckgt fcc0,cc3,cc2,0 | |
| 363 | test_spr_immed 0x1b1b,cccr | |
| 364 | ||
| 365 | set_spr_immed 0x1b5b,cccr | |
| 366 | set_fcc 0x7 0 | |
| 367 | cfckgt fcc0,cc3,cc2,1 | |
| 368 | test_spr_immed 0x1b1b,cccr | |
| 369 | ||
| 370 | set_spr_immed 0x1b5b,cccr | |
| 371 | set_fcc 0x8 0 | |
| 372 | cfckgt fcc0,cc3,cc6,0 | |
| 373 | test_spr_immed 0x1b1b,cccr | |
| 374 | ||
| 375 | set_spr_immed 0x1b5b,cccr | |
| 376 | set_fcc 0x9 0 | |
| 377 | cfckgt fcc0,cc3,cc6,1 | |
| 378 | test_spr_immed 0x1b1b,cccr | |
| 379 | ||
| 380 | set_spr_immed 0x1b5b,cccr | |
| 381 | set_fcc 0xa 0 | |
| 382 | cfckgt fcc0,cc3,cc6,0 | |
| 383 | test_spr_immed 0x1b1b,cccr | |
| 384 | ||
| 385 | set_spr_immed 0x1b5b,cccr | |
| 386 | set_fcc 0xb 0 | |
| 387 | cfckgt fcc0,cc3,cc6,1 | |
| 388 | test_spr_immed 0x1b1b,cccr | |
| 389 | ||
| 390 | set_spr_immed 0x1b5b,cccr | |
| 391 | set_fcc 0xc 0 | |
| 392 | cfckgt fcc0,cc3,cc6,0 | |
| 393 | test_spr_immed 0x1b1b,cccr | |
| 394 | ||
| 395 | set_spr_immed 0x1b5b,cccr | |
| 396 | set_fcc 0xd 0 | |
| 397 | cfckgt fcc0,cc3,cc6,1 | |
| 398 | test_spr_immed 0x1b1b,cccr | |
| 399 | ||
| 400 | set_spr_immed 0x1b5b,cccr | |
| 401 | set_fcc 0xe 0 | |
| 402 | cfckgt fcc0,cc3,cc6,0 | |
| 403 | test_spr_immed 0x1b1b,cccr | |
| 404 | ||
| 405 | set_spr_immed 0x1b5b,cccr | |
| 406 | set_fcc 0xf 0 | |
| 407 | cfckgt fcc0,cc3,cc6,1 | |
| 408 | test_spr_immed 0x1b1b,cccr | |
| 409 | ||
| 410 | set_spr_immed 0x1b5b,cccr | |
| 411 | set_fcc 0x0 0 | |
| 412 | cfckgt fcc0,cc3,cc3,0 | |
| 413 | test_spr_immed 0x1b1b,cccr | |
| 414 | ||
| 415 | set_spr_immed 0x1b5b,cccr | |
| 416 | set_fcc 0x1 0 | |
| 417 | cfckgt fcc0,cc3,cc3,1 | |
| 418 | test_spr_immed 0x1b1b,cccr | |
| 419 | ||
| 420 | set_spr_immed 0x1b5b,cccr | |
| 421 | set_fcc 0x2 0 | |
| 422 | cfckgt fcc0,cc3,cc3,0 | |
| 423 | test_spr_immed 0x1b1b,cccr | |
| 424 | ||
| 425 | set_spr_immed 0x1b5b,cccr | |
| 426 | set_fcc 0x3 0 | |
| 427 | cfckgt fcc0,cc3,cc3,1 | |
| 428 | test_spr_immed 0x1b1b,cccr | |
| 429 | ||
| 430 | set_spr_immed 0x1b5b,cccr | |
| 431 | set_fcc 0x4 0 | |
| 432 | cfckgt fcc0,cc3,cc3,0 | |
| 433 | test_spr_immed 0x1b1b,cccr | |
| 434 | ||
| 435 | set_spr_immed 0x1b5b,cccr | |
| 436 | set_fcc 0x5 0 | |
| 437 | cfckgt fcc0,cc3,cc3,1 | |
| 438 | test_spr_immed 0x1b1b,cccr | |
| 439 | ||
| 440 | set_spr_immed 0x1b5b,cccr | |
| 441 | set_fcc 0x6 0 | |
| 442 | cfckgt fcc0,cc3,cc3,0 | |
| 443 | test_spr_immed 0x1b1b,cccr | |
| 444 | ||
| 445 | set_spr_immed 0x1b5b,cccr | |
| 446 | set_fcc 0x7 0 | |
| 447 | cfckgt fcc0,cc3,cc3,1 | |
| 448 | test_spr_immed 0x1b1b,cccr | |
| 449 | ||
| 450 | set_spr_immed 0x1b5b,cccr | |
| 451 | set_fcc 0x8 0 | |
| 452 | cfckgt fcc0,cc3,cc7,0 | |
| 453 | test_spr_immed 0x1b1b,cccr | |
| 454 | ||
| 455 | set_spr_immed 0x1b5b,cccr | |
| 456 | set_fcc 0x9 0 | |
| 457 | cfckgt fcc0,cc3,cc7,1 | |
| 458 | test_spr_immed 0x1b1b,cccr | |
| 459 | ||
| 460 | set_spr_immed 0x1b5b,cccr | |
| 461 | set_fcc 0xa 0 | |
| 462 | cfckgt fcc0,cc3,cc7,0 | |
| 463 | test_spr_immed 0x1b1b,cccr | |
| 464 | ||
| 465 | set_spr_immed 0x1b5b,cccr | |
| 466 | set_fcc 0xb 0 | |
| 467 | cfckgt fcc0,cc3,cc7,1 | |
| 468 | test_spr_immed 0x1b1b,cccr | |
| 469 | ||
| 470 | set_spr_immed 0x1b5b,cccr | |
| 471 | set_fcc 0xc 0 | |
| 472 | cfckgt fcc0,cc3,cc7,0 | |
| 473 | test_spr_immed 0x1b1b,cccr | |
| 474 | ||
| 475 | set_spr_immed 0x1b5b,cccr | |
| 476 | set_fcc 0xd 0 | |
| 477 | cfckgt fcc0,cc3,cc7,1 | |
| 478 | test_spr_immed 0x1b1b,cccr | |
| 479 | ||
| 480 | set_spr_immed 0x1b5b,cccr | |
| 481 | set_fcc 0xe 0 | |
| 482 | cfckgt fcc0,cc3,cc7,0 | |
| 483 | test_spr_immed 0x1b1b,cccr | |
| 484 | ||
| 485 | set_spr_immed 0x1b5b,cccr | |
| 486 | set_fcc 0xf 0 | |
| 487 | cfckgt fcc0,cc3,cc7,1 | |
| 488 | test_spr_immed 0x1b1b,cccr | |
| 489 | ||
| 490 | pass |