Commit | Line | Data |
---|---|---|
4a306116 | 1 | # frv testcase for cmsubhss $FRi,$FRj,$FRj,$CCi,$cond |
086419a8 | 2 | # mach: frv fr500 fr400 |
4a306116 DB |
3 | |
4 | .include "testutils.inc" | |
5 | ||
6 | start | |
7 | ||
8 | .global cmsubhss | |
9 | cmsubhss: | |
10 | set_spr_immed 0x1b1b,cccr | |
11 | ||
12 | set_fr_iimmed 0x0000,0x0000,fr10 | |
13 | set_fr_iimmed 0x0000,0x0000,fr11 | |
14 | cmsubhss fr10,fr11,fr12,cc0,1 | |
15 | test_fr_limmed 0x0000,0x0000,fr12 | |
16 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
17 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
18 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
19 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
20 | ||
21 | set_fr_iimmed 0xdead,0x0000,fr10 | |
22 | set_fr_iimmed 0x0000,0xbeef,fr11 | |
23 | cmsubhss fr10,fr11,fr12,cc0,1 | |
24 | test_fr_limmed 0xdead,0x4111,fr12 | |
25 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
26 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
27 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
28 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
29 | ||
30 | set_fr_iimmed 0x0000,0xdead,fr10 | |
31 | set_fr_iimmed 0xbeef,0x0000,fr11 | |
32 | cmsubhss fr10,fr11,fr12,cc0,1 | |
33 | test_fr_limmed 0x4111,0xdead,fr12 | |
34 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
35 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
36 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
37 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
38 | ||
39 | set_fr_iimmed 0x1234,0x5678,fr10 | |
40 | set_fr_iimmed 0x1111,0x1111,fr11 | |
41 | cmsubhss fr10,fr11,fr12,cc0,1 | |
42 | test_fr_limmed 0x0123,0x4567,fr12 | |
43 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
44 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
45 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
46 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
47 | ||
48 | set_fr_iimmed 0x1234,0x5678,fr10 | |
49 | set_fr_iimmed 0xffff,0xffff,fr11 | |
50 | cmsubhss fr10,fr11,fr12,cc0,1 | |
51 | test_fr_limmed 0x1235,0x5679,fr12 | |
52 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
53 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
54 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
55 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
56 | ||
57 | set_spr_immed 0,msr0 | |
58 | set_fr_iimmed 0x7ffe,0x7ffe,fr10 | |
59 | set_fr_iimmed 0xfffe,0xffff,fr11 | |
60 | cmsubhss fr10,fr11,fr12,cc4,1 | |
61 | test_fr_limmed 0x7fff,0x7fff,fr12 | |
62 | test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set | |
63 | test_spr_bits 2,1,1,msr0 ; msr0.ovf set | |
64 | test_spr_bits 1,0,1,msr0 ; msr0.aovf set | |
65 | test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set | |
66 | ||
67 | set_spr_immed 0,msr0 | |
68 | set_fr_iimmed 0x8001,0x8001,fr10 | |
69 | set_fr_iimmed 0x0001,0x0002,fr11 | |
70 | cmsubhss fr10,fr11,fr12,cc4,1 | |
71 | test_fr_limmed 0x8000,0x8000,fr12 | |
72 | test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set | |
73 | test_spr_bits 2,1,1,msr0 ; msr0.ovf set | |
74 | test_spr_bits 1,0,1,msr0 ; msr0.aovf set | |
75 | test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set | |
76 | ||
77 | set_spr_immed 0,msr0 | |
78 | set_fr_iimmed 0x8001,0x8001,fr10 | |
79 | set_fr_iimmed 0x0002,0x0001,fr11 | |
80 | cmsubhss fr10,fr11,fr12,cc4,1 | |
81 | test_fr_limmed 0x8000,0x8000,fr12 | |
82 | test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set | |
83 | test_spr_bits 2,1,1,msr0 ; msr0.ovf set | |
84 | test_spr_bits 1,0,1,msr0 ; msr0.aovf set | |
85 | test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set | |
86 | ||
87 | set_spr_immed 0,msr0 | |
88 | set_spr_immed 0,msr1 | |
89 | set_fr_iimmed 0x0001,0x0001,fr10 | |
90 | set_fr_iimmed 0x8000,0x8000,fr11 | |
91 | cmsubhss.p fr10,fr10,fr12,cc4,1 | |
92 | cmsubhss fr11,fr10,fr13,cc4,1 | |
93 | test_fr_limmed 0x0000,0x0000,fr12 | |
94 | test_fr_limmed 0x8000,0x8000,fr13 | |
95 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
96 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
97 | test_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is set | |
98 | test_spr_bits 2,1,1,msr1 ; msr1.ovf set | |
99 | test_spr_bits 1,0,1,msr0 ; msr0.aovf set | |
100 | test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set | |
101 | ||
102 | set_spr_immed 0,msr0 | |
103 | set_spr_immed 0,msr1 | |
104 | set_fr_iimmed 0x0000,0x0000,fr10 | |
105 | set_fr_iimmed 0x0000,0x0000,fr11 | |
106 | cmsubhss fr10,fr11,fr12,cc1,0 | |
107 | test_fr_limmed 0x0000,0x0000,fr12 | |
108 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
109 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
110 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
111 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
112 | ||
113 | set_fr_iimmed 0xdead,0x0000,fr10 | |
114 | set_fr_iimmed 0x0000,0xbeef,fr11 | |
115 | cmsubhss fr10,fr11,fr12,cc1,0 | |
116 | test_fr_limmed 0xdead,0x4111,fr12 | |
117 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
118 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
119 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
120 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
121 | ||
122 | set_fr_iimmed 0x0000,0xdead,fr10 | |
123 | set_fr_iimmed 0xbeef,0x0000,fr11 | |
124 | cmsubhss fr10,fr11,fr12,cc1,0 | |
125 | test_fr_limmed 0x4111,0xdead,fr12 | |
126 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
127 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
128 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
129 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
130 | ||
131 | set_fr_iimmed 0x1234,0x5678,fr10 | |
132 | set_fr_iimmed 0x1111,0x1111,fr11 | |
133 | cmsubhss fr10,fr11,fr12,cc1,0 | |
134 | test_fr_limmed 0x0123,0x4567,fr12 | |
135 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
136 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
137 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
138 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
139 | ||
140 | set_fr_iimmed 0x1234,0x5678,fr10 | |
141 | set_fr_iimmed 0xffff,0xffff,fr11 | |
142 | cmsubhss fr10,fr11,fr12,cc1,0 | |
143 | test_fr_limmed 0x1235,0x5679,fr12 | |
144 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
145 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
146 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
147 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
148 | ||
149 | set_spr_immed 0,msr0 | |
150 | set_fr_iimmed 0x7ffe,0x7ffe,fr10 | |
151 | set_fr_iimmed 0xfffe,0xffff,fr11 | |
152 | cmsubhss fr10,fr11,fr12,cc5,0 | |
153 | test_fr_limmed 0x7fff,0x7fff,fr12 | |
154 | test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set | |
155 | test_spr_bits 2,1,1,msr0 ; msr0.ovf set | |
156 | test_spr_bits 1,0,1,msr0 ; msr0.aovf set | |
157 | test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set | |
158 | ||
159 | set_spr_immed 0,msr0 | |
160 | set_fr_iimmed 0x8001,0x8001,fr10 | |
161 | set_fr_iimmed 0x0001,0x0002,fr11 | |
162 | cmsubhss fr10,fr11,fr12,cc5,0 | |
163 | test_fr_limmed 0x8000,0x8000,fr12 | |
164 | test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set | |
165 | test_spr_bits 2,1,1,msr0 ; msr0.ovf set | |
166 | test_spr_bits 1,0,1,msr0 ; msr0.aovf set | |
167 | test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set | |
168 | ||
169 | set_spr_immed 0,msr0 | |
170 | set_fr_iimmed 0x8001,0x8001,fr10 | |
171 | set_fr_iimmed 0x0002,0x0001,fr11 | |
172 | cmsubhss fr10,fr11,fr12,cc5,0 | |
173 | test_fr_limmed 0x8000,0x8000,fr12 | |
174 | test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set | |
175 | test_spr_bits 2,1,1,msr0 ; msr0.ovf set | |
176 | test_spr_bits 1,0,1,msr0 ; msr0.aovf set | |
177 | test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set | |
178 | ||
179 | set_spr_immed 0,msr0 | |
180 | set_spr_immed 0,msr1 | |
181 | set_fr_iimmed 0x0001,0x0001,fr10 | |
182 | set_fr_iimmed 0x8000,0x8000,fr11 | |
183 | cmsubhss.p fr10,fr10,fr12,cc5,0 | |
184 | cmsubhss fr11,fr10,fr13,cc5,0 | |
185 | test_fr_limmed 0x0000,0x0000,fr12 | |
186 | test_fr_limmed 0x8000,0x8000,fr13 | |
187 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
188 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
189 | test_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is set | |
190 | test_spr_bits 2,1,1,msr1 ; msr1.ovf set | |
191 | test_spr_bits 1,0,1,msr0 ; msr0.aovf set | |
192 | test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set | |
193 | ||
194 | set_fr_iimmed 0xdead,0xbeef,fr12 | |
195 | set_spr_immed 0,msr0 | |
196 | set_spr_immed 0,msr1 | |
197 | set_fr_iimmed 0x0000,0x0000,fr10 | |
198 | set_fr_iimmed 0x0000,0x0000,fr11 | |
199 | cmsubhss fr10,fr11,fr12,cc0,0 | |
200 | test_fr_limmed 0xdead,0xbeef,fr12 | |
201 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
202 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
203 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
204 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
205 | ||
206 | set_fr_iimmed 0xdead,0x0000,fr10 | |
207 | set_fr_iimmed 0x0000,0xbeef,fr11 | |
208 | cmsubhss fr10,fr11,fr12,cc0,0 | |
209 | test_fr_limmed 0xdead,0xbeef,fr12 | |
210 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
211 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
212 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
213 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
214 | ||
215 | set_fr_iimmed 0x0000,0xdead,fr10 | |
216 | set_fr_iimmed 0xbeef,0x0000,fr11 | |
217 | cmsubhss fr10,fr11,fr12,cc0,0 | |
218 | test_fr_limmed 0xdead,0xbeef,fr12 | |
219 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
220 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
221 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
222 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
223 | ||
224 | set_fr_iimmed 0x1234,0x5678,fr10 | |
225 | set_fr_iimmed 0x1111,0x1111,fr11 | |
226 | cmsubhss fr10,fr11,fr12,cc0,0 | |
227 | test_fr_limmed 0xdead,0xbeef,fr12 | |
228 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
229 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
230 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
231 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
232 | ||
233 | set_fr_iimmed 0x1234,0x5678,fr10 | |
234 | set_fr_iimmed 0xffff,0xffff,fr11 | |
235 | cmsubhss fr10,fr11,fr12,cc0,0 | |
236 | test_fr_limmed 0xdead,0xbeef,fr12 | |
237 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
238 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
239 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
240 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
241 | ||
242 | set_spr_immed 0,msr0 | |
243 | set_fr_iimmed 0x7ffe,0x7ffe,fr10 | |
244 | set_fr_iimmed 0xfffe,0xffff,fr11 | |
245 | cmsubhss fr10,fr11,fr12,cc4,0 | |
246 | test_fr_limmed 0xdead,0xbeef,fr12 | |
247 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
248 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
249 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
250 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
251 | ||
252 | set_spr_immed 0,msr0 | |
253 | set_fr_iimmed 0x8001,0x8001,fr10 | |
254 | set_fr_iimmed 0x0001,0x0002,fr11 | |
255 | cmsubhss fr10,fr11,fr12,cc4,0 | |
256 | test_fr_limmed 0xdead,0xbeef,fr12 | |
257 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
258 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
259 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
260 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
261 | ||
262 | set_spr_immed 0,msr0 | |
263 | set_fr_iimmed 0x8001,0x8001,fr10 | |
264 | set_fr_iimmed 0x0002,0x0001,fr11 | |
265 | cmsubhss fr10,fr11,fr12,cc4,0 | |
266 | test_fr_limmed 0xdead,0xbeef,fr12 | |
267 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
268 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
269 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
270 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
271 | ||
272 | set_fr_iimmed 0xbeef,0xdead,fr13 | |
273 | set_spr_immed 0,msr0 | |
274 | set_spr_immed 0,msr1 | |
275 | set_fr_iimmed 0x0001,0x0001,fr10 | |
276 | set_fr_iimmed 0x8000,0x8000,fr11 | |
277 | cmsubhss.p fr10,fr10,fr12,cc4,0 | |
278 | cmsubhss fr11,fr10,fr13,cc4,0 | |
279 | test_fr_limmed 0xdead,0xbeef,fr12 | |
280 | test_fr_limmed 0xbeef,0xdead,fr13 | |
281 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
282 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
283 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
284 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
285 | ||
286 | set_fr_iimmed 0xdead,0xbeef,fr12 | |
287 | set_spr_immed 0,msr0 | |
288 | set_spr_immed 0,msr1 | |
289 | set_fr_iimmed 0x0000,0x0000,fr10 | |
290 | set_fr_iimmed 0x0000,0x0000,fr11 | |
291 | cmsubhss fr10,fr11,fr12,cc1,1 | |
292 | test_fr_limmed 0xdead,0xbeef,fr12 | |
293 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
294 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
295 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
296 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
297 | ||
298 | set_fr_iimmed 0xdead,0x0000,fr10 | |
299 | set_fr_iimmed 0x0000,0xbeef,fr11 | |
300 | cmsubhss fr10,fr11,fr12,cc1,1 | |
301 | test_fr_limmed 0xdead,0xbeef,fr12 | |
302 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
303 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
304 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
305 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
306 | ||
307 | set_fr_iimmed 0x0000,0xdead,fr10 | |
308 | set_fr_iimmed 0xbeef,0x0000,fr11 | |
309 | cmsubhss fr10,fr11,fr12,cc1,1 | |
310 | test_fr_limmed 0xdead,0xbeef,fr12 | |
311 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
312 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
313 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
314 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
315 | ||
316 | set_fr_iimmed 0x1234,0x5678,fr10 | |
317 | set_fr_iimmed 0x1111,0x1111,fr11 | |
318 | cmsubhss fr10,fr11,fr12,cc1,1 | |
319 | test_fr_limmed 0xdead,0xbeef,fr12 | |
320 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
321 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
322 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
323 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
324 | ||
325 | set_fr_iimmed 0x1234,0x5678,fr10 | |
326 | set_fr_iimmed 0xffff,0xffff,fr11 | |
327 | cmsubhss fr10,fr11,fr12,cc1,1 | |
328 | test_fr_limmed 0xdead,0xbeef,fr12 | |
329 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
330 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
331 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
332 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
333 | ||
334 | set_spr_immed 0,msr0 | |
335 | set_fr_iimmed 0x7ffe,0x7ffe,fr10 | |
336 | set_fr_iimmed 0xfffe,0xffff,fr11 | |
337 | cmsubhss fr10,fr11,fr12,cc5,1 | |
338 | test_fr_limmed 0xdead,0xbeef,fr12 | |
339 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
340 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
341 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
342 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
343 | ||
344 | set_spr_immed 0,msr0 | |
345 | set_fr_iimmed 0x8001,0x8001,fr10 | |
346 | set_fr_iimmed 0x0001,0x0002,fr11 | |
347 | cmsubhss fr10,fr11,fr12,cc5,1 | |
348 | test_fr_limmed 0xdead,0xbeef,fr12 | |
349 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
350 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
351 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
352 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
353 | ||
354 | set_spr_immed 0,msr0 | |
355 | set_fr_iimmed 0x8001,0x8001,fr10 | |
356 | set_fr_iimmed 0x0002,0x0001,fr11 | |
357 | cmsubhss fr10,fr11,fr12,cc5,1 | |
358 | test_fr_limmed 0xdead,0xbeef,fr12 | |
359 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
360 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
361 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
362 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
363 | ||
364 | set_fr_iimmed 0xbeef,0xdead,fr13 | |
365 | set_spr_immed 0,msr0 | |
366 | set_spr_immed 0,msr1 | |
367 | set_fr_iimmed 0x0001,0x0001,fr10 | |
368 | set_fr_iimmed 0x8000,0x8000,fr11 | |
369 | cmsubhss.p fr10,fr10,fr12,cc5,1 | |
370 | cmsubhss fr11,fr10,fr13,cc5,1 | |
371 | test_fr_limmed 0xdead,0xbeef,fr12 | |
372 | test_fr_limmed 0xbeef,0xdead,fr13 | |
373 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
374 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
375 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
376 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
377 | ||
378 | set_fr_iimmed 0xdead,0xbeef,fr12 | |
379 | set_spr_immed 0,msr0 | |
380 | set_spr_immed 0,msr1 | |
381 | set_fr_iimmed 0x0000,0x0000,fr10 | |
382 | set_fr_iimmed 0x0000,0x0000,fr11 | |
383 | cmsubhss fr10,fr11,fr12,cc2,1 | |
384 | test_fr_limmed 0xdead,0xbeef,fr12 | |
385 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
386 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
387 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
388 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
389 | ||
390 | set_fr_iimmed 0xdead,0x0000,fr10 | |
391 | set_fr_iimmed 0x0000,0xbeef,fr11 | |
392 | cmsubhss fr10,fr11,fr12,cc2,0 | |
393 | test_fr_limmed 0xdead,0xbeef,fr12 | |
394 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
395 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
396 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
397 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
398 | ||
399 | set_fr_iimmed 0x0000,0xdead,fr10 | |
400 | set_fr_iimmed 0xbeef,0x0000,fr11 | |
401 | cmsubhss fr10,fr11,fr12,cc2,1 | |
402 | test_fr_limmed 0xdead,0xbeef,fr12 | |
403 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
404 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
405 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
406 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
407 | ||
408 | set_fr_iimmed 0x1234,0x5678,fr10 | |
409 | set_fr_iimmed 0x1111,0x1111,fr11 | |
410 | cmsubhss fr10,fr11,fr12,cc2,0 | |
411 | test_fr_limmed 0xdead,0xbeef,fr12 | |
412 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
413 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
414 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
415 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
416 | ||
417 | set_fr_iimmed 0x1234,0x5678,fr10 | |
418 | set_fr_iimmed 0xffff,0xffff,fr11 | |
419 | cmsubhss fr10,fr11,fr12,cc2,1 | |
420 | test_fr_limmed 0xdead,0xbeef,fr12 | |
421 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
422 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
423 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
424 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
425 | ||
426 | set_spr_immed 0,msr0 | |
427 | set_fr_iimmed 0x7ffe,0x7ffe,fr10 | |
428 | set_fr_iimmed 0xfffe,0xffff,fr11 | |
429 | cmsubhss fr10,fr11,fr12,cc6,0 | |
430 | test_fr_limmed 0xdead,0xbeef,fr12 | |
431 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
432 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
433 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
434 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
435 | ||
436 | set_spr_immed 0,msr0 | |
437 | set_fr_iimmed 0x8001,0x8001,fr10 | |
438 | set_fr_iimmed 0x0001,0x0002,fr11 | |
439 | cmsubhss fr10,fr11,fr12,cc6,1 | |
440 | test_fr_limmed 0xdead,0xbeef,fr12 | |
441 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
442 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
443 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
444 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
445 | ||
446 | set_spr_immed 0,msr0 | |
447 | set_fr_iimmed 0x8001,0x8001,fr10 | |
448 | set_fr_iimmed 0x0002,0x0001,fr11 | |
449 | cmsubhss fr10,fr11,fr12,cc6,0 | |
450 | test_fr_limmed 0xdead,0xbeef,fr12 | |
451 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
452 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
453 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
454 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
455 | ||
456 | set_fr_iimmed 0xbeef,0xdead,fr13 | |
457 | set_spr_immed 0,msr0 | |
458 | set_spr_immed 0,msr1 | |
459 | set_fr_iimmed 0x0001,0x0001,fr10 | |
460 | set_fr_iimmed 0x8000,0x8000,fr11 | |
461 | cmsubhss.p fr10,fr10,fr12,cc6,1 | |
462 | cmsubhss fr11,fr10,fr13,cc6,0 | |
463 | test_fr_limmed 0xdead,0xbeef,fr12 | |
464 | test_fr_limmed 0xbeef,0xdead,fr13 | |
465 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
466 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
467 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
468 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
469 | ; | |
470 | set_fr_iimmed 0xdead,0xbeef,fr12 | |
471 | set_spr_immed 0,msr0 | |
472 | set_spr_immed 0,msr1 | |
473 | set_fr_iimmed 0x0000,0x0000,fr10 | |
474 | set_fr_iimmed 0x0000,0x0000,fr11 | |
475 | cmsubhss fr10,fr11,fr12,cc3,1 | |
476 | test_fr_limmed 0xdead,0xbeef,fr12 | |
477 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
478 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
479 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
480 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
481 | ||
482 | set_fr_iimmed 0xdead,0x0000,fr10 | |
483 | set_fr_iimmed 0x0000,0xbeef,fr11 | |
484 | cmsubhss fr10,fr11,fr12,cc3,0 | |
485 | test_fr_limmed 0xdead,0xbeef,fr12 | |
486 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
487 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
488 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
489 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
490 | ||
491 | set_fr_iimmed 0x0000,0xdead,fr10 | |
492 | set_fr_iimmed 0xbeef,0x0000,fr11 | |
493 | cmsubhss fr10,fr11,fr12,cc3,1 | |
494 | test_fr_limmed 0xdead,0xbeef,fr12 | |
495 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
496 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
497 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
498 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
499 | ||
500 | set_fr_iimmed 0x1234,0x5678,fr10 | |
501 | set_fr_iimmed 0x1111,0x1111,fr11 | |
502 | cmsubhss fr10,fr11,fr12,cc3,0 | |
503 | test_fr_limmed 0xdead,0xbeef,fr12 | |
504 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
505 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
506 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
507 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
508 | ||
509 | set_fr_iimmed 0x1234,0x5678,fr10 | |
510 | set_fr_iimmed 0xffff,0xffff,fr11 | |
511 | cmsubhss fr10,fr11,fr12,cc3,1 | |
512 | test_fr_limmed 0xdead,0xbeef,fr12 | |
513 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
514 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
515 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
516 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
517 | ||
518 | set_spr_immed 0,msr0 | |
519 | set_fr_iimmed 0x7ffe,0x7ffe,fr10 | |
520 | set_fr_iimmed 0xfffe,0xffff,fr11 | |
521 | cmsubhss fr10,fr11,fr12,cc7,0 | |
522 | test_fr_limmed 0xdead,0xbeef,fr12 | |
523 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
524 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
525 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
526 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
527 | ||
528 | set_spr_immed 0,msr0 | |
529 | set_fr_iimmed 0x8001,0x8001,fr10 | |
530 | set_fr_iimmed 0x0001,0x0002,fr11 | |
531 | cmsubhss fr10,fr11,fr12,cc7,1 | |
532 | test_fr_limmed 0xdead,0xbeef,fr12 | |
533 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
534 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
535 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
536 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
537 | ||
538 | set_spr_immed 0,msr0 | |
539 | set_fr_iimmed 0x8001,0x8001,fr10 | |
540 | set_fr_iimmed 0x0002,0x0001,fr11 | |
541 | cmsubhss fr10,fr11,fr12,cc7,0 | |
542 | test_fr_limmed 0xdead,0xbeef,fr12 | |
543 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
544 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
545 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
546 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
547 | ||
548 | set_fr_iimmed 0xbeef,0xdead,fr13 | |
549 | set_spr_immed 0,msr0 | |
550 | set_spr_immed 0,msr1 | |
551 | set_fr_iimmed 0x0001,0x0001,fr10 | |
552 | set_fr_iimmed 0x8000,0x8000,fr11 | |
553 | cmsubhss.p fr10,fr10,fr12,cc7,1 | |
554 | cmsubhss fr11,fr10,fr13,cc7,0 | |
555 | test_fr_limmed 0xdead,0xbeef,fr12 | |
556 | test_fr_limmed 0xbeef,0xdead,fr13 | |
557 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
558 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
559 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
560 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
561 | ||
562 | pass |