Commit | Line | Data |
---|---|---|
4a306116 DB |
1 | # frv testcase for fblglr $FCCi,$hint |
2 | # mach: all | |
3 | ||
4 | .include "testutils.inc" | |
5 | ||
6 | start | |
7 | ||
8 | .global fblglr | |
9 | fblglr: | |
10 | set_spr_addr bad,lr | |
11 | set_fcc 0x0 0 | |
12 | fblglr fcc0,0 | |
13 | ||
14 | set_spr_addr bad,lr | |
15 | set_fcc 0x1 1 | |
16 | fblglr fcc1,1 | |
17 | ||
18 | set_spr_addr ok3,lr | |
19 | set_fcc 0x2 2 | |
20 | fblglr fcc2,2 | |
21 | fail | |
22 | ok3: | |
23 | set_spr_addr ok4,lr | |
24 | set_fcc 0x3 3 | |
25 | fblglr fcc3,3 | |
26 | fail | |
27 | ok4: | |
28 | set_spr_addr ok5,lr | |
29 | set_fcc 0x4 0 | |
30 | fblglr fcc0,0 | |
31 | fail | |
32 | ok5: | |
33 | set_spr_addr ok6,lr | |
34 | set_fcc 0x5 1 | |
35 | fblglr fcc1,1 | |
36 | fail | |
37 | ok6: | |
38 | set_spr_addr ok7,lr | |
39 | set_fcc 0x6 2 | |
40 | fblglr fcc2,2 | |
41 | fail | |
42 | ok7: | |
43 | set_spr_addr ok8,lr | |
44 | set_fcc 0x7 3 | |
45 | fblglr fcc3,3 | |
46 | fail | |
47 | ok8: | |
48 | set_spr_addr bad,lr | |
49 | set_fcc 0x8 0 | |
50 | fblglr fcc0,0 | |
51 | ||
52 | set_spr_addr bad,lr | |
53 | set_fcc 0x9 1 | |
54 | fblglr fcc1,1 | |
55 | ||
56 | set_spr_addr okb,lr | |
57 | set_fcc 0xa 2 | |
58 | fblglr fcc2,2 | |
59 | fail | |
60 | okb: | |
61 | set_spr_addr okc,lr | |
62 | set_fcc 0xb 3 | |
63 | fblglr fcc3,3 | |
64 | fail | |
65 | okc: | |
66 | set_spr_addr okd,lr | |
67 | set_fcc 0xc 0 | |
68 | fblglr fcc0,0 | |
69 | fail | |
70 | okd: | |
71 | set_spr_addr oke,lr | |
72 | set_fcc 0xd 1 | |
73 | fblglr fcc1,1 | |
74 | fail | |
75 | oke: | |
76 | set_spr_addr okf,lr | |
77 | set_fcc 0xe 2 | |
78 | fblglr fcc2,2 | |
79 | fail | |
80 | okf: | |
81 | set_spr_addr okg,lr | |
82 | set_fcc 0xf 3 | |
83 | fblglr fcc3,3 | |
84 | fail | |
85 | okg: | |
86 | pass | |
87 | bad: | |
88 | fail |