Commit | Line | Data |
---|---|---|
4a306116 DB |
1 | # frv testcase for fcbralr $ccond |
2 | # mach: all | |
3 | ||
4 | .include "testutils.inc" | |
5 | ||
6 | start | |
7 | ||
8 | .global fcbralr | |
9 | fcbralr: | |
10 | ; ccond is true | |
11 | set_spr_immed 128,lcr | |
12 | set_spr_addr ok1,lr | |
13 | set_fcc 0x0 0 | |
14 | fcbralr 0 | |
15 | fail | |
16 | ok1: | |
17 | set_spr_addr ok2,lr | |
18 | set_fcc 0x1 1 | |
19 | fcbralr 0 | |
20 | fail | |
21 | ok2: | |
22 | set_spr_addr ok3,lr | |
23 | set_fcc 0x2 2 | |
24 | fcbralr 0 | |
25 | fail | |
26 | ok3: | |
27 | set_spr_addr ok4,lr | |
28 | set_fcc 0x3 3 | |
29 | fcbralr 0 | |
30 | fail | |
31 | ok4: | |
32 | set_spr_addr ok5,lr | |
33 | set_fcc 0x4 0 | |
34 | fcbralr 0 | |
35 | fail | |
36 | ok5: | |
37 | set_spr_addr ok6,lr | |
38 | set_fcc 0x5 1 | |
39 | fcbralr 0 | |
40 | fail | |
41 | ok6: | |
42 | set_spr_addr ok7,lr | |
43 | set_fcc 0x6 2 | |
44 | fcbralr 0 | |
45 | fail | |
46 | ok7: | |
47 | set_spr_addr ok8,lr | |
48 | set_fcc 0x7 3 | |
49 | fcbralr 0 | |
50 | fail | |
51 | ok8: | |
52 | set_spr_addr ok9,lr | |
53 | set_fcc 0x8 0 | |
54 | fcbralr 0 | |
55 | fail | |
56 | ok9: | |
57 | set_spr_addr oka,lr | |
58 | set_fcc 0x9 1 | |
59 | fcbralr 0 | |
60 | fail | |
61 | oka: | |
62 | set_spr_addr okb,lr | |
63 | set_fcc 0xa 2 | |
64 | fcbralr 0 | |
65 | fail | |
66 | okb: | |
67 | set_spr_addr okc,lr | |
68 | set_fcc 0xb 3 | |
69 | fcbralr 0 | |
70 | fail | |
71 | okc: | |
72 | set_spr_addr okd,lr | |
73 | set_fcc 0xc 0 | |
74 | fcbralr 0 | |
75 | fail | |
76 | okd: | |
77 | set_spr_addr oke,lr | |
78 | set_fcc 0xd 1 | |
79 | fcbralr 0 | |
80 | fail | |
81 | oke: | |
82 | set_spr_addr okf,lr | |
83 | set_fcc 0xe 2 | |
84 | fcbralr 0 | |
85 | fail | |
86 | okf: | |
87 | set_spr_addr okg,lr | |
88 | set_fcc 0xf 3 | |
89 | fcbralr 0 | |
90 | fail | |
91 | okg: | |
92 | ||
93 | ; ccond is true | |
94 | set_spr_immed 1,lcr | |
95 | set_spr_addr okh,lr | |
96 | set_fcc 0x0 0 | |
97 | fcbralr 1 | |
98 | fail | |
99 | okh: | |
100 | set_spr_immed 1,lcr | |
101 | set_spr_addr oki,lr | |
102 | set_fcc 0x1 1 | |
103 | fcbralr 1 | |
104 | fail | |
105 | oki: | |
106 | set_spr_immed 1,lcr | |
107 | set_spr_addr okj,lr | |
108 | set_fcc 0x2 2 | |
109 | fcbralr 1 | |
110 | fail | |
111 | okj: | |
112 | set_spr_immed 1,lcr | |
113 | set_spr_addr okk,lr | |
114 | set_fcc 0x3 3 | |
115 | fcbralr 1 | |
116 | fail | |
117 | okk: | |
118 | set_spr_immed 1,lcr | |
119 | set_spr_addr okl,lr | |
120 | set_fcc 0x4 0 | |
121 | fcbralr 1 | |
122 | fail | |
123 | okl: | |
124 | set_spr_immed 1,lcr | |
125 | set_spr_addr okm,lr | |
126 | set_fcc 0x5 1 | |
127 | fcbralr 1 | |
128 | fail | |
129 | okm: | |
130 | set_spr_immed 1,lcr | |
131 | set_spr_addr okn,lr | |
132 | set_fcc 0x6 2 | |
133 | fcbralr 1 | |
134 | fail | |
135 | okn: | |
136 | set_spr_immed 1,lcr | |
137 | set_spr_addr oko,lr | |
138 | set_fcc 0x7 3 | |
139 | fcbralr 1 | |
140 | fail | |
141 | oko: | |
142 | set_spr_immed 1,lcr | |
143 | set_spr_addr okp,lr | |
144 | set_fcc 0x8 0 | |
145 | fcbralr 1 | |
146 | fail | |
147 | okp: | |
148 | set_spr_immed 1,lcr | |
149 | set_spr_addr okq,lr | |
150 | set_fcc 0x9 1 | |
151 | fcbralr 1 | |
152 | fail | |
153 | okq: | |
154 | set_spr_immed 1,lcr | |
155 | set_spr_addr okr,lr | |
156 | set_fcc 0xa 2 | |
157 | fcbralr 1 | |
158 | fail | |
159 | okr: | |
160 | set_spr_immed 1,lcr | |
161 | set_spr_addr oks,lr | |
162 | set_fcc 0xb 3 | |
163 | fcbralr 1 | |
164 | fail | |
165 | oks: | |
166 | set_spr_immed 1,lcr | |
167 | set_spr_addr okt,lr | |
168 | set_fcc 0xc 0 | |
169 | fcbralr 1 | |
170 | fail | |
171 | okt: | |
172 | set_spr_immed 1,lcr | |
173 | set_spr_addr oku,lr | |
174 | set_fcc 0xd 1 | |
175 | fcbralr 1 | |
176 | fail | |
177 | oku: | |
178 | set_spr_immed 1,lcr | |
179 | set_spr_addr okv,lr | |
180 | set_fcc 0xe 2 | |
181 | fcbralr 1 | |
182 | fail | |
183 | okv: | |
184 | set_spr_immed 1,lcr | |
185 | set_spr_addr okw,lr | |
186 | set_fcc 0xf 3 | |
187 | fcbralr 1 | |
188 | fail | |
189 | okw: | |
190 | ; ccond is false | |
191 | set_spr_immed 128,lcr | |
192 | ||
193 | set_fcc 0x0 0 | |
194 | fcbralr 1 | |
195 | set_fcc 0x1 1 | |
196 | fcbralr 1 | |
197 | set_fcc 0x2 2 | |
198 | fcbralr 1 | |
199 | set_fcc 0x3 3 | |
200 | fcbralr 1 | |
201 | set_fcc 0x4 0 | |
202 | fcbralr 1 | |
203 | set_fcc 0x5 1 | |
204 | fcbralr 1 | |
205 | set_fcc 0x6 2 | |
206 | fcbralr 1 | |
207 | set_fcc 0x7 3 | |
208 | fcbralr 1 | |
209 | set_fcc 0x8 0 | |
210 | fcbralr 1 | |
211 | set_fcc 0x9 1 | |
212 | fcbralr 1 | |
213 | set_fcc 0xa 2 | |
214 | fcbralr 1 | |
215 | set_fcc 0xb 3 | |
216 | fcbralr 1 | |
217 | set_fcc 0xc 0 | |
218 | fcbralr 1 | |
219 | set_fcc 0xd 1 | |
220 | fcbralr 1 | |
221 | set_fcc 0xe 2 | |
222 | fcbralr 1 | |
223 | set_fcc 0xf 3 | |
224 | fcbralr 1 | |
225 | ||
226 | ; ccond is false | |
227 | set_spr_immed 1,lcr | |
228 | set_fcc 0x0 0 | |
229 | fcbralr 0 | |
230 | set_spr_immed 1,lcr | |
231 | set_fcc 0x1 1 | |
232 | fcbralr 0 | |
233 | set_spr_immed 1,lcr | |
234 | set_fcc 0x2 2 | |
235 | fcbralr 0 | |
236 | set_spr_immed 1,lcr | |
237 | set_fcc 0x3 3 | |
238 | fcbralr 0 | |
239 | set_spr_immed 1,lcr | |
240 | set_fcc 0x4 0 | |
241 | fcbralr 0 | |
242 | set_spr_immed 1,lcr | |
243 | set_fcc 0x5 1 | |
244 | fcbralr 0 | |
245 | set_spr_immed 1,lcr | |
246 | set_fcc 0x6 2 | |
247 | fcbralr 0 | |
248 | set_spr_immed 1,lcr | |
249 | set_fcc 0x7 3 | |
250 | fcbralr 0 | |
251 | set_spr_immed 1,lcr | |
252 | set_fcc 0x8 0 | |
253 | fcbralr 0 | |
254 | set_spr_immed 1,lcr | |
255 | set_fcc 0x9 1 | |
256 | fcbralr 0 | |
257 | set_spr_immed 1,lcr | |
258 | set_fcc 0xa 2 | |
259 | fcbralr 0 | |
260 | set_spr_immed 1,lcr | |
261 | set_fcc 0xb 3 | |
262 | fcbralr 0 | |
263 | set_spr_immed 1,lcr | |
264 | set_fcc 0xc 0 | |
265 | fcbralr 0 | |
266 | set_spr_immed 1,lcr | |
267 | set_fcc 0xd 1 | |
268 | fcbralr 0 | |
269 | set_spr_immed 1,lcr | |
270 | set_fcc 0xe 2 | |
271 | fcbralr 0 | |
272 | set_spr_immed 1,lcr | |
273 | set_fcc 0xf 3 | |
274 | fcbralr 0 | |
275 | ||
276 | pass |