projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 4a306116 DB |
1 | # frv testcase for mabshs $FRj,$FRk |
| 2 | # mach: fr400 | |
| 3 | ||
| 4 | .include "testutils.inc" | |
| 5 | ||
| 6 | start | |
| 7 | ||
| 8 | .global mabshs | |
| 9 | mabshs: | |
| 10 | set_fr_iimmed 0x0000,0x0000,fr10 | |
| 11 | mabshs fr10,fr11 | |
| 12 | test_fr_limmed 0x0000,0x0000,fr11 | |
| 13 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
| 14 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
| 15 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
| 16 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
| 17 | ||
| 18 | set_fr_iimmed 0x0001,0xffff,fr10 | |
| 19 | mabshs fr10,fr11 | |
| 20 | test_fr_limmed 0x0001,0x0001,fr11 | |
| 21 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
| 22 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
| 23 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
| 24 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
| 25 | ||
| 26 | set_fr_iimmed 0x7fff,0x8001,fr10 | |
| 27 | mabshs fr10,fr11 | |
| 28 | test_fr_limmed 0x7fff,0x7fff,fr11 | |
| 29 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
| 30 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
| 31 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
| 32 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
| 33 | ||
| 34 | set_spr_immed 0,msr0 | |
| 35 | set_fr_iimmed 0x7fff,0x8000,fr10 | |
| 36 | mabshs fr10,fr11 | |
| 37 | test_fr_limmed 0x7fff,0x7fff,fr11 | |
| 38 | test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set | |
| 39 | test_spr_bits 2,1,1,msr0 ; msr0.ovf set | |
| 40 | test_spr_bits 1,0,1,msr0 ; msr0.aovf set | |
| 41 | test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set | |
| 42 | ||
| 43 | set_spr_immed 0,msr0 | |
| 44 | set_fr_iimmed 0x8000,0x7fff,fr10 | |
| 45 | mabshs fr10,fr11 | |
| 46 | test_fr_limmed 0x7fff,0x7fff,fr11 | |
| 47 | test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set | |
| 48 | test_spr_bits 2,1,1,msr0 ; msr0.ovf set | |
| 49 | test_spr_bits 1,0,1,msr0 ; msr0.aovf set | |
| 50 | test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set | |
| 51 | ||
| 52 | set_spr_immed 0,msr0 | |
| 53 | set_spr_immed 0,msr1 | |
| 54 | set_fr_iimmed 0x7fff,0x8000,fr10 | |
| 55 | set_fr_iimmed 0x8000,0x7fff,fr11 | |
| 56 | mabshs.p fr10,fr12 | |
| 57 | mabshs fr11,fr13 | |
| 58 | test_fr_limmed 0x7fff,0x7fff,fr12 | |
| 59 | test_fr_limmed 0x7fff,0x7fff,fr13 | |
| 60 | test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set | |
| 61 | test_spr_bits 0x3c,2,0x8,msr1 ; msr1.sie is set | |
| 62 | test_spr_bits 2,1,1,msr0 ; msr0.ovf set | |
| 63 | test_spr_bits 2,1,1,msr1 ; msr1.ovf set | |
| 64 | test_spr_bits 1,0,1,msr0 ; msr0.aovf set | |
| 65 | test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set | |
| 66 | ||
| 67 | pass |