Commit | Line | Data |
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4a306116 DB |
1 | # frv testcase for mqxmachs $GRi,$GRj,$ACCk |
2 | # mach: fr400 | |
3 | ||
4 | .include "testutils.inc" | |
5 | ||
6 | start | |
7 | ||
8 | .global mqxmachs | |
9 | mqxmachs: | |
10 | ; Positive operands | |
11 | set_fr_iimmed 2,3,fr8 ; multiply small numbers | |
12 | set_fr_iimmed 3,2,fr10 | |
13 | set_fr_iimmed 0,1,fr9 ; multiply by 0 | |
14 | set_fr_iimmed 2,0,fr11 | |
15 | mqxmachs fr8,fr10,acc0 | |
16 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
17 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
18 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
19 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
20 | test_accg_immed 0,accg0 | |
21 | test_acc_immed 0,acc0 | |
22 | test_accg_immed 0,accg1 | |
23 | test_acc_immed 0,acc1 | |
24 | test_accg_immed 0,accg2 | |
25 | test_acc_immed 6,acc2 | |
26 | test_accg_immed 0,accg3 | |
27 | test_acc_immed 6,acc3 | |
28 | ||
29 | set_fr_iimmed 2,1,fr8 ; multiply by 1 | |
30 | set_fr_iimmed 1,2,fr10 | |
31 | set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result | |
32 | set_fr_iimmed 2,0x3fff,fr11 | |
33 | mqxmachs fr8,fr10,acc0 | |
34 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
35 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
36 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
37 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
38 | test_accg_immed 0,accg2 | |
39 | test_acc_immed 8,acc2 | |
40 | test_accg_immed 0,accg3 | |
41 | test_acc_immed 8,acc3 | |
42 | test_accg_immed 0,accg0 | |
43 | test_acc_limmed 0,0x7ffe,acc0 | |
44 | test_accg_immed 0,accg1 | |
45 | test_acc_limmed 0,0x7ffe,acc1 | |
46 | ||
47 | set_fr_iimmed 0x4000,2,fr8 ; 16 bit result | |
48 | set_fr_iimmed 2,0x4000,fr10 | |
49 | set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result | |
50 | set_fr_iimmed 0x7fff,0x7fff,fr11 | |
51 | mqxmachs fr8,fr10,acc0 | |
52 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
53 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
54 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
55 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
56 | test_accg_immed 0,accg2 | |
57 | test_acc_limmed 0x0000,0x8008,acc2 | |
58 | test_accg_immed 0,accg3 | |
59 | test_acc_limmed 0x0000,0x8008,acc3 | |
60 | test_accg_immed 0,accg0 | |
61 | test_acc_limmed 0x3fff,0x7fff,acc0 | |
62 | test_accg_immed 0,accg1 | |
63 | test_acc_limmed 0x3fff,0x7fff,acc1 | |
64 | ||
65 | ; Mixed operands | |
66 | set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers | |
67 | set_fr_iimmed 0xfffd,2,fr10 | |
68 | set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 | |
69 | set_fr_iimmed 1,0xfffe,fr11 | |
70 | mqxmachs fr8,fr10,acc0 | |
71 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
72 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
73 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
74 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
75 | test_accg_immed 0,accg2 | |
76 | test_acc_limmed 0x0000,0x8002,acc2 | |
77 | test_accg_immed 0,accg3 | |
78 | test_acc_limmed 0x0000,0x8002,acc3 | |
79 | test_accg_immed 0,accg0 | |
80 | test_acc_limmed 0x3fff,0x7ffd,acc0 | |
81 | test_accg_immed 0,accg1 | |
82 | test_acc_limmed 0x3fff,0x7ffd,acc1 | |
83 | ||
84 | set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 | |
85 | set_fr_iimmed 0,0xfffe,fr10 | |
86 | set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result | |
87 | set_fr_iimmed 0xfffe,0x2001,fr11 | |
88 | mqxmachs fr8,fr10,acc0 | |
89 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
90 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
91 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
92 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
93 | test_accg_immed 0,accg2 | |
94 | test_acc_limmed 0x0000,0x8002,acc2 | |
95 | test_accg_immed 0,accg3 | |
96 | test_acc_limmed 0x0000,0x8002,acc3 | |
97 | test_accg_immed 0,accg0 | |
98 | test_acc_limmed 0x3fff,0x3ffb,acc0 | |
99 | test_accg_immed 0,accg1 | |
100 | test_acc_limmed 0x3fff,0x3ffb,acc1 | |
101 | ||
102 | set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result | |
103 | set_fr_iimmed 0xfffe,0x4000,fr10 | |
104 | set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result | |
105 | set_fr_iimmed 0x8000,0x7fff,fr11 | |
106 | mqxmachs fr8,fr10,acc0 | |
107 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
108 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
109 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
110 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
111 | test_accg_immed 0,accg2 | |
112 | test_acc_limmed 0x0000,0x0002,acc2 | |
113 | test_accg_immed 0,accg3 | |
114 | test_acc_limmed 0x0000,0x0002,acc3 | |
115 | test_accg_immed 0xff,accg0 | |
116 | test_acc_limmed 0xffff,0xbffb,acc0 | |
117 | test_accg_immed 0xff,accg1 | |
118 | test_acc_limmed 0xffff,0xbffb,acc1 | |
119 | ||
120 | ; Negative operands | |
121 | set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers | |
122 | set_fr_iimmed 0xfffd,0xfffe,fr10 | |
123 | set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 | |
124 | set_fr_iimmed 0xfffe,0xffff,fr11 | |
125 | mqxmachs fr8,fr10,acc0 | |
126 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
127 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
128 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
129 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
130 | test_accg_immed 0,accg2 | |
131 | test_acc_limmed 0x0000,0x0008,acc2 | |
132 | test_accg_immed 0,accg3 | |
133 | test_acc_limmed 0x0000,0x0008,acc3 | |
134 | test_accg_immed 0xff,accg0 | |
135 | test_acc_limmed 0xffff,0xbffd,acc0 | |
136 | test_accg_immed 0xff,accg1 | |
137 | test_acc_limmed 0xffff,0xbffd,acc1 | |
138 | ||
139 | set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result | |
140 | set_fr_iimmed 0x8001,0x8001,fr10 | |
141 | set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result | |
142 | set_fr_iimmed 0x8000,0x8000,fr11 | |
143 | mqxmachs fr8,fr10,acc0 | |
144 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
145 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
146 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
147 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
148 | test_accg_immed 0,accg2 | |
149 | test_acc_immed 0x3fff0009,acc2 | |
150 | test_accg_immed 0,accg3 | |
151 | test_acc_immed 0x3fff0009,acc3 | |
152 | test_accg_immed 0,accg0 | |
153 | test_acc_immed 0x3fffbffd,acc0 | |
154 | test_accg_immed 0,accg1 | |
155 | test_acc_immed 0x3fffbffd,acc1 | |
156 | ||
157 | set_accg_immed 0x7f,accg2 ; saturation | |
158 | set_acc_immed 0xffffffff,acc2 | |
159 | set_accg_immed 0x7f,accg3 | |
160 | set_acc_immed 0xffffffff,acc3 | |
161 | set_accg_immed 0x7f,accg0 ; saturation | |
162 | set_acc_immed 0xffffffff,acc0 | |
163 | set_accg_immed 0x7f,accg1 | |
164 | set_acc_immed 0xffffffff,acc1 | |
165 | set_fr_iimmed 1,1,fr8 | |
166 | set_fr_iimmed 1,1,fr10 | |
167 | set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation | |
168 | set_fr_iimmed 0x7fff,0x7fff,fr11 | |
169 | mqxmachs fr8,fr10,acc0 | |
170 | test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set | |
171 | test_spr_bits 2,1,1,msr0 ; msr0.ovf is set | |
172 | test_spr_bits 1,0,1,msr0 ; msr0.aovf is set | |
173 | test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set | |
174 | test_accg_immed 0x7f,accg2 | |
175 | test_acc_limmed 0xffff,0xffff,acc2 | |
176 | test_accg_immed 0x7f,accg3 | |
177 | test_acc_limmed 0xffff,0xffff,acc3 | |
178 | test_accg_immed 0x7f,accg0 | |
179 | test_acc_limmed 0xffff,0xffff,acc0 | |
180 | test_accg_immed 0x7f,accg1 | |
181 | test_acc_limmed 0xffff,0xffff,acc1 | |
182 | ||
183 | set_accg_immed 0x80,accg2 ; saturation | |
184 | set_acc_immed 0,acc2 | |
185 | set_accg_immed 0x80,accg3 | |
186 | set_acc_immed 0,acc3 | |
187 | set_accg_immed 0x80,accg0 ; saturation | |
188 | set_acc_immed 0,acc0 | |
189 | set_accg_immed 0x80,accg1 | |
190 | set_acc_immed 0,acc1 | |
191 | set_fr_iimmed 0xffff,0,fr8 | |
192 | set_fr_iimmed 1,0xffff,fr10 | |
193 | set_fr_iimmed 0x0000,0x8000,fr9 ; saturation | |
194 | set_fr_iimmed 0x7fff,0x7fff,fr11 | |
195 | mqxmachs fr8,fr10,acc0 | |
196 | test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set | |
197 | test_spr_bits 2,1,1,msr0 ; msr0.ovf is set | |
198 | test_spr_bits 1,0,1,msr0 ; msr0.aovf is set | |
199 | test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set | |
200 | test_accg_immed 0x80,accg2 | |
201 | test_acc_immed 0,acc2 | |
202 | test_accg_immed 0x80,accg3 | |
203 | test_acc_immed 0,acc3 | |
204 | test_accg_immed 0x80,accg0 | |
205 | test_acc_immed 0,acc0 | |
206 | test_accg_immed 0x80,accg1 | |
207 | test_acc_immed 0,acc1 | |
208 | ||
209 | pass | |
210 | ||
211 |