Commit | Line | Data |
---|---|---|
4a306116 DB |
1 | # frv testcase for tnv $ICCi_2,$GRi,$GRj |
2 | # mach: all | |
3 | ||
4 | .include "testutils.inc" | |
5 | ||
6 | start | |
7 | ||
8 | .global tnv | |
9 | tnv: | |
10 | and_spr_immed -4081,tbr ; clear tbr.tt | |
11 | set_gr_spr tbr,gr7 | |
12 | inc_gr_immed 2112,gr7 ; address of exception handler | |
13 | set_bctrlr_0_0 gr7 ; bctrlr 0,0 | |
14 | ||
15 | set_spr_immed 128,lcr | |
16 | set_gr_immed 0,gr7 | |
17 | set_gr_immed 4,gr8 | |
18 | ||
19 | set_psr_et 1 | |
20 | set_spr_addr ok0,lr | |
21 | set_icc 0x0 0 | |
22 | tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 | |
23 | fail | |
24 | ok0: | |
25 | set_psr_et 1 | |
26 | set_spr_addr ok1,lr | |
27 | set_icc 0x1 0 | |
28 | tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 | |
29 | fail | |
30 | ok1: | |
31 | set_spr_addr bad,lr | |
32 | set_icc 0x2 0 | |
33 | tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 | |
34 | ||
35 | set_spr_addr bad,lr | |
36 | set_icc 0x3 0 | |
37 | tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 | |
38 | ||
39 | set_psr_et 1 | |
40 | set_spr_addr ok4,lr | |
41 | set_icc 0x4 0 | |
42 | tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 | |
43 | fail | |
44 | ok4: | |
45 | set_psr_et 1 | |
46 | set_spr_addr ok5,lr | |
47 | set_icc 0x5 0 | |
48 | tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 | |
49 | fail | |
50 | ok5: | |
51 | set_spr_addr bad,lr | |
52 | set_icc 0x6 0 | |
53 | tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 | |
54 | ||
55 | set_spr_addr bad,lr | |
56 | set_icc 0x7 0 | |
57 | tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 | |
58 | ||
59 | set_psr_et 1 | |
60 | set_spr_addr ok8,lr | |
61 | set_icc 0x8 0 | |
62 | tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 | |
63 | fail | |
64 | ok8: | |
65 | set_psr_et 1 | |
66 | set_spr_addr ok9,lr | |
67 | set_icc 0x9 0 | |
68 | tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 | |
69 | fail | |
70 | ok9: | |
71 | set_spr_addr bad,lr | |
72 | set_icc 0xa 0 | |
73 | tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 | |
74 | ||
75 | set_spr_addr bad,lr | |
76 | set_icc 0xb 0 | |
77 | tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 | |
78 | ||
79 | set_psr_et 1 | |
80 | set_spr_addr okc,lr | |
81 | set_icc 0xc 0 | |
82 | tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 | |
83 | fail | |
84 | okc: | |
85 | set_psr_et 1 | |
86 | set_spr_addr okd,lr | |
87 | set_icc 0xd 0 | |
88 | tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 | |
89 | fail | |
90 | okd: | |
91 | set_spr_addr bad,lr | |
92 | set_icc 0xe 0 | |
93 | tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 | |
94 | ||
95 | set_spr_addr bad,lr | |
96 | set_icc 0xf 0 | |
97 | tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 | |
98 | ||
99 | pass | |
100 | bad: | |
101 | fail |