Commit | Line | Data |
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32ebdc4c MS |
1 | # Hitachi H8 testcase 'and.w' |
2 | # mach(): h8300h h8300s h8sx | |
3 | # as(h8300): --defsym sim_cpu=0 | |
4 | # as(h8300h): --defsym sim_cpu=1 | |
5 | # as(h8300s): --defsym sim_cpu=2 | |
6 | # as(h8sx): --defsym sim_cpu=3 | |
7 | # ld(h8300h): -m h8300helf | |
8 | # ld(h8300s): -m h8300self | |
9 | # ld(h8sx): -m h8300sxelf | |
10 | ||
11 | .include "testutils.inc" | |
12 | ||
13 | start | |
14 | ||
15 | .if (sim_cpu) ; non-zero means h8300h, s, or sx | |
16 | and_w_imm16: | |
17 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
18 | ;; fixme set ccr | |
19 | ||
20 | ;; and.w #xx:16,Rd | |
21 | and.w #0xaaaa, r0 ; Immediate 16-bit operand | |
22 | ||
23 | ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 | |
24 | test_h_gr16 0xa0a0 r0 ; and result: a5a5 & aaaa | |
25 | .if (sim_cpu) ; non-zero means h8300h, s, or sx | |
26 | test_h_gr32 0xa5a5a0a0 er0 ; and result: a5a5 & aaaa | |
27 | .endif | |
28 | test_gr_a5a5 1 ; Make sure other general regs not disturbed | |
29 | test_gr_a5a5 2 | |
30 | test_gr_a5a5 3 | |
31 | test_gr_a5a5 4 | |
32 | test_gr_a5a5 5 | |
33 | test_gr_a5a5 6 | |
34 | test_gr_a5a5 7 | |
35 | .endif | |
36 | ||
37 | and_w_reg: | |
38 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
39 | ;; fixme set ccr | |
40 | ||
41 | ;; and.w Rs,Rd | |
42 | mov.w #0xaaaa, r1 | |
43 | and.w r1, r0 ; Register operand | |
44 | ||
45 | ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 | |
46 | test_h_gr16 0xa0a0 r0 ; and result: a5a5 & aaaa | |
47 | test_h_gr16 0xaaaa r1 ; Make sure r1 is unchanged | |
48 | .if (sim_cpu) ; non-zero means h8300h, s, or sx | |
49 | test_h_gr32 0xa5a5a0a0 er0 ; and result: a5a5 & aaaa | |
50 | test_h_gr32 0xa5a5aaaa er1 ; Make sure er1 is unchanged | |
51 | .endif | |
52 | test_gr_a5a5 2 ; Make sure other general regs not disturbed | |
53 | test_gr_a5a5 3 | |
54 | test_gr_a5a5 4 | |
55 | test_gr_a5a5 5 | |
56 | test_gr_a5a5 6 | |
57 | test_gr_a5a5 7 | |
58 | ||
59 | pass | |
60 | ||
61 | exit 0 |