Commit | Line | Data |
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5fe8b0df MS |
1 | # Hitachi H8 testcase 'dec.b, dec.w, dec.l' |
2 | # mach(): all | |
3 | # as(h8300): --defsym sim_cpu=0 | |
4 | # as(h8300h): --defsym sim_cpu=1 | |
5 | # as(h8300s): --defsym sim_cpu=2 | |
6 | # as(h8sx): --defsym sim_cpu=3 | |
7 | # ld(h8300h): -m h8300helf | |
8 | # ld(h8300s): -m h8300self | |
9 | # ld(h8sx): -m h8300sxelf | |
10 | ||
11 | .include "testutils.inc" | |
12 | ||
13 | start | |
14 | ||
15 | dec_b: | |
16 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
17 | ;; fixme set ccr | |
18 | ||
19 | ;; dec.b Rd | |
20 | dec.b r0h ; Decrement 8-bit reg by one | |
21 | ||
22 | ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 | |
23 | test_h_gr16 0xa4a5 r0 ; dec result: a4|a5 | |
24 | .if (sim_cpu) ; non-zero means h8300h, s, or sx | |
25 | test_h_gr32 0xa5a5a4a5 er0 ; dec result: a5|a5|a4|a5 | |
26 | .endif | |
27 | test_gr_a5a5 1 ; Make sure other general regs not disturbed | |
28 | test_gr_a5a5 2 | |
29 | test_gr_a5a5 3 | |
30 | test_gr_a5a5 4 | |
31 | test_gr_a5a5 5 | |
32 | test_gr_a5a5 6 | |
33 | test_gr_a5a5 7 | |
34 | ||
35 | .if (sim_cpu) ; non-zero means h8300h, s, or sx | |
36 | dec_w_1: | |
37 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
38 | ;; fixme set ccr | |
39 | ||
40 | ;; dec.w #1, Rd | |
41 | dec.w #1, r0 ; Decrement 16-bit reg by one | |
42 | ||
43 | ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 | |
44 | test_h_gr16 0xa5a4 r0 ; dec result: a5|a4 | |
45 | ||
46 | test_h_gr32 0xa5a5a5a4 er0 ; dec result: a5|a5|a5|a4 | |
47 | ||
48 | test_gr_a5a5 1 ; Make sure other general regs not disturbed | |
49 | test_gr_a5a5 2 | |
50 | test_gr_a5a5 3 | |
51 | test_gr_a5a5 4 | |
52 | test_gr_a5a5 5 | |
53 | test_gr_a5a5 6 | |
54 | test_gr_a5a5 7 | |
55 | ||
56 | dec_w_2: | |
57 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
58 | ;; fixme set ccr | |
59 | ||
60 | ;; dec.w #2, Rd | |
61 | dec.w #2, r0 ; Decrement 16-bit reg by two | |
62 | ||
63 | ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 | |
64 | test_h_gr16 0xa5a3 r0 ; dec result: a5|a3 | |
65 | ||
66 | test_h_gr32 0xa5a5a5a3 er0 ; dec result: a5|a5|a5|a3 | |
67 | ||
68 | test_gr_a5a5 1 ; Make sure other general regs not disturbed | |
69 | test_gr_a5a5 2 | |
70 | test_gr_a5a5 3 | |
71 | test_gr_a5a5 4 | |
72 | test_gr_a5a5 5 | |
73 | test_gr_a5a5 6 | |
74 | test_gr_a5a5 7 | |
75 | ||
76 | dec_l_1: | |
77 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
78 | ;; fixme set ccr | |
79 | ||
80 | ;; dec.l #1, eRd | |
81 | dec.l #1, er0 ; Decrement 32-bit reg by one | |
82 | ||
83 | ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 | |
84 | ||
85 | test_h_gr32 0xa5a5a5a4 er0 ; dec result: a5|a5|a5|a4 | |
86 | ||
87 | test_gr_a5a5 1 ; Make sure other general regs not disturbed | |
88 | test_gr_a5a5 2 | |
89 | test_gr_a5a5 3 | |
90 | test_gr_a5a5 4 | |
91 | test_gr_a5a5 5 | |
92 | test_gr_a5a5 6 | |
93 | test_gr_a5a5 7 | |
94 | ||
95 | dec_l_2: | |
96 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
97 | ;; fixme set ccr | |
98 | ||
99 | ;; dec.l #2, eRd | |
100 | dec.l #2, er0 ; Decrement 32-bit reg by two | |
101 | ||
102 | ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 | |
103 | ||
104 | test_h_gr32 0xa5a5a5a3 er0 ; dec result: a5|a5|a5|a3 | |
105 | ||
106 | test_gr_a5a5 1 ; Make sure other general regs not disturbed | |
107 | test_gr_a5a5 2 | |
108 | test_gr_a5a5 3 | |
109 | test_gr_a5a5 4 | |
110 | test_gr_a5a5 5 | |
111 | test_gr_a5a5 6 | |
112 | test_gr_a5a5 7 | |
113 | .endif | |
114 | ||
115 | pass | |
116 | ||
117 | exit 0 |