Commit | Line | Data |
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5fe8b0df MS |
1 | # Hitachi H8 testcase 'shal' |
2 | # mach(): all | |
3 | # as(h8300): --defsym sim_cpu=0 | |
4 | # as(h8300h): --defsym sim_cpu=1 | |
5 | # as(h8300s): --defsym sim_cpu=2 | |
6 | # as(h8sx): --defsym sim_cpu=3 | |
7 | # ld(h8300h): -m h8300helf | |
8 | # ld(h8300s): -m h8300self | |
9 | # ld(h8sx): -m h8300sxelf | |
10 | ||
11 | .include "testutils.inc" | |
12 | ||
13 | start | |
14 | ||
15 | .data | |
16 | byte_dest: .byte 0xa5 | |
17 | .align 2 | |
18 | word_dest: .word 0xa5a5 | |
19 | .align 4 | |
20 | long_dest: .long 0xa5a5a5a5 | |
21 | ||
22 | .text | |
23 | ||
24 | shal_b_reg8_1: | |
25 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
26 | set_ccr_zero | |
27 | ||
28 | shal.b r0l ; shift left arithmetic by one | |
29 | ;;; .word 0x1088 | |
30 | ||
31 | test_carry_set ; H=0 N=0 Z=0 V=0 C=1 | |
32 | test_zero_clear | |
33 | ; test_ovf_clear ; FIXME | |
34 | test_neg_clear | |
35 | test_h_gr16 0xa54a r0 ; 1010 0101 -> 0100 1010 | |
36 | .if (sim_cpu) | |
37 | test_h_gr32 0xa5a5a54a er0 | |
38 | .endif | |
39 | test_gr_a5a5 1 ; Make sure other general regs not disturbed | |
40 | test_gr_a5a5 2 | |
41 | test_gr_a5a5 3 | |
42 | test_gr_a5a5 4 | |
43 | test_gr_a5a5 5 | |
44 | test_gr_a5a5 6 | |
45 | test_gr_a5a5 7 | |
46 | ||
47 | shal_b_reg8_2: | |
48 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
49 | set_ccr_zero | |
50 | ||
51 | shal.b #2, r0l ; shift left arithmetic by two | |
52 | ;;; .word 0x10c8 | |
53 | ||
54 | test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 | |
55 | test_zero_clear | |
56 | ; test_ovf_clear ; FIXME | |
57 | test_neg_set | |
58 | ||
59 | test_h_gr16 0xa594 r0 ; 1010 0101 -> 1001 0100 | |
60 | .if (sim_cpu) | |
61 | test_h_gr32 0xa5a5a594 er0 | |
62 | .endif | |
63 | test_gr_a5a5 1 ; Make sure other general regs not disturbed | |
64 | test_gr_a5a5 2 | |
65 | test_gr_a5a5 3 | |
66 | test_gr_a5a5 4 | |
67 | test_gr_a5a5 5 | |
68 | test_gr_a5a5 6 | |
69 | test_gr_a5a5 7 | |
70 | ||
71 | .if (sim_cpu) ; Not available in h8300 mode | |
72 | shal_w_reg16_1: | |
73 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
74 | set_ccr_zero | |
75 | ||
76 | shal.w r0 ; shift left arithmetic by one | |
77 | ;;; .word 0x1090 | |
78 | ||
79 | test_carry_set ; H=0 N=0 Z=0 V=0 C=1 | |
80 | test_zero_clear | |
81 | ; test_ovf_clear ; FIXME | |
82 | test_neg_clear | |
83 | test_h_gr16 0x4b4a r0 ; 1010 0101 1010 0101 -> 0100 1011 0100 1010 | |
84 | test_h_gr32 0xa5a54b4a er0 | |
85 | ||
86 | test_gr_a5a5 1 ; Make sure other general regs not disturbed | |
87 | test_gr_a5a5 2 | |
88 | test_gr_a5a5 3 | |
89 | test_gr_a5a5 4 | |
90 | test_gr_a5a5 5 | |
91 | test_gr_a5a5 6 | |
92 | test_gr_a5a5 7 | |
93 | ||
94 | shal_w_reg16_2: | |
95 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
96 | set_ccr_zero | |
97 | ||
98 | shal.w #2, r0 ; shift left arithmetic by two | |
99 | ;;; .word 0x10d0 | |
100 | ||
101 | test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 | |
102 | test_zero_clear | |
103 | ; test_ovf_clear ; FIXME | |
104 | test_neg_set | |
105 | test_h_gr16 0x9694 r0 ; 1010 0101 1010 0101 -> 1001 0110 1001 0100 | |
106 | test_h_gr32 0xa5a59694 er0 | |
107 | ||
108 | test_gr_a5a5 1 ; Make sure other general regs not disturbed | |
109 | test_gr_a5a5 2 | |
110 | test_gr_a5a5 3 | |
111 | test_gr_a5a5 4 | |
112 | test_gr_a5a5 5 | |
113 | test_gr_a5a5 6 | |
114 | test_gr_a5a5 7 | |
115 | ||
116 | shal_l_reg32_1: | |
117 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
118 | set_ccr_zero | |
119 | ||
120 | shal.l er0 ; shift left arithmetic by one | |
121 | ;;; .word 10b0 | |
122 | ||
123 | test_carry_set ; H=0 N=0 Z=0 V=0 C=1 | |
124 | test_zero_clear | |
125 | ; test_ovf_clear ; FIXME | |
126 | test_neg_clear | |
127 | ; 1010 0101 1010 0101 1010 0101 1010 0101 | |
128 | ; -> 0100 1011 0100 1011 0100 1011 0100 1010 | |
129 | test_h_gr32 0x4b4b4b4a er0 | |
130 | ||
131 | test_gr_a5a5 1 ; Make sure other general regs not disturbed | |
132 | test_gr_a5a5 2 | |
133 | test_gr_a5a5 3 | |
134 | test_gr_a5a5 4 | |
135 | test_gr_a5a5 5 | |
136 | test_gr_a5a5 6 | |
137 | test_gr_a5a5 7 | |
138 | ||
139 | shal_l_reg32_2: | |
140 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
141 | set_ccr_zero | |
142 | ||
143 | shal.l #2, er0 ; shift left arithmetic by two | |
144 | ;;; .word 0x10f0 | |
145 | ||
146 | test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 | |
147 | test_zero_clear | |
148 | ; test_ovf_clear ; FIXME | |
149 | test_neg_set | |
150 | ; 1010 0101 1010 0101 1010 0101 1010 0101 | |
151 | ; -> 1001 0110 1001 0110 1001 0110 1001 0100 | |
152 | test_h_gr32 0x96969694 er0 | |
153 | ||
154 | test_gr_a5a5 1 ; Make sure other general regs not disturbed | |
155 | test_gr_a5a5 2 | |
156 | test_gr_a5a5 3 | |
157 | test_gr_a5a5 4 | |
158 | test_gr_a5a5 5 | |
159 | test_gr_a5a5 6 | |
160 | test_gr_a5a5 7 | |
161 | ||
162 | .endif | |
163 | ||
164 | pass | |
165 | ||
166 | exit 0 | |
167 |