projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| d5e2c74e AC |
1 | Tue Apr 29 10:58:48 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 2 | ||
| 3 | * alu.h (MEM, STORE): Force addresses to be correctly aligned. | |
| 4 | ||
| 5 | * insns (do_jsr): Fix. | |
| 6 | (do_st, do_ld): Handle 64bit transfers. | |
| 7 | (do_trap): Match libgloss. | |
| 8 | (rdcr): Implement nop - Dest == r0 - variant. | |
| 9 | ||
| 10 | * sim-calls.c (sim_create_inferior): Initialize SP. | |
| 11 | ||
| 12 | * Makefile.in (ENGINE_H): Everything now depends on sim-options.h. | |
| 13 | (support.o): Depends on ENGINE_H. | |
| 14 | ||
| 15 | * cpu.h: Four accumulators. | |
| 16 | ||
| 17 | * Makefile.in (tmp-igen): Include line number information in | |
| 18 | generated files. | |
| 19 | ||
| 20 | * insns (dld, dst): Fill in. | |
| 21 | ||
| 22 | Mon Apr 28 13:02:26 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 23 | ||
| 24 | * insns (vld): Fix instruction format wrong. | |
| 25 | ||
| abe293a0 AC |
26 | Thu Apr 24 16:43:09 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 27 | ||
| 28 | * dc: Add additional rules so that minor opcode files are | |
| 29 | detected. | |
| 30 | * insns: Enable more instructions. | |
| 31 | ||
| 32 | * sim-calls.c (sim_fetch_register,sim_store_register, sim_write): | |
| 33 | Implement. | |
| 34 | ||
| dd442a44 DE |
35 | Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com> |
| 36 | ||
| 37 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 38 | * Makefile.in (SIM_OBJS): Add sim-module.o, sim-profile.o. | |
| 39 | * sim-calls.c (sim_open): Call sim_module_uninstall if argument | |
| 40 | parsing fails. Call sim_post_argv_init. | |
| 41 | (sim_close): Call sim_module_uninstall. | |
| 42 | ||
| 480e740c AC |
43 | Wed Apr 23 20:05:33 1997 Andrew Cagney <cagney@b1.cygnus.com> |
| 44 | ||
| 45 | * insns (and, bbo, bcnd, bsr, dcache, jsr, or, xor, nor): Enable. | |
| 46 | * ic: Add fields for enabled instructions. | |
| 47 |