Commit | Line | Data |
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d5e2c74e | 1 | /* TIc80 Simulator. |
241b4624 | 2 | Copyright (C) 1997, 1998 Free Software Foundation, Inc. |
d5e2c74e AC |
3 | Contributed by Cygnus Support. |
4 | ||
5 | This file is part of GDB, the GNU debugger. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License along | |
18 | with this program; if not, write to the Free Software Foundation, Inc., | |
19 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
20 | ||
21 | ||
22 | ||
381f42ef AC |
23 | /* TI C80 control registers */ |
24 | ||
25 | typedef enum { | |
26 | EPC_CR, | |
27 | EIP_CR, | |
28 | CONFIG_CR, | |
29 | INTPEN_CR, | |
30 | IE_CR, | |
31 | FPST_CR, | |
32 | PPERROR_CR, | |
33 | PKTREQ_CR, | |
34 | TCOUNT_CR, | |
35 | TSCALE_CR, | |
36 | FLTOP_CR, | |
37 | FLTADR_CR, | |
38 | FLTTAG_CR, | |
39 | FLTDLT_CR, | |
40 | FLTDTH_CR, | |
41 | FLT005_CR, | |
42 | FLT006_CR, | |
43 | FLT007_CR, | |
44 | FLT008_CR, | |
45 | FLT009_CR, | |
46 | FLT010_CR, | |
47 | FLT011_CR, | |
48 | FLT012_CR, | |
49 | FLT013_CR, | |
50 | FLT014_CR, | |
51 | FLT015_CR, | |
52 | SYSSTK_CR, | |
53 | SYSTMP_CR, | |
54 | MPC_CR, | |
55 | MIP_CR, | |
56 | ECOMCNTL_CR, | |
57 | ANASTAT_CR, | |
58 | BRK1_CR, | |
59 | BRK2_CR, | |
60 | ITAG0_CR, | |
61 | ITAG1_CR, | |
62 | ITAG2_CR, | |
63 | ITAG3_CR, | |
64 | ITAG4_CR, | |
65 | ITAG5_CR, | |
66 | ITAG6_CR, | |
67 | ITAG7_CR, | |
68 | ITAG8_CR, | |
69 | ITAG9_CR, | |
70 | ITAG10_CR, | |
71 | ITAG11_CR, | |
72 | ITAG12_CR, | |
73 | ITAG13_CR, | |
74 | ITAG14_CR, | |
75 | ITAG15_CR, | |
76 | ILRU_CR, | |
77 | DTAG0_CR, | |
78 | DTAG1_CR, | |
79 | DTAG2_CR, | |
80 | DTAG3_CR, | |
81 | DTAG4_CR, | |
82 | DTAG5_CR, | |
83 | DTAG6_CR, | |
84 | DTAG7_CR, | |
85 | DTAG8_CR, | |
86 | DTAG9_CR, | |
87 | DTAG10_CR, | |
88 | DTAG11_CR, | |
89 | DTAG12_CR, | |
90 | DTAG13_CR, | |
91 | DTAG14_CR, | |
92 | DTAG15_CR, | |
93 | DLRU_CR, | |
94 | IN0P_CR, | |
95 | IN1P_CR, | |
96 | OUTP_CR, | |
97 | SCRATCH_CR, | |
98 | nr_tic80_control_regs, | |
99 | } tic80_control_regs; | |
100 | ||
101 | /* extern int tic80_cr2index (tic80_control_regs reg); */ | |
102 | ||
103 | /* Map an instruction CR index onto the corresponding internal cr enum | |
104 | or SCRATCH_CR if the index is invalid */ | |
105 | ||
106 | extern tic80_control_regs tic80_index2cr (int index); | |
107 | ||
108 | ||
109 | /* TIc80 interrupt register bits */ | |
110 | ||
111 | enum { | |
112 | IE_CR_PE = BIT32(31), | |
113 | IE_CR_X4 = BIT32(30), | |
114 | IE_CR_X3 = BIT32(29), | |
115 | IE_CR_BP = BIT32(28), | |
116 | IE_CR_PB = BIT32(27), | |
117 | IE_CR_PC = BIT32(26), | |
118 | IE_CR_MI = BIT32(25), | |
119 | /**/ | |
120 | IE_CR_P3 = BIT32(19), | |
121 | IE_CR_P2 = BIT32(18), | |
122 | IE_CR_P1 = BIT32(17), | |
123 | IE_CR_P0 = BIT32(16), | |
124 | IE_CR_IO = BIT32(15), | |
125 | IE_CR_MF = BIT32(14), | |
126 | /**/ | |
127 | IE_CR_X2 = BIT32(12), | |
128 | IE_CR_X1 = BIT32(11), | |
129 | IE_CR_TI = BIT32(10), | |
130 | IE_CR_F1 = BIT32(9), | |
131 | IE_CR_F0 = BIT32(8), | |
132 | IE_CR_FX = BIT32(7), | |
133 | IE_CR_FU = BIT32(6), | |
134 | IE_CR_FO = BIT32(5), | |
135 | /**/ | |
136 | IE_CR_FZ = BIT32(3), | |
137 | IE_CR_FI = BIT32(2), | |
138 | /**/ | |
139 | IE_CR_IE = BIT32(0), | |
140 | }; | |
141 | ||
142 | ||
143 | ||
144 | ||
d9b75947 | 145 | struct _sim_cpu { |
abe293a0 | 146 | unsigned32 reg[32]; |
d5e2c74e | 147 | unsigned64 acc[4]; |
381f42ef AC |
148 | unsigned32 cr[nr_tic80_control_regs]; |
149 | int is_user_mode; /* hidden mode latch */ | |
d9b75947 | 150 | sim_cia cia; |
abe293a0 | 151 | sim_cpu_base base; |
d9b75947 | 152 | }; |
15c16493 | 153 | |
9ec6741b AC |
154 | #define CIA_GET(CPU) ((CPU)->cia) |
155 | #define CIA_SET(CPU,VAL) ((CPU)->cia = (VAL)) | |
70c8abdb | 156 | |
15c16493 | 157 | #define GPR(N) ((CPU)->reg[N]) |
37a684b8 | 158 | #define GPR_SET(N, VAL) ((CPU)->reg[N] = (VAL)) |
abe293a0 | 159 | #define ACC(N) ((CPU)->acc[N]) |
381f42ef AC |
160 | #define CR(N) ((CPU)->cr[tic80_index2cr ((N))]) |
161 | ||
162 | ||
3971886a | 163 | |
7b167b09 MM |
164 | #if defined(WITH_TRACE) |
165 | extern char *tic80_trace_alu3 PARAMS ((int, unsigned32, unsigned32, unsigned32)); | |
241b4624 | 166 | extern char *tic80_trace_cmp PARAMS ((int, unsigned32, unsigned32, unsigned32)); |
7b167b09 | 167 | extern char *tic80_trace_alu2 PARAMS ((int, unsigned32, unsigned32)); |
450be234 | 168 | extern char *tic80_trace_shift PARAMS ((int, unsigned32, unsigned32, int, int, int, int, int)); |
8114673a MM |
169 | extern void tic80_trace_fpu3 PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int, sim_fpu *, sim_fpu *, sim_fpu *)); |
170 | extern void tic80_trace_fpu2 PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int, sim_fpu *, sim_fpu *)); | |
171 | extern void tic80_trace_fpu1 PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int, sim_fpu *)); | |
172 | extern void tic80_trace_fpu2i PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int, unsigned32, sim_fpu *, sim_fpu *)); | |
173 | extern void tic80_trace_fpu2cmp PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int, unsigned32, sim_fpu *, sim_fpu *)); | |
7b167b09 MM |
174 | extern char *tic80_trace_nop PARAMS ((int)); |
175 | extern char *tic80_trace_sink1 PARAMS ((int, unsigned32)); | |
176 | extern char *tic80_trace_sink2 PARAMS ((int, unsigned32, unsigned32)); | |
381f42ef | 177 | extern char *tic80_trace_sink3 PARAMS ((int, unsigned32, unsigned32, unsigned32)); |
99022131 | 178 | extern char *tic80_trace_cond_br PARAMS ((int, int, unsigned32, unsigned32, int, int)); |
7b167b09 | 179 | extern char *tic80_trace_ucond_br PARAMS ((int, unsigned32)); |
128b5154 | 180 | extern void tic80_trace_ldst PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int, int, int, int, unsigned32, unsigned32, unsigned32)); |
7b167b09 MM |
181 | |
182 | #define TRACE_ALU3(indx, result, input1, input2) \ | |
183 | do { \ | |
184 | if (TRACE_ALU_P (CPU)) { \ | |
185 | trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \ | |
186 | itable[indx].line_nr, "alu", \ | |
187 | tic80_trace_alu3 (indx, result, input1, input2)); \ | |
188 | } \ | |
189 | } while (0) | |
190 | ||
241b4624 MM |
191 | #define TRACE_CMP(indx, result, input1, input2) \ |
192 | do { \ | |
193 | if (TRACE_ALU_P (CPU)) { \ | |
194 | trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \ | |
195 | itable[indx].line_nr, "alu", \ | |
196 | tic80_trace_cmp (indx, result, input1, input2)); \ | |
197 | } \ | |
198 | } while (0) | |
199 | ||
7b167b09 MM |
200 | #define TRACE_ALU2(indx, result, input) \ |
201 | do { \ | |
202 | if (TRACE_ALU_P (CPU)) { \ | |
203 | trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \ | |
204 | itable[indx].line_nr, "alu", \ | |
205 | tic80_trace_alu2 (indx, result, input)); \ | |
206 | } \ | |
207 | } while (0) | |
208 | ||
450be234 MM |
209 | #define TRACE_SHIFT(indx, result, input, i, n, merge, endmask, rotate) \ |
210 | do { \ | |
211 | if (TRACE_ALU_P (CPU)) { \ | |
212 | trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \ | |
213 | itable[indx].line_nr, "shift", \ | |
214 | tic80_trace_shift (indx, result, input, i, n, \ | |
215 | merge, endmask, rotate)); \ | |
216 | } \ | |
217 | } while (0) | |
218 | ||
128b5154 | 219 | #define TRACE_FPU3(result, input1, input2) \ |
381f42ef AC |
220 | do { \ |
221 | if (TRACE_FPU_P (CPU)) { \ | |
128b5154 | 222 | tic80_trace_fpu3 (SD, CPU, cia, MY_INDEX, \ |
8114673a | 223 | &result, &input1, &input2); \ |
381f42ef AC |
224 | } \ |
225 | } while (0) | |
226 | ||
128b5154 | 227 | #define TRACE_FPU2(result, input) \ |
381f42ef AC |
228 | do { \ |
229 | if (TRACE_FPU_P (CPU)) { \ | |
128b5154 | 230 | tic80_trace_fpu2 (SD, CPU, cia, MY_INDEX, \ |
8114673a | 231 | &result, &input); \ |
381f42ef AC |
232 | } \ |
233 | } while (0) | |
234 | ||
128b5154 | 235 | #define TRACE_FPU1(result) \ |
aa3a0447 AC |
236 | do { \ |
237 | if (TRACE_FPU_P (CPU)) { \ | |
128b5154 | 238 | tic80_trace_fpu1 (SD, CPU, cia, MY_INDEX, \ |
8114673a | 239 | &result); \ |
aa3a0447 AC |
240 | } \ |
241 | } while (0) | |
242 | ||
128b5154 | 243 | #define TRACE_FPU2I(result, input1, input2) \ |
381f42ef AC |
244 | do { \ |
245 | if (TRACE_FPU_P (CPU)) { \ | |
128b5154 | 246 | tic80_trace_fpu2i (SD, CPU, cia, MY_INDEX, \ |
8114673a | 247 | result, &input1, &input2); \ |
381f42ef AC |
248 | } \ |
249 | } while (0) | |
250 | ||
241b4624 MM |
251 | #define TRACE_FPU2CMP(result, input1, input2) \ |
252 | do { \ | |
253 | if (TRACE_FPU_P (CPU)) { \ | |
254 | tic80_trace_fpu2cmp (SD, CPU, cia, MY_INDEX, \ | |
8114673a | 255 | result, &input1, &input2); \ |
241b4624 MM |
256 | } \ |
257 | } while (0) | |
258 | ||
7b167b09 MM |
259 | #define TRACE_NOP(indx) \ |
260 | do { \ | |
261 | if (TRACE_ALU_P (CPU)) { \ | |
262 | trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \ | |
263 | itable[indx].line_nr, "nop", \ | |
264 | tic80_trace_nop (indx)); \ | |
265 | } \ | |
266 | } while (0) | |
267 | ||
268 | #define TRACE_SINK1(indx, input) \ | |
269 | do { \ | |
270 | if (TRACE_ALU_P (CPU)) { \ | |
271 | trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \ | |
272 | itable[indx].line_nr, "nop", \ | |
273 | tic80_trace_sink1 (indx, input)); \ | |
274 | } \ | |
275 | } while (0) | |
276 | ||
277 | #define TRACE_SINK2(indx, input1, input2) \ | |
278 | do { \ | |
279 | if (TRACE_ALU_P (CPU)) { \ | |
280 | trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \ | |
281 | itable[indx].line_nr, "nop", \ | |
282 | tic80_trace_sink2 (indx, input1, input2)); \ | |
283 | } \ | |
284 | } while (0) | |
285 | ||
381f42ef AC |
286 | #define TRACE_SINK3(indx, input1, input2, input3) \ |
287 | do { \ | |
288 | if (TRACE_ALU_P (CPU)) { \ | |
289 | trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \ | |
290 | itable[indx].line_nr, "nop", \ | |
291 | tic80_trace_sink3 (indx, input1, input2, input3)); \ | |
292 | } \ | |
293 | } while (0) | |
294 | ||
99022131 | 295 | #define TRACE_COND_BR(indx, jump_p, cond, target, size, code) \ |
7b167b09 MM |
296 | do { \ |
297 | if (TRACE_BRANCH_P (CPU)) { \ | |
298 | trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \ | |
299 | itable[indx].line_nr, "branch", \ | |
99022131 MM |
300 | tic80_trace_cond_br (indx, jump_p, cond, target, \ |
301 | size, code)); \ | |
7b167b09 MM |
302 | } \ |
303 | } while (0) | |
304 | ||
305 | #define TRACE_UCOND_BR(indx, target) \ | |
306 | do { \ | |
c5ecfceb | 307 | if (TRACE_BRANCH_P (CPU)) { \ |
7b167b09 MM |
308 | trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \ |
309 | itable[indx].line_nr, "branch", \ | |
310 | tic80_trace_ucond_br (indx, target)); \ | |
311 | } \ | |
312 | } while (0) | |
313 | ||
128b5154 | 314 | #define TRACE_LD(result, m, s, addr1, addr2) \ |
7b167b09 MM |
315 | do { \ |
316 | if (TRACE_MEMORY_P (CPU)) { \ | |
128b5154 AC |
317 | tic80_trace_ldst (SD, CPU, cia, MY_INDEX, \ |
318 | 0, m, s, result, addr1, addr2); \ | |
7b167b09 MM |
319 | } \ |
320 | } while (0) | |
321 | ||
128b5154 | 322 | #define TRACE_ST(value, m, s, addr1, addr2) \ |
7b167b09 MM |
323 | do { \ |
324 | if (TRACE_MEMORY_P (CPU)) { \ | |
128b5154 AC |
325 | tic80_trace_ldst (SD, CPU, cia, MY_INDEX, \ |
326 | 1, m, s, value, addr1, addr2); \ | |
7b167b09 MM |
327 | } \ |
328 | } while (0) | |
329 | ||
330 | #else | |
331 | #define TRACE_ALU3(indx, result, input1, input2) | |
332 | #define TRACE_ALU2(indx, result, input) | |
128b5154 AC |
333 | #define TRACE_FPU3(result, input1, input2) |
334 | #define TRACE_FPU2(result, input) | |
335 | #define TRACE_FPU1(result) | |
336 | #define TRACE_FPU2I(result, input1, input2) | |
7b167b09 MM |
337 | #define TRACE_NOP(indx) |
338 | #define TRACE_SINK1(indx, input) | |
339 | #define TRACE_SINK2(indx, input1, input2) | |
381f42ef | 340 | #define TRACE_SINK3(indx, input1, input2, input3) |
99022131 | 341 | #define TRACE_COND_BR(indx, jump_p, cond, target, size, code) |
7b167b09 | 342 | #define TRACE_UCOND_BR(indx, target) |
128b5154 AC |
343 | #define TRACE_LD(m, s, result, addr1, addr2) |
344 | #define TRACE_ST(m, s, value, addr1, addr2) | |
7b167b09 | 345 | #endif |