Clear cntrl-c after handling it.
[deliverable/binutils-gdb.git] / sim / tic80 / cpu.h
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1/* TIc80 Simulator.
2 Copyright (C) 1997 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
4
5This file is part of GDB, the GNU debugger.
6
7This program is free software; you can redistribute it and/or modify
8it under the terms of the GNU General Public License as published by
9the Free Software Foundation; either version 2, or (at your option)
10any later version.
11
12This program is distributed in the hope that it will be useful,
13but WITHOUT ANY WARRANTY; without even the implied warranty of
14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License along
18with this program; if not, write to the Free Software Foundation, Inc.,
1959 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20
21
22
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23/* TI C80 control registers */
24
25typedef enum {
26 EPC_CR,
27 EIP_CR,
28 CONFIG_CR,
29 INTPEN_CR,
30 IE_CR,
31 FPST_CR,
32 PPERROR_CR,
33 PKTREQ_CR,
34 TCOUNT_CR,
35 TSCALE_CR,
36 FLTOP_CR,
37 FLTADR_CR,
38 FLTTAG_CR,
39 FLTDLT_CR,
40 FLTDTH_CR,
41 FLT005_CR,
42 FLT006_CR,
43 FLT007_CR,
44 FLT008_CR,
45 FLT009_CR,
46 FLT010_CR,
47 FLT011_CR,
48 FLT012_CR,
49 FLT013_CR,
50 FLT014_CR,
51 FLT015_CR,
52 SYSSTK_CR,
53 SYSTMP_CR,
54 MPC_CR,
55 MIP_CR,
56 ECOMCNTL_CR,
57 ANASTAT_CR,
58 BRK1_CR,
59 BRK2_CR,
60 ITAG0_CR,
61 ITAG1_CR,
62 ITAG2_CR,
63 ITAG3_CR,
64 ITAG4_CR,
65 ITAG5_CR,
66 ITAG6_CR,
67 ITAG7_CR,
68 ITAG8_CR,
69 ITAG9_CR,
70 ITAG10_CR,
71 ITAG11_CR,
72 ITAG12_CR,
73 ITAG13_CR,
74 ITAG14_CR,
75 ITAG15_CR,
76 ILRU_CR,
77 DTAG0_CR,
78 DTAG1_CR,
79 DTAG2_CR,
80 DTAG3_CR,
81 DTAG4_CR,
82 DTAG5_CR,
83 DTAG6_CR,
84 DTAG7_CR,
85 DTAG8_CR,
86 DTAG9_CR,
87 DTAG10_CR,
88 DTAG11_CR,
89 DTAG12_CR,
90 DTAG13_CR,
91 DTAG14_CR,
92 DTAG15_CR,
93 DLRU_CR,
94 IN0P_CR,
95 IN1P_CR,
96 OUTP_CR,
97 SCRATCH_CR,
98 nr_tic80_control_regs,
99} tic80_control_regs;
100
101/* extern int tic80_cr2index (tic80_control_regs reg); */
102
103/* Map an instruction CR index onto the corresponding internal cr enum
104 or SCRATCH_CR if the index is invalid */
105
106extern tic80_control_regs tic80_index2cr (int index);
107
108
109/* TIc80 interrupt register bits */
110
111enum {
112 IE_CR_PE = BIT32(31),
113 IE_CR_X4 = BIT32(30),
114 IE_CR_X3 = BIT32(29),
115 IE_CR_BP = BIT32(28),
116 IE_CR_PB = BIT32(27),
117 IE_CR_PC = BIT32(26),
118 IE_CR_MI = BIT32(25),
119 /**/
120 IE_CR_P3 = BIT32(19),
121 IE_CR_P2 = BIT32(18),
122 IE_CR_P1 = BIT32(17),
123 IE_CR_P0 = BIT32(16),
124 IE_CR_IO = BIT32(15),
125 IE_CR_MF = BIT32(14),
126 /**/
127 IE_CR_X2 = BIT32(12),
128 IE_CR_X1 = BIT32(11),
129 IE_CR_TI = BIT32(10),
130 IE_CR_F1 = BIT32(9),
131 IE_CR_F0 = BIT32(8),
132 IE_CR_FX = BIT32(7),
133 IE_CR_FU = BIT32(6),
134 IE_CR_FO = BIT32(5),
135 /**/
136 IE_CR_FZ = BIT32(3),
137 IE_CR_FI = BIT32(2),
138 /**/
139 IE_CR_IE = BIT32(0),
140};
141
142
143
144
d9b75947 145struct _sim_cpu {
abe293a0 146 unsigned32 reg[32];
d5e2c74e 147 unsigned64 acc[4];
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148 unsigned32 cr[nr_tic80_control_regs];
149 int is_user_mode; /* hidden mode latch */
d9b75947 150 sim_cia cia;
abe293a0 151 sim_cpu_base base;
d9b75947 152};
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153
154#define GPR(N) ((CPU)->reg[N])
abe293a0 155#define ACC(N) ((CPU)->acc[N])
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156#define CR(N) ((CPU)->cr[tic80_index2cr ((N))])
157
158
3971886a 159
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160#if defined(WITH_TRACE)
161extern char *tic80_trace_alu3 PARAMS ((int, unsigned32, unsigned32, unsigned32));
162extern char *tic80_trace_alu2 PARAMS ((int, unsigned32, unsigned32));
450be234 163extern char *tic80_trace_shift PARAMS ((int, unsigned32, unsigned32, int, int, int, int, int));
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164extern void tic80_trace_fpu3 PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int,
165 sim_fpu, sim_fpu, sim_fpu));
166extern void tic80_trace_fpu2 PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int,
167 sim_fpu, sim_fpu));
168extern void tic80_trace_fpu2i PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int,
169 unsigned32, sim_fpu, sim_fpu));
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170extern char *tic80_trace_nop PARAMS ((int));
171extern char *tic80_trace_sink1 PARAMS ((int, unsigned32));
172extern char *tic80_trace_sink2 PARAMS ((int, unsigned32, unsigned32));
381f42ef 173extern char *tic80_trace_sink3 PARAMS ((int, unsigned32, unsigned32, unsigned32));
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174extern char *tic80_trace_cond_br PARAMS ((int, int, unsigned32, unsigned32));
175extern char *tic80_trace_ucond_br PARAMS ((int, unsigned32));
176extern char *tic80_trace_ldst PARAMS ((int, int, int, int, unsigned32, unsigned32, unsigned32));
177
178#define TRACE_ALU3(indx, result, input1, input2) \
179do { \
180 if (TRACE_ALU_P (CPU)) { \
181 trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
182 itable[indx].line_nr, "alu", \
183 tic80_trace_alu3 (indx, result, input1, input2)); \
184 } \
185} while (0)
186
187#define TRACE_ALU2(indx, result, input) \
188do { \
189 if (TRACE_ALU_P (CPU)) { \
190 trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
191 itable[indx].line_nr, "alu", \
192 tic80_trace_alu2 (indx, result, input)); \
193 } \
194} while (0)
195
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196#define TRACE_SHIFT(indx, result, input, i, n, merge, endmask, rotate) \
197do { \
198 if (TRACE_ALU_P (CPU)) { \
199 trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
200 itable[indx].line_nr, "shift", \
201 tic80_trace_shift (indx, result, input, i, n, \
202 merge, endmask, rotate)); \
203 } \
204} while (0)
205
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206#define TRACE_FPU3(indx, result, input1, input2) \
207do { \
208 if (TRACE_FPU_P (CPU)) { \
209 tic80_trace_fpu3 (SD, CPU, cia, indx, result, input1, input2); \
210 } \
211} while (0)
212
213#define TRACE_FPU2(indx, result, input) \
214do { \
215 if (TRACE_FPU_P (CPU)) { \
216 tic80_trace_fpu2 (SD, CPU, cia, indx, result, input); \
217 } \
218} while (0)
219
220#define TRACE_FPU2I(indx, result, input1, input2) \
221do { \
222 if (TRACE_FPU_P (CPU)) { \
223 tic80_trace_fpu2i (SD, CPU, cia, indx, result, input1, input2); \
224 } \
225} while (0)
226
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227#define TRACE_NOP(indx) \
228do { \
229 if (TRACE_ALU_P (CPU)) { \
230 trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
231 itable[indx].line_nr, "nop", \
232 tic80_trace_nop (indx)); \
233 } \
234} while (0)
235
236#define TRACE_SINK1(indx, input) \
237do { \
238 if (TRACE_ALU_P (CPU)) { \
239 trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
240 itable[indx].line_nr, "nop", \
241 tic80_trace_sink1 (indx, input)); \
242 } \
243} while (0)
244
245#define TRACE_SINK2(indx, input1, input2) \
246do { \
247 if (TRACE_ALU_P (CPU)) { \
248 trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
249 itable[indx].line_nr, "nop", \
250 tic80_trace_sink2 (indx, input1, input2)); \
251 } \
252} while (0)
253
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254#define TRACE_SINK3(indx, input1, input2, input3) \
255do { \
256 if (TRACE_ALU_P (CPU)) { \
257 trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
258 itable[indx].line_nr, "nop", \
259 tic80_trace_sink3 (indx, input1, input2, input3)); \
260 } \
261} while (0)
262
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263#define TRACE_COND_BR(indx, jump_p, cond, target) \
264do { \
265 if (TRACE_BRANCH_P (CPU)) { \
266 trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
267 itable[indx].line_nr, "branch", \
268 tic80_trace_cond_br (indx, jump_p, cond, target)); \
269 } \
270} while (0)
271
272#define TRACE_UCOND_BR(indx, target) \
273do { \
274 if (TRACE_ALU_P (CPU)) { \
275 trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
276 itable[indx].line_nr, "branch", \
277 tic80_trace_ucond_br (indx, target)); \
278 } \
279} while (0)
280
281#define TRACE_LD(indx, result, m, s, addr1, addr2) \
282do { \
283 if (TRACE_MEMORY_P (CPU)) { \
284 trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
285 itable[indx].line_nr, "memory", \
286 tic80_trace_ldst (indx, 0, m, s, result, \
287 addr1, addr2)); \
288 } \
289} while (0)
290
291#define TRACE_ST(indx, value, m, s, addr1, addr2) \
292do { \
293 if (TRACE_MEMORY_P (CPU)) { \
294 trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
295 itable[indx].line_nr, "memory", \
296 tic80_trace_ldst (indx, 1, m, s, value, \
297 addr1, addr2)); \
298 } \
299} while (0)
300
301#else
302#define TRACE_ALU3(indx, result, input1, input2)
303#define TRACE_ALU2(indx, result, input)
304#define TRACE_NOP(indx)
305#define TRACE_SINK1(indx, input)
306#define TRACE_SINK2(indx, input1, input2)
381f42ef 307#define TRACE_SINK3(indx, input1, input2, input3)
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308#define TRACE_COND_BR(indx, jump_p, cond, target)
309#define TRACE_UCOND_BR(indx, target)
310#define TRACE_LD(indx, m, s, result, addr1, addr2)
311#define TRACE_ST(indx, m, s, value, addr1, addr2)
312#endif
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