[deliverable/binutils-gdb.git] / sim / tic80 / cpu.h

/* TIc80 Simulator.
   Copyright (C) 1997 Free Software Foundation, Inc.
   Contributed by Cygnus Support.

This file is part of GDB, the GNU debugger.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */


/* TI C80 control registers */

typedef enum {
  EPC_CR,
  EIP_CR,
  CONFIG_CR,
  INTPEN_CR,
  IE_CR,
  FPST_CR,
  PPERROR_CR,
  PKTREQ_CR,
  TCOUNT_CR,
  TSCALE_CR,
  FLTOP_CR,
  FLTADR_CR,
  FLTTAG_CR,
  FLTDLT_CR,
  FLTDTH_CR,
  FLT005_CR,
  FLT006_CR,
  FLT007_CR,
  FLT008_CR,
  FLT009_CR,
  FLT010_CR,
  FLT011_CR,
  FLT012_CR,
  FLT013_CR,
  FLT014_CR,
  FLT015_CR,
  SYSSTK_CR,
  SYSTMP_CR,
  MPC_CR,
  MIP_CR,
  ECOMCNTL_CR,
  ANASTAT_CR,
  BRK1_CR,
  BRK2_CR,
  ITAG0_CR,
  ITAG1_CR,
  ITAG2_CR,
  ITAG3_CR,
  ITAG4_CR,
  ITAG5_CR,
  ITAG6_CR,
  ITAG7_CR,
  ITAG8_CR,
  ITAG9_CR,
  ITAG10_CR,
  ITAG11_CR,
  ITAG12_CR,
  ITAG13_CR,
  ITAG14_CR,
  ITAG15_CR,
  ILRU_CR,
  DTAG0_CR,
  DTAG1_CR,
  DTAG2_CR,
  DTAG3_CR,
  DTAG4_CR,
  DTAG5_CR,
  DTAG6_CR,
  DTAG7_CR,
  DTAG8_CR,
  DTAG9_CR,
  DTAG10_CR,
  DTAG11_CR,
  DTAG12_CR,
  DTAG13_CR,
  DTAG14_CR,
  DTAG15_CR,
  DLRU_CR,
  IN0P_CR,
  IN1P_CR,
  OUTP_CR,
  SCRATCH_CR,
  nr_tic80_control_regs,
} tic80_control_regs;

/* extern int tic80_cr2index (tic80_control_regs reg); */

/* Map an instruction CR index onto the corresponding internal cr enum
   or SCRATCH_CR if the index is invalid */

extern tic80_control_regs tic80_index2cr (int index);


/* TIc80 interrupt register bits */

enum {
  IE_CR_PE = BIT32(31),
  IE_CR_X4 = BIT32(30),
  IE_CR_X3 = BIT32(29),
  IE_CR_BP = BIT32(28),
  IE_CR_PB = BIT32(27),
  IE_CR_PC = BIT32(26),
  IE_CR_MI = BIT32(25),
  /**/
  IE_CR_P3 = BIT32(19),
  IE_CR_P2 = BIT32(18),
  IE_CR_P1 = BIT32(17),
  IE_CR_P0 = BIT32(16),
  IE_CR_IO = BIT32(15),
  IE_CR_MF = BIT32(14),
  /**/
  IE_CR_X2 = BIT32(12),
  IE_CR_X1 = BIT32(11),
  IE_CR_TI = BIT32(10),
  IE_CR_F1 = BIT32(9),
  IE_CR_F0 = BIT32(8),
  IE_CR_FX = BIT32(7),
  IE_CR_FU = BIT32(6),
  IE_CR_FO = BIT32(5),
  /**/
  IE_CR_FZ = BIT32(3),
  IE_CR_FI = BIT32(2),
  /**/
  IE_CR_IE = BIT32(0),
};


struct _sim_cpu {
  unsigned32 reg[32];
  unsigned64 acc[4];
  unsigned32 cr[nr_tic80_control_regs];
  int is_user_mode; /* hidden mode latch */
  sim_cia cia;
  sim_cpu_base base;
};

#define GPR(N) ((CPU)->reg[N])
#define GPR_SET(N, VAL) ((CPU)->reg[N] = (VAL))
#define ACC(N) ((CPU)->acc[N])
#define CR(N) ((CPU)->cr[tic80_index2cr ((N))])


#if defined(WITH_TRACE)
extern char *tic80_trace_alu3	  PARAMS ((int, unsigned32, unsigned32, unsigned32));
extern char *tic80_trace_alu2	  PARAMS ((int, unsigned32, unsigned32));
extern char *tic80_trace_shift	  PARAMS ((int, unsigned32, unsigned32, int, int, int, int, int));
extern void tic80_trace_fpu3	  PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int, sim_fpu, sim_fpu, sim_fpu));
extern void tic80_trace_fpu2	  PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int, sim_fpu, sim_fpu));
extern void tic80_trace_fpu1	  PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int, sim_fpu));
extern void tic80_trace_fpu2i	  PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int, unsigned32, sim_fpu, sim_fpu));
extern char *tic80_trace_nop	  PARAMS ((int));
extern char *tic80_trace_sink1	  PARAMS ((int, unsigned32));
extern char *tic80_trace_sink2	  PARAMS ((int, unsigned32, unsigned32));
extern char *tic80_trace_sink3	  PARAMS ((int, unsigned32, unsigned32, unsigned32));
extern char *tic80_trace_cond_br  PARAMS ((int, int, unsigned32, unsigned32));
extern char *tic80_trace_ucond_br PARAMS ((int, unsigned32));
extern char *tic80_trace_ldst	  PARAMS ((int, int, int, int, unsigned32, unsigned32, unsigned32));

#define TRACE_ALU3(indx, result, input1, input2)			\
do {									\
  if (TRACE_ALU_P (CPU)) {						\
    trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file,		\
		    itable[indx].line_nr, "alu",			\
		    tic80_trace_alu3 (indx, result, input1, input2));	\
  }									\
} while (0)

#define TRACE_ALU2(indx, result, input)					\
do {									\
  if (TRACE_ALU_P (CPU)) {						\
    trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file,		\
		    itable[indx].line_nr, "alu",			\
		    tic80_trace_alu2 (indx, result, input));		\
  }									\
} while (0)

#define TRACE_SHIFT(indx, result, input, i, n, merge, endmask, rotate)	\
do {									\
  if (TRACE_ALU_P (CPU)) {						\
    trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file,		\
		    itable[indx].line_nr, "shift",			\
		    tic80_trace_shift (indx, result, input, i, n,	\
				       merge, endmask, rotate));	\
  }									\
} while (0)

#define TRACE_FPU3(indx, result, input1, input2)			\
do {									\
  if (TRACE_FPU_P (CPU)) {						\
    tic80_trace_fpu3 (SD, CPU, cia, indx, result, input1, input2);	\
  }									\
} while (0)

#define TRACE_FPU2(indx, result, input)					\
do {									\
  if (TRACE_FPU_P (CPU)) {						\
    tic80_trace_fpu2 (SD, CPU, cia, indx, result, input);		\
  }									\
} while (0)

#define TRACE_FPU1(indx, result)					\
do {									\
  if (TRACE_FPU_P (CPU)) {						\
    tic80_trace_fpu1 (SD, CPU, cia, indx, result);			\
  }									\
} while (0)

#define TRACE_FPU2I(indx, result, input1, input2)			\
do {									\
  if (TRACE_FPU_P (CPU)) {						\
    tic80_trace_fpu2i (SD, CPU, cia, indx, result, input1, input2);	\
  }									\
} while (0)

#define TRACE_NOP(indx)							\
do {									\
  if (TRACE_ALU_P (CPU)) {						\
    trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file,		\
		    itable[indx].line_nr, "nop",			\
		    tic80_trace_nop (indx));				\
  }									\
} while (0)

#define TRACE_SINK1(indx, input)					\
do {									\
  if (TRACE_ALU_P (CPU)) {						\
    trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file,		\
		    itable[indx].line_nr, "nop",			\
		    tic80_trace_sink1 (indx, input));			\
  }									\
} while (0)

#define TRACE_SINK2(indx, input1, input2)				\
do {									\
  if (TRACE_ALU_P (CPU)) {						\
    trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file,		\
		    itable[indx].line_nr, "nop",			\
		    tic80_trace_sink2 (indx, input1, input2));		\
  }									\
} while (0)

#define TRACE_SINK3(indx, input1, input2, input3)			\
do {									\
  if (TRACE_ALU_P (CPU)) {						\
    trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file,		\
		    itable[indx].line_nr, "nop",			\
		    tic80_trace_sink3 (indx, input1, input2, input3));	\
  }									\
} while (0)

#define TRACE_COND_BR(indx, jump_p, cond, target)			\
do {									\
  if (TRACE_BRANCH_P (CPU)) {						\
    trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file,		\
		    itable[indx].line_nr, "branch",			\
		    tic80_trace_cond_br (indx, jump_p, cond, target));	\
  }									\
} while (0)

#define TRACE_UCOND_BR(indx, target)					\
do {									\
  if (TRACE_ALU_P (CPU)) {						\
    trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file,		\
		    itable[indx].line_nr, "branch",			\
		    tic80_trace_ucond_br (indx, target));		\
  }									\
} while (0)

#define TRACE_LD(indx, result, m, s, addr1, addr2)			\
do {									\
  if (TRACE_MEMORY_P (CPU)) {						\
    trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file,		\
		    itable[indx].line_nr, "memory",			\
		    tic80_trace_ldst (indx, 0, m, s, result,		\
				      addr1, addr2));			\
  }									\
} while (0)

#define TRACE_ST(indx, value, m, s, addr1, addr2)			\
do {									\
  if (TRACE_MEMORY_P (CPU)) {						\
    trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file,		\
		    itable[indx].line_nr, "memory",			\
		    tic80_trace_ldst (indx, 1, m, s, value,		\
				      addr1, addr2));			\
  }									\
} while (0)

#else
#define TRACE_ALU3(indx, result, input1, input2)
#define TRACE_ALU2(indx, result, input)
#define TRACE_NOP(indx)
#define TRACE_SINK1(indx, input)
#define TRACE_SINK2(indx, input1, input2)
#define TRACE_SINK3(indx, input1, input2, input3)
#define TRACE_COND_BR(indx, jump_p, cond, target)
#define TRACE_UCOND_BR(indx, target)
#define TRACE_LD(indx, m, s, result, addr1, addr2)
#define TRACE_ST(indx, m, s, value, addr1, addr2)
#endif
Commit	Line	Data
d5e2c74e AC	1	/* TIc80 Simulator.
	2	Copyright (C) 1997 Free Software Foundation, Inc.
	3	Contributed by Cygnus Support.
	4
	5	This file is part of GDB, the GNU debugger.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
	9	the Free Software Foundation; either version 2, or (at your option)
	10	any later version.
	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License along
	18	with this program; if not, write to the Free Software Foundation, Inc.,
	19	59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
	20
	21
	22
381f42ef AC	23	/* TI C80 control registers */
	24
	25	typedef enum {
	26	EPC_CR,
	27	EIP_CR,
	28	CONFIG_CR,
	29	INTPEN_CR,
	30	IE_CR,
	31	FPST_CR,
	32	PPERROR_CR,
	33	PKTREQ_CR,
	34	TCOUNT_CR,
	35	TSCALE_CR,
	36	FLTOP_CR,
	37	FLTADR_CR,
	38	FLTTAG_CR,
	39	FLTDLT_CR,
	40	FLTDTH_CR,
	41	FLT005_CR,
	42	FLT006_CR,
	43	FLT007_CR,
	44	FLT008_CR,
	45	FLT009_CR,
	46	FLT010_CR,
	47	FLT011_CR,
	48	FLT012_CR,
	49	FLT013_CR,
	50	FLT014_CR,
	51	FLT015_CR,
	52	SYSSTK_CR,
	53	SYSTMP_CR,
	54	MPC_CR,
	55	MIP_CR,
	56	ECOMCNTL_CR,
	57	ANASTAT_CR,
	58	BRK1_CR,
	59	BRK2_CR,
	60	ITAG0_CR,
	61	ITAG1_CR,
	62	ITAG2_CR,
	63	ITAG3_CR,
	64	ITAG4_CR,
	65	ITAG5_CR,
	66	ITAG6_CR,
	67	ITAG7_CR,
	68	ITAG8_CR,
	69	ITAG9_CR,
	70	ITAG10_CR,
	71	ITAG11_CR,
	72	ITAG12_CR,
	73	ITAG13_CR,
	74	ITAG14_CR,
	75	ITAG15_CR,
	76	ILRU_CR,
	77	DTAG0_CR,
	78	DTAG1_CR,
	79	DTAG2_CR,
	80	DTAG3_CR,
	81	DTAG4_CR,
	82	DTAG5_CR,
	83	DTAG6_CR,
	84	DTAG7_CR,
	85	DTAG8_CR,
	86	DTAG9_CR,
87	DTAG10_CR,
88	DTAG11_CR,
89	DTAG12_CR,
90	DTAG13_CR,
91	DTAG14_CR,
92	DTAG15_CR,
93	DLRU_CR,
94	IN0P_CR,
95	IN1P_CR,
96	OUTP_CR,
97	SCRATCH_CR,
98	nr_tic80_control_regs,
99	} tic80_control_regs;
100
101	/* extern int tic80_cr2index (tic80_control_regs reg); */
102
103	/* Map an instruction CR index onto the corresponding internal cr enum
104	or SCRATCH_CR if the index is invalid */
105
106	extern tic80_control_regs tic80_index2cr (int index);
107
108
109	/* TIc80 interrupt register bits */
110
111	enum {
112	IE_CR_PE = BIT32(31),
113	IE_CR_X4 = BIT32(30),
114	IE_CR_X3 = BIT32(29),
115	IE_CR_BP = BIT32(28),
116	IE_CR_PB = BIT32(27),
117	IE_CR_PC = BIT32(26),
118	IE_CR_MI = BIT32(25),
119	/**/
120	IE_CR_P3 = BIT32(19),
121	IE_CR_P2 = BIT32(18),
122	IE_CR_P1 = BIT32(17),
123	IE_CR_P0 = BIT32(16),
124	IE_CR_IO = BIT32(15),
125	IE_CR_MF = BIT32(14),
126	/**/
127	IE_CR_X2 = BIT32(12),
128	IE_CR_X1 = BIT32(11),
129	IE_CR_TI = BIT32(10),
130	IE_CR_F1 = BIT32(9),
131	IE_CR_F0 = BIT32(8),
132	IE_CR_FX = BIT32(7),
133	IE_CR_FU = BIT32(6),
134	IE_CR_FO = BIT32(5),
135	/**/
136	IE_CR_FZ = BIT32(3),
137	IE_CR_FI = BIT32(2),
138	/**/
139	IE_CR_IE = BIT32(0),
140	};
141
142
143
144
d9b75947	145	struct _sim_cpu {
abe293a0	146	unsigned32 reg[32];
d5e2c74e	147	unsigned64 acc[4];
381f42ef AC	148	unsigned32 cr[nr_tic80_control_regs];
381f42ef AC	149	int is_user_mode; /* hidden mode latch */
d9b75947	150	sim_cia cia;
abe293a0	151	sim_cpu_base base;
d9b75947	152	};
15c16493 AC	153
15c16493 AC	154	#define GPR(N) ((CPU)->reg[N])
37a684b8	155	#define GPR_SET(N, VAL) ((CPU)->reg[N] = (VAL))
abe293a0	156	#define ACC(N) ((CPU)->acc[N])
381f42ef AC	157	#define CR(N) ((CPU)->cr[tic80_index2cr ((N))])
	158
	159
3971886a	160
7b167b09 MM	161	#if defined(WITH_TRACE)
	162	extern char *tic80_trace_alu3 PARAMS ((int, unsigned32, unsigned32, unsigned32));
	163	extern char *tic80_trace_alu2 PARAMS ((int, unsigned32, unsigned32));
450be234	164	extern char *tic80_trace_shift PARAMS ((int, unsigned32, unsigned32, int, int, int, int, int));
aa3a0447 AC	165	extern void tic80_trace_fpu3 PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int, sim_fpu, sim_fpu, sim_fpu));
	166	extern void tic80_trace_fpu2 PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int, sim_fpu, sim_fpu));
	167	extern void tic80_trace_fpu1 PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int, sim_fpu));
	168	extern void tic80_trace_fpu2i PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int, unsigned32, sim_fpu, sim_fpu));
7b167b09 MM	169	extern char *tic80_trace_nop PARAMS ((int));
	170	extern char *tic80_trace_sink1 PARAMS ((int, unsigned32));
	171	extern char *tic80_trace_sink2 PARAMS ((int, unsigned32, unsigned32));
381f42ef	172	extern char *tic80_trace_sink3 PARAMS ((int, unsigned32, unsigned32, unsigned32));
7b167b09 MM	173	extern char *tic80_trace_cond_br PARAMS ((int, int, unsigned32, unsigned32));
	174	extern char *tic80_trace_ucond_br PARAMS ((int, unsigned32));
	175	extern char *tic80_trace_ldst PARAMS ((int, int, int, int, unsigned32, unsigned32, unsigned32));
	176
	177	#define TRACE_ALU3(indx, result, input1, input2) \
	178	do { \
	179	if (TRACE_ALU_P (CPU)) { \
	180	trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
	181	itable[indx].line_nr, "alu", \
	182	tic80_trace_alu3 (indx, result, input1, input2)); \
	183	} \
	184	} while (0)
	185
	186	#define TRACE_ALU2(indx, result, input) \
	187	do { \
	188	if (TRACE_ALU_P (CPU)) { \
	189	trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
	190	itable[indx].line_nr, "alu", \
	191	tic80_trace_alu2 (indx, result, input)); \
	192	} \
	193	} while (0)
	194
450be234 MM	195	#define TRACE_SHIFT(indx, result, input, i, n, merge, endmask, rotate) \
	196	do { \
	197	if (TRACE_ALU_P (CPU)) { \
	198	trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
	199	itable[indx].line_nr, "shift", \
	200	tic80_trace_shift (indx, result, input, i, n, \
	201	merge, endmask, rotate)); \
	202	} \
	203	} while (0)
	204
381f42ef AC	205	#define TRACE_FPU3(indx, result, input1, input2) \
	206	do { \
	207	if (TRACE_FPU_P (CPU)) { \
	208	tic80_trace_fpu3 (SD, CPU, cia, indx, result, input1, input2); \
	209	} \
	210	} while (0)
	211
	212	#define TRACE_FPU2(indx, result, input) \
	213	do { \
	214	if (TRACE_FPU_P (CPU)) { \
	215	tic80_trace_fpu2 (SD, CPU, cia, indx, result, input); \
	216	} \
	217	} while (0)
	218
aa3a0447 AC	219	#define TRACE_FPU1(indx, result) \
	220	do { \
	221	if (TRACE_FPU_P (CPU)) { \
	222	tic80_trace_fpu1 (SD, CPU, cia, indx, result); \
	223	} \
	224	} while (0)
	225
381f42ef AC	226	#define TRACE_FPU2I(indx, result, input1, input2) \
	227	do { \
	228	if (TRACE_FPU_P (CPU)) { \
	229	tic80_trace_fpu2i (SD, CPU, cia, indx, result, input1, input2); \
	230	} \
	231	} while (0)
	232
7b167b09 MM	233	#define TRACE_NOP(indx) \
	234	do { \
	235	if (TRACE_ALU_P (CPU)) { \
	236	trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
	237	itable[indx].line_nr, "nop", \
	238	tic80_trace_nop (indx)); \
	239	} \
	240	} while (0)
	241
	242	#define TRACE_SINK1(indx, input) \
	243	do { \
	244	if (TRACE_ALU_P (CPU)) { \
	245	trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
	246	itable[indx].line_nr, "nop", \
	247	tic80_trace_sink1 (indx, input)); \
	248	} \
	249	} while (0)
	250
	251	#define TRACE_SINK2(indx, input1, input2) \
	252	do { \
	253	if (TRACE_ALU_P (CPU)) { \
	254	trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
	255	itable[indx].line_nr, "nop", \
	256	tic80_trace_sink2 (indx, input1, input2)); \
	257	} \
	258	} while (0)
	259
381f42ef AC	260	#define TRACE_SINK3(indx, input1, input2, input3) \
	261	do { \
	262	if (TRACE_ALU_P (CPU)) { \
	263	trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
	264	itable[indx].line_nr, "nop", \
	265	tic80_trace_sink3 (indx, input1, input2, input3)); \
	266	} \
	267	} while (0)
	268
7b167b09 MM	269	#define TRACE_COND_BR(indx, jump_p, cond, target) \
	270	do { \
	271	if (TRACE_BRANCH_P (CPU)) { \
	272	trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
	273	itable[indx].line_nr, "branch", \
	274	tic80_trace_cond_br (indx, jump_p, cond, target)); \
	275	} \
	276	} while (0)
	277
	278	#define TRACE_UCOND_BR(indx, target) \
	279	do { \
	280	if (TRACE_ALU_P (CPU)) { \
	281	trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
	282	itable[indx].line_nr, "branch", \
	283	tic80_trace_ucond_br (indx, target)); \
	284	} \
	285	} while (0)
	286
	287	#define TRACE_LD(indx, result, m, s, addr1, addr2) \
	288	do { \
	289	if (TRACE_MEMORY_P (CPU)) { \
	290	trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
	291	itable[indx].line_nr, "memory", \
	292	tic80_trace_ldst (indx, 0, m, s, result, \
	293	addr1, addr2)); \
	294	} \
	295	} while (0)
	296
	297	#define TRACE_ST(indx, value, m, s, addr1, addr2) \
	298	do { \
	299	if (TRACE_MEMORY_P (CPU)) { \
	300	trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
	301	itable[indx].line_nr, "memory", \
	302	tic80_trace_ldst (indx, 1, m, s, value, \
	303	addr1, addr2)); \
	304	} \
	305	} while (0)
	306
	307	#else
	308	#define TRACE_ALU3(indx, result, input1, input2)
	309	#define TRACE_ALU2(indx, result, input)
	310	#define TRACE_NOP(indx)
	311	#define TRACE_SINK1(indx, input)
	312	#define TRACE_SINK2(indx, input1, input2)
381f42ef	313	#define TRACE_SINK3(indx, input1, input2, input3)
7b167b09 MM	314	#define TRACE_COND_BR(indx, jump_p, cond, target)
	315	#define TRACE_UCOND_BR(indx, target)
	316	#define TRACE_LD(indx, m, s, result, addr1, addr2)
	317	#define TRACE_ST(indx, m, s, value, addr1, addr2)
	318	#endif