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[deliverable/binutils-gdb.git] / sim / tic80 / insns
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3971886a
AC		 1// Texas Instruments TMS320C80 (MVP) Simulator.
2// Copyright (C) 1997 Free Software Foundation, Inc.
3// Contributed by Cygnus Support.
4//
5// This file is part of GDB, the GNU debugger.
6//
7// This program is free software; you can redistribute it and/or modify
8// it under the terms of the GNU General Public License as published by
9// the Free Software Foundation; either version 2, or (at your option)
10// any later version.
11//
12// This program is distributed in the hope that it will be useful,
13// but WITHOUT ANY WARRANTY; without even the implied warranty of
14// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15// GNU General Public License for more details.
16//
17// You should have received a copy of the GNU General Public License along
18// with this program; if not, write to the Free Software Foundation, Inc.,
19// 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20
21
381f42ef 22// The following is called when ever an illegal instruction is encountered.
15c16493 23::internal::illegal
abe293a0 24 engine_error (SD, CPU, cia, "illegal instruction at 0x%lx", cia.ip);
381f42ef
AC		 25// The following is called when ever an FP op is attempted with FPU disabled.
26::internal::fp_unavailable
27 engine_error (SD, CPU, cia, "floating-point unavailable at 0x%lx", cia.ip);
15c16493
AC		 28
29// Signed Integer Add - add source1, source2, dest
381f42ef 30void::function::do_add:signed32 *rDest, signed32 Source1, signed32 Source2
15c16493
AC		 31 ALU_BEGIN (Source1);
32 ALU_ADD (Source2);
33 ALU_END (*rDest);
381f42ef 34 TRACE_ALU3 (MY_INDEX, *rDest, Source1, Source2);
480e740c
AC		 35 /* FIXME - a signed add may cause an exception */
3631.Dest,26.Source2,21.0b101100,15.0,14.SignedImmediate::::add i
381f42ef 37 do_add (_SD, rDest, vSource1, rSource2);
15c16493 3831.Dest,26.Source2,21.0b11101100,13.0,12.0,11./,4.Source1::::add r
381f42ef 39 do_add (_SD, rDest, rSource1, rSource2);
15c16493 4031.Dest,26.Source2,21.0b11101100,13.0,12.1,11./::::add l
abe293a0 41 long_immediate (LongSignedImmediate);
381f42ef 42 do_add (_SD, rDest, LongSignedImmediate, rSource2);
15c16493
AC		 43
44
45// Unsigned Integer Add - addu source1, source2, dest
381f42ef 46void::function::do_addu:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
7b167b09 47 unsigned32 result = Source1 + Source2;
381f42ef 48 TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
7b167b09
MM		 49 *rDest = result;
50
480e740c 5131.Dest,26.Source2,21.0b101100,15.1,14.SignedImmediate::::addu i
381f42ef 52 do_addu (_SD, rDest, vSource1, rSource2);
15c16493 5331.Dest,26.Source2,21.0b11101100,13.1,12.0,11./,4.Source1::::addu r
381f42ef 54 do_addu (_SD, rDest, rSource1, rSource2);
15c16493 5531.Dest,26.Source2,21.0b11101100,13.1,12.1,11./::::addu l
480e740c 56 long_immediate (LongSignedImmediate);
381f42ef 57 do_addu (_SD, rDest, LongSignedImmediate, rSource2);
15c16493
AC		 58
59
381f42ef 60void::function::do_and:signed32 *rDest, signed32 Source1, signed32 Source2
7b167b09 61 unsigned32 result = Source1 & Source2;
381f42ef 62 TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
7b167b09 63 *rDest = result;
15c16493
AC		 64
65
66// and, and.tt
480e740c 6731.Dest,26.Source2,21.0b0010001,14.SignedImmediate::::and.tt i
381f42ef 68 do_and (_SD, rDest, vSource1, rSource2);
480e740c 6931.Dest,26.Source2,21.0b110010001,12.0,11./,4.Source1::::and.tt r
381f42ef 70 do_and (_SD, rDest, rSource1, rSource2);
480e740c
AC		 7131.Dest,26.Source2,21.0b110010001,12.1,11./::::and.tt l
72 long_immediate (LongSignedImmediate);
381f42ef 73 do_and (_SD, rDest, LongSignedImmediate, rSource2);
15c16493
AC		 74
75
76// and.ff
480e740c 7731.Dest,26.Source2,21.0b0011000,14.SignedImmediate::::and.ff i
381f42ef 78 do_and (_SD, rDest, ~vSource1, ~rSource2);
480e740c 7931.Dest,26.Source2,21.0b110011000,12.0,11./,4.Source1::::and.ff r
381f42ef 80 do_and (_SD, rDest, ~rSource1, ~rSource2);
480e740c
AC		 8131.Dest,26.Source2,21.0b110011000,12.1,11./::::and.ff l
82 long_immediate (LongSignedImmediate);
381f42ef 83 do_and (_SD, rDest, ~LongSignedImmediate, ~rSource2);
15c16493
AC		 84
85
86// and.ft
480e740c 8731.Dest,26.Source2,21.0b0010100,14.SignedImmediate::::and.ft i
381f42ef 88 do_and (_SD, rDest, ~vSource1, rSource2);
480e740c 8931.Dest,26.Source2,21.0b110010100,12.0,11./,4.Source1::::and.ft r
381f42ef 90 do_and (_SD, rDest, ~rSource1, rSource2);
480e740c
AC		 9131.Dest,26.Source2,21.0b110010100,12.1,11./::::and.ft l
92 long_immediate (LongSignedImmediate);
381f42ef 93 do_and (_SD, rDest, ~LongSignedImmediate, rSource2);
15c16493
AC		 94
95
96// and.tf
480e740c 9731.Dest,26.Source2,21.0b0010010,14.SignedImmediate::::and.tf i
381f42ef 98 do_and (_SD, rDest, vSource1, ~rSource2);
480e740c 9931.Dest,26.Source2,21.0b110010010,12.0,11./,4.Source1::::and.tf r
381f42ef 100 do_and (_SD, rDest, rSource1, ~rSource2);
480e740c
AC		 10131.Dest,26.Source2,21.0b110010010,12.1,11./::::and.tf l
102 long_immediate (LongSignedImmediate);
381f42ef 103 do_and (_SD, rDest, LongSignedImmediate, ~rSource2);
15c16493
AC		 104
105
106// bbo.[a]
381f42ef 107instruction_address::function::do_bbo:instruction_address nia, int bitnum, unsigned32 source, int annul, unsigned32 offset
7b167b09
MM		 108 int jump_p;
109 unsigned32 target = cia.ip + 4 * offset;
480e740c
AC		 110 if (MASKED32 (source, bitnum, bitnum))
111 {
112 if (annul)
113 nia.ip = -1;
7b167b09
MM		 114 nia.dp = target;
115 jump_p = 1;
480e740c 116 }
7b167b09
MM		 117 else
118 jump_p = 0;
381f42ef 119 TRACE_COND_BR(MY_INDEX, jump_p, bitnum, target);
480e740c
AC		 120 return nia;
12131.BITNUM,26.Source,21.0b100101,15.A,14.SignedOffset::::bbo i
381f42ef 122 nia = do_bbo (_SD, nia, BITNUM, rSource, A, vSignedOffset);
480e740c 12331.BITNUM,26.Source,21.0b11100101,13.A,12.0,11./,4.IndOff::::bbo r
381f42ef 124 nia = do_bbo (_SD, nia, BITNUM, rSource, A, rIndOff);
480e740c
AC		 12531.BITNUM,26.Source,21.0b11100101,13.A,12.1,11./::::bbo l
126 long_immediate (LongSignedImmediate);
381f42ef 127 nia = do_bbo (_SD, nia, BITNUM, rSource, A, LongSignedImmediate);
15c16493
AC		 128
129
130// bbz[.a]
381f42ef 131instruction_address::function::do_bbz:instruction_address nia, int bitnum, unsigned32 source, int annul, unsigned32 offset
7b167b09
MM		 132 int jump_p;
133 unsigned32 target = cia.ip + 4 * offset;
15c16493
AC		 134 if (!MASKED32 (source, bitnum, bitnum))
135 {
136 if (annul)
137 nia.ip = -1;
7b167b09
MM		 138 nia.dp = target;
139 jump_p = 1;
15c16493 140 }
7b167b09
MM		 141 else
142 jump_p = 0;
381f42ef 143 TRACE_COND_BR(MY_INDEX, jump_p, bitnum, target);
15c16493 144 return nia;
480e740c 14531.BITNUM,26.Source,21.0b100100,15.A,14.SignedOffset::::bbz i
381f42ef 146 nia = do_bbz (_SD, nia, BITNUM, rSource, A, vSignedOffset);
15c16493 14731.BITNUM,26.Source,21.0b11100100,13.A,12.0,11./,4.IndOff::::bbz r
381f42ef 148 nia = do_bbz (_SD, nia, BITNUM, rSource, A, rIndOff);
15c16493 14931.BITNUM,26.Source,21.0b11100100,13.A,12.1,11./::::bbz l
480e740c 150 long_immediate (LongSignedImmediate);
381f42ef 151 nia = do_bbz (_SD, nia, BITNUM, rSource, A, LongSignedImmediate);
15c16493
AC		 152
153
154// bcnd[.a]
381f42ef 155instruction_address::function::do_bcnd:instruction_address nia, int Cond, unsigned32 source, int annul, unsigned32 offset
480e740c
AC		 156 int condition;
157 int size = EXTRACTED32 (Cond, 31 - 27, 30 - 27);
158 int code = EXTRACTED32 (Cond, 29 - 27, 27 - 27);
159 signed32 val = 0;
7b167b09 160 unsigned32 target = cia.ip + 4 * offset;
480e740c
AC		 161 switch (size)
162 {
163 case 0: val = SEXT32 (source, 7); break;
164 case 1: val = SEXT32 (source, 15); break;
165 case 2: val = source; break;
abe293a0 166 default: engine_error (SD, CPU, cia, "bcnd - reserved size");
480e740c
AC		 167 }
168 switch (code)
169 {
170 case 0: condition = 0; break;
171 case 1: condition = val > 0; break;
172 case 2: condition = val == 0; break;
173 case 3: condition = val >= 0; break;
174 case 4: condition = val < 0; break;
175 case 5: condition = val != 0; break;
176 case 6: condition = val <= 0; break;
177 default: condition = 1; break;
178 }
179 if (condition)
180 {
181 if (annul)
182 nia.ip = -1;
7b167b09 183 nia.dp = target;
480e740c 184 }
381f42ef 185 TRACE_COND_BR(MY_INDEX, condition, source, target);
480e740c
AC		 186 return nia;
18731.Code,26.Source,21.0b100110,15.A,14.SignedOffset::::bcnd i
381f42ef 188 nia = do_bcnd (_SD, nia, Code, rSource, A, vSignedOffset);
480e740c 18931.Code,26.Source,21.0b11100110,13.A,12.0,11./,4.IndOff::::bcnd r
381f42ef 190 nia = do_bcnd (_SD, nia, Code, rSource, A, rIndOff);
480e740c
AC		 19131.Code,26.Source,21.0b11100110,13.A,12.1,11./::::bcnd l
192 long_immediate (LongSignedImmediate);
381f42ef 193 nia = do_bcnd (_SD, nia, Code, rSource, A, LongSignedImmediate);
15c16493
AC		 194
195
196// br[.a] - see bbz[.a]
197
198
199// brcr
381f42ef
AC		 200sim_cia::function::do_brcr:instruction_address nia, int cr
201 if (cr >= 0x4000 || !(CPU)->is_user_mode)
202 {
203 unsigned32 control = CR (cr);
204 unsigned32 ie = control & 0x00000001;
205 unsigned32 pc = control & 0xfffffffc;
206 unsigned32 is_user_mode = control & 0x00000002;
207 (CPU)->is_user_mode = is_user_mode;
208 nia.dp = pc;
209 if (ie)
210 (CPU)->cr[IE_CR] |= IE_CR_IE;
211 else
212 (CPU)->cr[IE_CR] &= ~IE_CR_IE;
213 }
214 TRACE_UCOND_BR (MY_INDEX, nia.dp);
215 return nia;
21631.//,27.0,26.//,21.0b0000110,14.UCRN::::brcr i
217 nia = do_brcr (_SD, nia, UCRN);
21831.//,27.0,26.//,21.0b110000110,12.0,11./,4.INDCR::::brcr r
219 nia = do_brcr (_SD, nia, UCRN);
abe293a0 22031.//,27.0,26.//,21.0b110000110,12.1,11./::::brcr l
381f42ef
AC		 221 long_immediate (UnsignedControlRegisterNumber)
222 nia = do_brcr (_SD, nia, UnsignedControlRegisterNumber);
15c16493
AC		 223
224
225// bsr[.a]
381f42ef 226instruction_address::function::do_bsr:instruction_address nia, signed32 *rLink, int annul, unsigned32 offset
480e740c
AC		 227 if (annul)
228 {
229 *rLink = nia.ip;
230 nia.ip = -1;
231 }
232 else
233 *rLink = cia.dp + sizeof (instruction_word);
234 nia.dp = cia.ip + 4 * offset;
381f42ef 235 TRACE_UCOND_BR (MY_INDEX, nia.dp);
480e740c
AC		 236 return nia;
23731.Link,26./,21.0b100000,15.A,14.SignedOffset::::bsr i
381f42ef 238 nia = do_bsr (_SD, nia, rLink, A, vSignedOffset);
480e740c 23931.Link,26./,21.0b11100000,13.A,12.0,11./,4.IndOff::::bsr r
381f42ef 240 nia = do_bsr (_SD, nia, rLink, A, rIndOff);
480e740c
AC		 24131.Link,26./,21.0b11100000,13.A,12.1,11./::::bsr l
242 long_immediate (LongSignedImmediate);
381f42ef 243 nia = do_bsr (_SD, nia, rLink, A, LongSignedImmediate);
15c16493
AC		 244
245
246// cmnd
381f42ef 247void::function::do_cmnd:signed32 source
3971886a
AC		 248 int Reset = EXTRACTED32 (source, 31, 31);
249 int Halt = EXTRACTED32 (source, 30, 30);
250 int Unhalt = EXTRACTED32 (source, 29, 29);
251 /* int ICR = EXTRACTED32 (source, 28, 28); */
252 /* int DCR = EXTRACTED32 (source, 27, 27); */
253 int Task = EXTRACTED32 (source, 14, 14);
254 int Msg = EXTRACTED32 (source, 13, 13);
255 int VC = EXTRACTED32 (source, 10, 10);
256 int TC = EXTRACTED32 (source, 9, 9);
257 int MP = EXTRACTED32 (source, 8, 8);
258 int PP = EXTRACTED32 (source, 3, 0);
259 /* what is implemented? */
260 if (PP != 0)
261 engine_error (SD, CPU, cia, "0x%lx: cmnd - PPs not supported",
262 (unsigned long) cia.ip);
263 if (VC != 0)
264 engine_error (SD, CPU, cia, "0x%lx: cmnd - VC not supported",
265 (unsigned long) cia.ip);
266 if (TC != 0)
267 engine_error (SD, CPU, cia, "0x%lx: cmnd - TC not supported",
268 (unsigned long) cia.ip);
269 if (MP)
270 {
271 if (Reset || Halt)
272 engine_halt (SD, CPU, cia, sim_exited, 0);
273 if (Unhalt)
274 engine_error (SD, CPU, cia, "0x%lx: cmnd - Can not unhalt the MP",
275 (unsigned long) cia.ip);
276 /* if (ICR || DCR); */
277 if (Task)
278 engine_error (SD, CPU, cia, "0x%lx: cmnd - Can not Task the MP",
279 (unsigned long) cia.ip);
280 if (Msg)
281 engine_error (SD, CPU, cia, "0x%lx: cmnd - Msg to MP not suported",
282 (unsigned long) cia.ip);
283 }
381f42ef 284 TRACE_SINK1 (MY_INDEX, source);
abe293a0 28531./,21.0b0000010,14.UI::::cmnd i
381f42ef 286 do_cmnd (_SD, UI);
3971886a 28731./,21.0b110000010,12.0,11./,4.Source::::cmnd r
381f42ef 288 do_cmnd (_SD, rSource);
abe293a0 28931./,21.0b110000010,12.1,11./::::cmnd l
3971886a 290 long_immediate (LongUnsignedImmediate);
381f42ef 291 do_cmnd (_SD, LongUnsignedImmediate);
15c16493
AC		 292
293// cmp
480e740c
AC		 294unsigned32::function::cmp_vals:signed32 s1, unsigned32 u1, signed32 s2, unsigned32 u2
295 unsigned32 field = 0;
296 if (s1 == s2) field |= BIT32 (0);
297 if (s1 != s2) field |= BIT32 (1);
298 if (s1 > s2) field |= BIT32 (2);
299 if (s1 <= s2) field |= BIT32 (3);
300 if (s1 < s2) field |= BIT32 (4);
301 if (s1 >= s2) field |= BIT32 (5);
302 if (u1 > u2) field |= BIT32 (6);
303 if (u1 <= u2) field |= BIT32 (7);
304 if (u1 < u2) field |= BIT32 (8);
305 if (u1 >= u2) field |= BIT32 (9);
306 return field;
381f42ef 307void::function::do_cmp:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
480e740c
AC		 308 unsigned32 field = 0;
309 field |= INSERTED32 (cmp_vals (_SD, Source2, Source1, Source2, Source2),
310 29, 20);
311 field |= INSERTED32 (cmp_vals (_SD, (signed16)Source1, (unsigned16)Source1,
312 (signed16)Source2, (unsigned16)Source2),
313 19, 10);
314 field |= INSERTED32 (cmp_vals (_SD, (signed8)Source1, (unsigned8)Source1,
315 (signed8)Source2, (unsigned8)Source2),
316 9, 0);
381f42ef 317 TRACE_ALU3 (MY_INDEX, field, Source1, Source2);
480e740c
AC		 318 *rDest = field;
31931.Dest,26.Source2,21.0b1010000,14.SignedImmediate::::cmp i
381f42ef 320 do_cmp (_SD, rDest, vSource1, rSource2);
480e740c 32131.Dest,26.Source2,21.0b111010000,12.0,11./,4.Source1::::cmp r
381f42ef 322 do_cmp (_SD, rDest, rSource1, rSource2);
480e740c
AC		 32331.Dest,26.Source2,21.0b111010000,12.1,11./::::cmp l
324 long_immediate (LongSignedImmediate);
381f42ef 325 do_cmp (_SD, rDest, LongSignedImmediate, rSource2);
15c16493
AC		 326
327
328// dcache
480e740c 32931./,27.F,26.Source2,21.0b0111,17.M,16.0b00,14.SignedOffset::::dcache i
7b167b09 330 TRACE_NOP (MY_INDEX);
480e740c
AC		 331 /* NOP */
33231./,27.F,26.Source2,21.0b110111,15.M,14.0b00,12.0,11./,4.Source1::::dcache r
7b167b09 333 TRACE_NOP (MY_INDEX);
480e740c
AC		 334 /* NOP */
33531./,27.F,26.Source2,21.0b110111,15.M,14.0b00,12.1,11./::::dcache l
336 long_immediate (LongSignedImmediate);
c1c77d40 337 LongSignedImmediate++;
7b167b09 338 TRACE_NOP (MY_INDEX);
480e740c 339 /* NOP */
15c16493
AC		 340
341
342// dld[{.b|.h|.d}]
381f42ef
AC		 343void::function::do_dld:int Dest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
344 do_ld (_SD, Dest, Base, rBase, m, sz, S, Offset);
abe293a0 34531.Dest,26.Base,21.0b110100,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dld r
381f42ef 346 do_dld (_SD, Dest, rBase, &GPR(Base), m, sz, S, rIndOff);
abe293a0 34731.Dest,26.Base,21.0b110100,15.m,14.sz,12.1,11.S,10.1,9./::::dld l
d5e2c74e 348 long_immediate (LongSignedImmediateOffset);
381f42ef 349 do_dld (_SD, Dest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
15c16493
AC		 350
351
352// dld.u[{.b|.h|.d}]
381f42ef
AC		 353void::function::do_dld_u:unsigned32 *rDest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
354 do_ld_u (_SD, rDest, Base, rBase, m, sz, S, Offset);
abe293a0 35531.Dest,26.Base,21.0b110101,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dld.u r
381f42ef 356 do_dld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, rIndOff);
abe293a0 35731.Dest,26.Base,21.0b110101,15.m,14.sz,12.1,11.S,10.1,9./::::dld.u l
d5e2c74e 358 long_immediate (LongSignedImmediateOffset);
381f42ef 359 do_dld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
15c16493
AC		 360
361
362// dst[{.b|.h|.d}]
381f42ef
AC		 363void::function::do_dst:int Source, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
364 do_st (_SD, Source, Base, rBase, m, sz, S, Offset);
d5e2c74e 36531.Source,26.Base,21.0b110110,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dst r
381f42ef 366 do_dst (_SD, Source, rBase, &GPR(Base), m, sz, S, rIndOff);
d5e2c74e
AC		 36731.Source,26.Base,21.0b110110,15.m,14.sz,12.1,11.S,10.1,9./::::dst l
368 long_immediate (LongSignedImmediateOffset);
381f42ef 369 do_dst (_SD, Source, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
15c16493
AC		 370
371
372// estop
abe293a0 37331./,21.0b1111111,14.1,13.0,12.0,11./::::estop
15c16493 374
15c16493 375// etrap
abe293a0
AC		 37631./,27.1,26./,21.0b0000001,14.UTN::::etrap i
37731./,27.1,26./,21.0b110000001,12.0,11./,4.iUTN::::etrap r
37831./,27.1,26./,21.0b110000001,12.1,11./::::etrap l
15c16493
AC		 379
380
381// exts - see shift.ds
382
383
384// extu - see shift.dz
385
386
3971886a
AC		 387sim_fpu::function::get_fp_reg:int reg, unsigned32 val, int precision
388 switch (precision)
389 {
390 case 0: /* single */
391 if (reg == 0)
392 return sim_fpu_32to (0);
393 else
394 return sim_fpu_32to (val);
395 case 1: /* double */
396 if (reg < 0)
397 return sim_fpu_32to (val);
398 if (reg & 1)
399 engine_error (SD, CPU, cia, "DP FP register must be even");
400 if (reg <= 1)
401 engine_error (SD, CPU, cia, "DP FP register must be >= 2");
402 return sim_fpu_64to (INSERTED64 (GPR(reg + 1), 63, 32)
403 | INSERTED64 (GPR(reg), 31, 0));
404 case 2: /* 32 bit signed integer */
405 if (reg == 0)
406 return sim_fpu_32to (0);
407 else
408 return sim_fpu_d2 ((signed32) val);
409 case 3: /* 32 bit unsigned integer */
410 if (reg == 0)
411 return sim_fpu_32to (0);
412 else
413 return sim_fpu_d2 ((unsigned32) val);
414 default:
415 engine_error (SD, CPU, cia, "Unsupported FP precision");
416 }
417 return sim_fpu_32to (0);
418void::function::set_fp_reg:int Dest, sim_fpu val, int PD
419 switch (PD)
420 {
421 case 0: /* single */
422 {
423 GPR (Dest) = sim_fpu_to32 (val);
424 break;
425 }
426 case 1: /* double */
427 {
428 unsigned64 v = *(unsigned64*) &val;
429 if (Dest & 1)
430 engine_error (SD, CPU, cia, "DP FP Dest register must be even");
431 if (Dest <= 1)
432 engine_error (SD, CPU, cia, "DP FP Dest register must be >= 2");
433 GPR (Dest) = EXTRACTED64 (v, 21, 0);
434 GPR (Dest + 1) = EXTRACTED64 (v, 63, 32);
435 break;
436 }
437 case 2: /* signed */
438 /* FIXME - rounding */
439 GPR (Dest) = sim_fpu_2d (val);
440 break;
441 case 3: /* unsigned */
442 /* FIXME - rounding */
443 GPR (Dest) = sim_fpu_2d (val);
444 break;
445 default:
446 engine_error (SD, CPU, cia, "Unsupported FP precision");
447 }
448
15c16493 449// fadd.{s|d}{s|d}{s|d}
3971886a
AC		 450void::function::do_fadd:int Dest, int PD, sim_fpu s1, sim_fpu s2
451 sim_fpu ans = sim_fpu_add (s1, s2);
381f42ef 452 TRACE_FPU3 (MY_INDEX, ans, s1, s2);
3971886a 453 set_fp_reg (_SD, Dest, ans, PD);
381f42ef 45431.Dest,26.Source2,21.0b111110000,12.0,11.r,10.PD,8.P2,6.P1,4.Source1::f::fadd r
3971886a
AC		 455 do_fadd (_SD, Dest, PD,
456 get_fp_reg (_SD, Source1, rSource1, P1),
457 get_fp_reg (_SD, Source2, rSource2, P2));
381f42ef 45831.Dest,26.Source2,21.0b111110000,12.1,11.r,10.PD,8.P2,6.P1,4./::f::fadd l
3971886a
AC		 459 long_immediate (SinglePrecisionFloatingPoint);
460 do_fadd (_SD, Dest, PD,
461 get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
462 get_fp_reg (_SD, Source2, rSource2, P2));
15c16493
AC		 463
464
465// fcmp.{s|d}{s|d}{s|d}
3971886a
AC		 466void::function::do_fcmp:unsigned32 *rDest, sim_fpu s1, sim_fpu s2
467 *rDest = 0;
468 if (sim_fpu_is_nan (s1) || sim_fpu_is_nan (s2))
469 *rDest |= BIT32 (30);
470 else
471 {
472 *rDest |= BIT32 (31);
473 if (sim_fpu_cmp (s1, s2) == 0) *rDest |= BIT32(20);
474 if (sim_fpu_cmp (s1, s2) != 0) *rDest |= BIT32(21);
475 if (sim_fpu_cmp (s1, s2) > 0) *rDest |= BIT32(22);
476 if (sim_fpu_cmp (s1, s2) <= 0) *rDest |= BIT32(23);
477 if (sim_fpu_cmp (s1, s2) < 0) *rDest |= BIT32(24);
478 if (sim_fpu_cmp (s1, s2) >= 0) *rDest |= BIT32(25);
479 if (sim_fpu_cmp (s1, sim_fpu_32to (0)) < 0
480 || sim_fpu_cmp (s1, s2) > 0) *rDest |= BIT32(26);
481 if (sim_fpu_cmp (sim_fpu_32to (0), s1) < 0
482 && sim_fpu_cmp (s1, s2) < 0) *rDest |= BIT32(27);
483 if (sim_fpu_cmp (sim_fpu_32to (0), s1) <= 0
484 && sim_fpu_cmp (s1, s2) <= 0) *rDest |= BIT32(28);
485 if (sim_fpu_cmp (s1, sim_fpu_32to (0)) <= 0
486 || sim_fpu_cmp (s1, s2) >= 0) *rDest |= BIT32(29);
487 }
381f42ef
AC		 488 TRACE_FPU2I (MY_INDEX, *rDest, s1, s2);
48931.Dest,26.Source2,21.0b111110101,12.0,11./,10.0,8.P2,6.P1,4.Source1::f::fcmp r
3971886a
AC		 490 do_fcmp (_SD, rDest,
491 get_fp_reg (_SD, Source1, rSource1, P1),
492 get_fp_reg (_SD, Source2, rSource2, P2));
381f42ef 49331.Dest,26.Source2,21.0b111110101,12.1,11./,10.0,8.P2,6.P1,4./::f::fcmp l
3971886a
AC		 494 long_immediate (SinglePrecisionFloatingPoint);
495 do_fcmp (_SD, rDest,
496 get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
497 get_fp_reg (_SD, Source2, rSource2, P2));
498
15c16493
AC		 499
500
501// fdiv.{s|d}{s|d}{s|d}
3971886a
AC		 502void::function::do_fdiv:int Dest, int PD, sim_fpu s1, sim_fpu s2
503 sim_fpu ans = sim_fpu_div (s1, s2);
381f42ef 504 TRACE_FPU3 (MY_INDEX, ans, s1, s2);
3971886a 505 set_fp_reg (_SD, Dest, ans, PD);
381f42ef 50631.Dest,26.Source2,21.0b111110011,12.0,11./,10.PD,8.P2,6.P1,4.Source1::f::fdiv r
3971886a
AC		 507 do_fdiv (_SD, Dest, PD,
508 get_fp_reg (_SD, Source1, rSource1, P1),
509 get_fp_reg (_SD, Source2, rSource2, P2));
381f42ef 51031.Dest,26.Source2,21.0b111110011,12.1,11./,10.PD,8.P2,6.P1,4./::f::fdiv l
3971886a
AC		 511 long_immediate (SinglePrecisionFloatingPoint);
512 do_fdiv (_SD, Dest, PD,
513 get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
514 get_fp_reg (_SD, Source2, rSource2, P2));
15c16493
AC		 515
516
517// fmpy.{s|d|i|u}{s|d|i|u}{s|d|i|u}
3971886a
AC		 518void::function::do_fmpy:int Dest, int PD, sim_fpu s1, sim_fpu s2
519 sim_fpu ans = sim_fpu_mul (s1, s2);
381f42ef 520 TRACE_FPU3 (MY_INDEX, ans, s1, s2);
3971886a 521 set_fp_reg (_SD, Dest, ans, PD);
381f42ef 52231.Dest,26.Source2,21.0b111110010,12.0,11./,10.PD,8.P2,6.P1,4.Source1::f::fmpy r
3971886a
AC		 523 do_fmpy (_SD, Dest, PD,
524 get_fp_reg (_SD, Source1, rSource1, P1),
525 get_fp_reg (_SD, Source2, rSource2, P2));
381f42ef 52631.Dest,26.Source2,21.0b111110010,12.1,11./,10.PD,8.P2,6.P1,4./::f::fmpy l
3971886a
AC		 527 long_immediate (SinglePrecisionFloatingPoint);
528 do_fmpy (_SD, Dest, PD,
529 get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
530 get_fp_reg (_SD, Source2, rSource2, P2));
15c16493
AC		 531
532
533// frndm.{s|d|i|u}{s|d|i|u}{s|d|i|u}
3971886a
AC		 534void::function::do_frnd:int Dest, int PD, sim_fpu s1
535 set_fp_reg (_SD, Dest, s1, PD);
381f42ef 53631.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b11,6.P1,4.Source::f::frndm r
3971886a
AC		 537 do_frnd (_SD, Dest, PD,
538 get_fp_reg (_SD, Source, rSource, P1));
381f42ef 53931.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b11,6.P1,4./::f::frndm l
3971886a
AC		 540 long_immediate (SinglePrecisionFloatingPoint);
541 do_frnd (_SD, Dest, PD,
542 get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1));
15c16493
AC		 543
544
545// frndn.{s|d|i|u}{s|d|i|u}{s|d|i|u}
381f42ef 54631.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b00,6.P1,4.Source::f::frndn r
3971886a
AC		 547 do_frnd (_SD, Dest, PD,
548 get_fp_reg (_SD, Source, rSource, P1));
381f42ef 54931.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b00,6.P1,4./::f::frndn l
3971886a
AC		 550 long_immediate (SinglePrecisionFloatingPoint);
551 do_frnd (_SD, Dest, PD,
552 get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1));
15c16493
AC		 553
554
555// frndp.{s|d|i|u}{s|d|i|u}{s|d|i|u}
381f42ef 55631.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b10,6.P1,4.Source::f::frndp r
3971886a
AC		 557 do_frnd (_SD, Dest, PD,
558 get_fp_reg (_SD, Source, rSource, P1));
381f42ef 55931.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b10,6.P1,4./::f::frndp l
3971886a
AC		 560 long_immediate (SinglePrecisionFloatingPoint);
561 do_frnd (_SD, Dest, PD,
562 get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1));
15c16493
AC		 563
564
565// frndz.{s|d|i|u}{s|d|i|u}{s|d|i|u}
381f42ef 56631.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b01,6.P1,4.Source::f::frndz r
3971886a
AC		 567 do_frnd (_SD, Dest, PD,
568 get_fp_reg (_SD, Source, rSource, P1));
381f42ef 56931.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b01,6.P1,4./::f::frndz l
3971886a
AC		 570 long_immediate (SinglePrecisionFloatingPoint);
571 do_frnd (_SD, Dest, PD,
572 get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1));
15c16493
AC		 573
574
575// fsqrt.{s|d}{s|d}{s|d}
480e740c 576#void::function::do_fsqrt:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
15c16493 577# sim_io_error ("fsqrt");
381f42ef 57831.Dest,26.Source2,21.0b111110111,12.0,11./,10.PD,8.//,6.P1,4.Source1::f::fsqrt r
480e740c 579# do_fsqrt (_SD, rDest, rSource1, rSource2);
381f42ef 58031.Dest,26.Source2,21.0b111110111,12.1,11./,10.PD,8.//,6.P1,4./::f::fsqrt l
480e740c 581# do_fsqrt (_SD, rDest, LongSignedImmediate, rSource2);
15c16493
AC		 582
583
584// fsub.{s|d}{s|d}{s|d}
3971886a
AC		 585void::function::do_fsub:int Dest, int PD, sim_fpu s1, sim_fpu s2
586 sim_fpu ans = sim_fpu_sub (s1, s2);
381f42ef 587 TRACE_FPU3 (MY_INDEX, ans, s1, s2);
3971886a 588 set_fp_reg (_SD, Dest, ans, PD);
381f42ef 58931.Dest,26.Source2,21.0b111110001,12.0,11.r,10.PD,8.P2,6.P1,4.Source1::f::fsub r
3971886a
AC		 590 do_fsub (_SD, Dest, PD,
591 get_fp_reg (_SD, Source1, rSource1, P1),
592 get_fp_reg (_SD, Source2, rSource2, P2));
381f42ef 59331.Dest,26.Source2,21.0b111110001,12.1,11.r,10.PD,8.P2,6.P1,4./::f::fsub l
3971886a
AC		 594 long_immediate (SinglePrecisionFloatingPoint);
595 do_fsub (_SD, Dest, PD,
596 get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
597 get_fp_reg (_SD, Source2, rSource2, P2));
15c16493
AC		 598
599
600// illop
abe293a0
AC		 60131./,21.0b0000000,14./::::illop
60231./,21.0b111111111,12./::::illop l
15c16493
AC		 603
604
abe293a0 605// ins - see sl.im
15c16493
AC		 606
607
608// jsr[.a]
381f42ef
AC		 609instruction_address::function::do_jsr:instruction_address nia, signed32 *rLink, int annul, unsigned32 offset, unsigned32 base
610 TRACE_UCOND_BR (MY_INDEX, nia.ip);
480e740c
AC		 611 if (annul)
612 {
613 *rLink = nia.ip;
614 nia.ip = -1;
615 }
616 else
617 *rLink = cia.dp + sizeof (instruction_word);
d5e2c74e
AC		 618 nia.dp = offset + base;
619 if (nia.dp & 0x3)
3971886a
AC		 620 engine_error (SD, CPU, cia,
621 "0x%lx: destination address 0x%lx misaligned",
622 (unsigned long) cia.ip,
d5e2c74e 623 (unsigned long) nia.dp);
480e740c
AC		 624 return nia;
62531.Link,26.Base,21.0b100010,15.A,14.SignedOffset::::jsr i
381f42ef 626 nia = do_jsr (_SD, nia, rLink, A, vSignedOffset, rBase);
480e740c 62731.Link,26.Base,21.0b11100010,13.A,12.0,11./,4.Source1::::jsr r
381f42ef 628 nia = do_jsr (_SD, nia, rLink, A, rSource1, rBase);
480e740c
AC		 62931.Link,26.Base,21.0b11100010,13.A,12.1,11./::::jsr l
630 long_immediate (LongSignedImmediate);
381f42ef 631 nia = do_jsr (_SD, nia, rLink, A, LongSignedImmediate, rBase);
15c16493
AC		 632
633
634// ld[{.b.h.d}]
381f42ef 635void::function::do_ld:int Dest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
abe293a0
AC		 636 unsigned32 addr;
637 switch (sz)
638 {
639 case 0:
640 addr = Base + (S ? (Offset << 0) : Offset);
d5e2c74e
AC		 641 if (m)
642 *rBase = addr;
643 GPR(Dest) = MEM (signed, addr, 1);
abe293a0
AC		 644 break;
645 case 1:
646 addr = Base + (S ? (Offset << 1) : Offset);
d5e2c74e
AC		 647 if (m)
648 *rBase = addr;
649 GPR(Dest) = MEM (signed, addr, 2);
abe293a0
AC		 650 break;
651 case 2:
652 addr = Base + (S ? (Offset << 2) : Offset);
d5e2c74e
AC		 653 if (m)
654 *rBase = addr;
655 GPR(Dest) = MEM (signed, addr, 4);
abe293a0
AC		 656 break;
657 case 3:
d5e2c74e
AC		 658 if (Dest & 0x1)
659 engine_error (SD, CPU, cia, "0x%lx: ld.d to odd register %d",
660 cia.ip, Dest);
abe293a0 661 addr = Base + (S ? (Offset << 3) : Offset);
d5e2c74e
AC		 662 if (m)
663 *rBase = addr;
664 *(unsigned64*)(&GPR(Dest)) = MEM (signed, addr, 8);
abe293a0
AC		 665 break;
666 default:
667 addr = -1;
668 engine_error (SD, CPU, cia, "ld - invalid sz %d", sz);
669 }
381f42ef 670 TRACE_LD (MY_INDEX, m, S, GPR(Dest), Base, Offset);
abe293a0 67131.Dest,26.Base,21.0b0100,17.m,16.sz,14.SignedOffset::::ld i
381f42ef 672 do_ld (_SD, Dest, rBase, &GPR(Base), m, sz, 0, vSignedOffset);
abe293a0 67331.Dest,26.Base,21.0b110100,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::ld r
381f42ef 674 do_ld (_SD, Dest, rBase, &GPR(Base), m, sz, S, rIndOff);
abe293a0
AC		 67531.Dest,26.Base,21.0b110100,15.m,14.sz,12.1,11.S,10.0,9./::::ld l
676 long_immediate (LongSignedImmediateOffset);
381f42ef 677 do_ld (_SD, Dest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
15c16493
AC		 678
679
680// ld.u[{.b.h.d}]
381f42ef 681void::function::do_ld_u:unsigned32 *rDest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
abe293a0
AC		 682 unsigned32 addr;
683 switch (sz)
684 {
685 case 0:
686 addr = Base + (S ? (Offset << 0) : Offset);
687 *rDest = MEM (unsigned, addr, 1);
688 break;
689 case 1:
690 addr = Base + (S ? (Offset << 1) : Offset);
691 *rDest = MEM (unsigned, addr, 2);
692 break;
693 default:
694 addr = -1;
695 engine_error (SD, CPU, cia, "ld.u - invalid sz %d", sz);
696 }
697 if (m)
698 *rBase = addr;
381f42ef 699 TRACE_LD (MY_INDEX, m, S, *rDest, Base, Offset);
abe293a0 70031.Dest,26.Base,21.0b0101,17.m,16.sz,14.SignedOffset::::ld.u i
381f42ef 701 do_ld_u (_SD, rDest, rBase, &GPR(Base), m, sz, 0, vSignedOffset);
abe293a0 70231.Dest,26.Base,21.0b110101,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::ld.u r
381f42ef 703 do_ld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, rIndOff);
abe293a0
AC		 70431.Dest,26.Base,21.0b110101,15.m,14.sz,12.1,11.S,10.0,9./::::ld.u l
705 long_immediate (LongSignedImmediateOffset);
381f42ef 706 do_ld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
15c16493
AC		 707
708
709// lmo
abe293a0 71031.Dest,26.Source,21.111111000,12.0,11./::::lmo
381f42ef
AC		 711 int b;
712 for (b = 0; b < 32; b++)
713 if (rSource & BIT32 (31 - b))
714 break;
715 TRACE_ALU2 (MY_INDEX, b, rSource);
716 *rDest = b;
717
15c16493 718
abe293a0 719// nop - see rdcr 0, r0
15c16493
AC		 720
721
381f42ef 722void::function::do_or:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
7b167b09 723 unsigned32 result = Source1 | Source2;
381f42ef 724 TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
7b167b09 725 *rDest = result;
15c16493
AC		 726
727
728// or, or.tt
480e740c 72931.Dest,26.Source2,21.0b0010111,14.UnsignedImmediate::::or.tt i
381f42ef 730 do_or (_SD, rDest, vSource1, rSource2);
480e740c 73131.Dest,26.Source2,21.0b110010111,12.0,11./,4.Source1::::or.tt r
381f42ef 732 do_or (_SD, rDest, rSource1, rSource2);
480e740c
AC		 73331.Dest,26.Source2,21.0b110010111,12.1,11./::::or.tt l
734 long_immediate (LongUnsignedImmediate);
381f42ef 735 do_or (_SD, rDest, LongUnsignedImmediate, rSource2);
15c16493
AC		 736
737
738// or.ff
480e740c 73931.Dest,26.Source2,21.0b0011110,14.UnsignedImmediate::::or.ff i
381f42ef 740 do_or (_SD, rDest, ~vSource1, ~rSource2);
480e740c 74131.Dest,26.Source2,21.0b110011110,12.0,11./,4.Source1::::or.ff r
381f42ef 742 do_or (_SD, rDest, ~rSource1, ~rSource2);
480e740c
AC		 74331.Dest,26.Source2,21.0b110011110,12.1,11./::::or.ff l
744 long_immediate (LongUnsignedImmediate);
381f42ef 745 do_or (_SD, rDest, ~LongUnsignedImmediate, ~rSource2);
15c16493
AC		 746
747
748// or.ft
480e740c 74931.Dest,26.Source2,21.0b0011101,14.UnsignedImmediate::::or.ft i
381f42ef 750 do_or (_SD, rDest, ~vSource1, rSource2);
480e740c 75131.Dest,26.Source2,21.0b110011101,12.0,11./,4.Source1::::or.ft r
381f42ef 752 do_or (_SD, rDest, ~rSource1, rSource2);
480e740c
AC		 75331.Dest,26.Source2,21.0b110011101,12.1,11./::::or.ft l
754 long_immediate (LongUnsignedImmediate);
381f42ef 755 do_or (_SD, rDest, ~LongUnsignedImmediate, rSource2);
15c16493
AC		 756
757
758// or.tf
480e740c 75931.Dest,26.Source2,21.0b0011011,14.UnsignedImmediate::::or.tf i
381f42ef 760 do_or (_SD, rDest, vSource1, ~rSource2);
480e740c 76131.Dest,26.Source2,21.0b110011011,12.0,11./,4.Source1::::or.tf r
381f42ef 762 do_or (_SD, rDest, rSource1, ~rSource2);
480e740c
AC		 76331.Dest,26.Source2,21.0b110011011,12.1,11./::::or.tf l
764 long_immediate (LongUnsignedImmediate);
381f42ef 765 do_or (_SD, rDest, LongUnsignedImmediate, ~rSource2);
15c16493
AC		 766
767
768// rdcr
381f42ef
AC		 769void::function::do_rdcr:unsigned32 Dest, int cr
770 TRACE_SINK2 (MY_INDEX, Dest, cr);
771 GPR (Dest) = CR (cr);
abe293a0 77231.Dest,26.0,21.0b0000100,14.UCRN::::rdcr i
381f42ef 773 do_rdcr (_SD, Dest, UCRN);
abe293a0 77431.Dest,26.0,21.0b110000100,12.0,11./,4.INDCR::::rdcr r
381f42ef 775 do_rdcr (_SD, Dest, UCRN);
abe293a0 77631.Dest,26.0,21.0b110000100,12.1,11./::::rdcr l
d5e2c74e 777 long_immediate (UnsignedControlRegisterNumber);
381f42ef 778 do_rdcr (_SD, Dest, UnsignedControlRegisterNumber);
15c16493
AC		 779
780
781// rmo
abe293a0 78231.Dest,26.Source,21.0b111111001,12.0,11./::::rmo
381f42ef
AC		 783 int b;
784 for (b = 0; b < 32; b++)
785 if (rSource & BIT32 (b))
786 break;
787 if (b < 32)
788 b = 31 - b;
789 TRACE_ALU2 (MY_INDEX, b, rSource);
790 *rDest = b;
15c16493
AC		 791
792
abe293a0 793// rotl - see sl.dz
15c16493
AC		 794
795
381f42ef 796// rotr - see sl.dz
15c16493
AC		 797
798
abe293a0 799// shl - see sl.iz
15c16493
AC		 800
801
802// sl.{d|e|i}{m|s|z}
381f42ef 803void::function::do_shift:int Dest, int Source, int Merge, int i, int n, int EndMask, int Rotate
c1c77d40 804 /* see 10-30 for a reasonable description */
7b167b09 805 unsigned32 input = GPR (Source);
c1c77d40
AC		 806 unsigned32 rotated;
807 unsigned32 endmask;
808 unsigned32 shiftmask;
809 unsigned32 cm;
810 int nRotate;
811 /* rotate the source */
812 if (n)
813 {
814 rotated = ROTR32 (GPR (Source), Rotate);
815 nRotate = (- Rotate) & 31;
816 }
817 else
818 {
819 rotated = ROTL32 (GPR (Source), Rotate);
820 nRotate = Rotate;
821 }
822 /* form the end mask */
823 if (EndMask == 0)
824 endmask = -1;
825 else
826 endmask = (1 << EndMask) - 1;
827 if (i)
828 endmask = ~endmask;
829 /* form the shiftmask */
830 switch (Merge)
831 {
832 case 0: case 1: case 2:
833 shiftmask = -1; /* disabled */
834 break;
835 case 3: case 4: case 5:
836 shiftmask = ((1 << nRotate) - 1); /* enabled */
837 break;
838 case 6: case 7:
839 shiftmask = ~((1 << nRotate) - 1); /* inverted */
840 break;
841 default:
842 engine_error (SD, CPU, cia,
843 "0x%lx: Invalid merge (%d) for shift",
844 cia.ip, Source);
845 shiftmask = 0;
846 }
847 /* and the composite mask */
848 cm = shiftmask & endmask;
849 /* and merge */
850 switch (Merge)
851 {
852 case 0: case 3: case 6: /* zero */
853 GPR (Dest) = rotated & cm;
854 break;
855 case 1: case 4: case 7: /* merge */
856 GPR (Dest) = (rotated & cm) | (GPR (Dest) & ~cm);
857 break;
858 case 2: case 5: /* sign */
859 {
860 int b;
861 GPR (Dest) = rotated & cm;
862 for (b = 1; b <= 31; b++)
863 if (!MASKED32 (cm, b, b))
864 GPR (Dest) |= INSERTED32 (EXTRACTED32 (GPR (Dest), b - 1, b - 1),
865 b, b);
866 }
867 break;
868 default:
869 engine_error (SD, CPU, cia,
870 "0x%lx: Invalid merge (%d)",
871 cia.ip, Source);
872
873 }
381f42ef 874 TRACE_ALU2 (MY_INDEX, GPR (Dest), input);
c1c77d40 87531.Dest,26.Source,21.0b0001,17.Merge,14./,11.i,10.n,9.EndMask,4.Rotate::::sl i
381f42ef 876 do_shift (_SD, Dest, Source, Merge, i, n, EndMask, Rotate);
c1c77d40
AC		 87731.Dest,26.Source,21.0b110001,15.Merge,12.0,11.i,10.n,9.EndMask,4.RotReg::::sl r
878 int endmask;
879 if (EndMask == 0)
880 endmask = EndMask;
881 else
882 {
883 if (Source & 1)
884 engine_error (SD, CPU, cia,
885 "0x%lx: Invalid source (%d) for shift",
886 cia.ip, Source);
887 endmask = GPR (Source + 1) & 31;
888 }
381f42ef 889 do_shift (_SD, Dest, Source, Merge, i, n, endmask, GPR (RotReg) & 31);
15c16493
AC		 890
891
381f42ef 892// sli.{d|e|i}{m|s|z} - see shift
15c16493
AC		 893
894
381f42ef 895// sr.{d|e|i}{m|s|z} - see shift
15c16493
AC		 896
897
381f42ef 898// sra - see sr.es - see shift
15c16493
AC		 899
900
381f42ef 901// sri.{d|e|i}{m|s|z} - see shift
15c16493
AC		 902
903
904// srl - see sr.ez
905
906
907// st[{.b|.h|.d}]
381f42ef 908void::function::do_st:int Source, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
abe293a0
AC		 909 unsigned32 addr;
910 switch (sz)
911 {
912 case 0:
913 addr = Base + (S ? (Offset << 0) : Offset);
d5e2c74e 914 STORE (addr, 1, GPR(Source));
abe293a0
AC		 915 break;
916 case 1:
917 addr = Base + (S ? (Offset << 1) : Offset);
d5e2c74e 918 STORE (addr, 2, GPR(Source));
abe293a0
AC		 919 break;
920 case 2:
921 addr = Base + (S ? (Offset << 2) : Offset);
d5e2c74e 922 STORE (addr, 4, GPR(Source));
abe293a0
AC		 923 break;
924 case 3:
d5e2c74e
AC		 925 if (Source & 0x1)
926 engine_error (SD, CPU, cia, "0x%lx: st.d with odd source register %d",
927 cia.ip, Source);
abe293a0 928 addr = Base + (S ? (Offset << 3) : Offset);
d5e2c74e 929 STORE (addr, 8, *(unsigned64*)&GPR(Source));
abe293a0
AC		 930 break;
931 default:
932 addr = -1;
d5e2c74e 933 engine_error (SD, CPU, cia, "st - invalid sz %d", sz);
abe293a0
AC		 934 }
935 if (m)
936 *rBase = addr;
381f42ef 937 TRACE_ST (MY_INDEX, m, S, Source, Base, Offset);
abe293a0 93831.Source,26.Base,21.0b0110,17.m,16.sz,14.SignedOffset::::st i
381f42ef 939 do_st (_SD, Source, rBase, &GPR(Base), m, sz, 0, vSignedOffset);
abe293a0 94031.Source,26.Base,21.0b110110,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::st r
381f42ef 941 do_st (_SD, Source, rBase, &GPR(Base), m, sz, S, rIndOff);
abe293a0
AC		 94231.Source,26.Base,21.0b110110,15.m,14.sz,12.1,11.S,10.0,9./::::st l
943 long_immediate (LongSignedImmediateOffset);
381f42ef 944 do_st (_SD, Source, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
15c16493
AC		 945
946
947// sub
381f42ef 948void::function::do_sub:signed32 *rDest, signed32 Source1, signed32 Source2
abe293a0
AC		 949 ALU_BEGIN (Source1);
950 ALU_SUB (Source2);
7b167b09 951 ALU_END (*rDest);
381f42ef 952 TRACE_ALU3 (MY_INDEX, *rDest, Source1, Source2);
abe293a0 95331.Dest,26.Source2,21.0b101101,15.0,14.SignedImmediate::::sub i
381f42ef 954 do_sub (_SD, rDest, vSource1, rSource2);
abe293a0 95531.Dest,26.Source2,21.0b11101101,13.0,12.0,11./,4.Source1::::sub r
381f42ef 956 do_sub (_SD, rDest, rSource1, rSource2);
abe293a0
AC		 95731.Dest,26.Source2,21.0b11101101,13.0,12.1,11./::::sub l
958 long_immediate (LongSignedImmediate);
381f42ef 959 do_sub (_SD, rDest, LongSignedImmediate, rSource2);
15c16493
AC		 960
961
962// subu
381f42ef 963void::function::do_subu:signed32 *rDest, signed32 Source1, signed32 Source2
7b167b09 964 unsigned32 result = Source1 - Source2;
381f42ef 965 TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
7b167b09 966 *rDest = result;
d5e2c74e 967// NOTE - the book has 15.1 which conflicts with subu.
abe293a0 96831.Dest,26.Source2,21.0b101101,15.1,14.SignedImmediate::::subu i
381f42ef 969 do_subu (_SD, rDest, vSource1, rSource2);
abe293a0 97031.Dest,26.Source2,21.0b11101101,13.1,12.0,11./,4.Source1::::subu r
381f42ef 971 do_subu (_SD, rDest, rSource1, rSource2);
abe293a0
AC		 97231.Dest,26.Source2,21.0b11101101,13.1,12.1,11./::::subu l
973 long_immediate (LongSignedImmediate);
381f42ef 974 do_subu (_SD, rDest, LongSignedImmediate, rSource2);
15c16493
AC		 975
976
977// swcr
381f42ef
AC		 978void::function::do_swcr:int Dest, signed32 rSource, signed32 cr
979 tic80_control_regs reg = tic80_index2cr (cr);
980 /* cache the old CR value */
981 unsigned32 old_cr = CR (cr);
982 /* Handle the write if allowed */
983 if (cr >= 0x4000 || !(CPU)->is_user_mode)
984 switch (reg)
985 {
986 case INTPEN_CR:
987 CR (cr) &= ~rSource;
988 break;
989 default:
990 CR (cr) = rSource;
991 break;
992 }
993 /* Finish off the read */
994 GPR (Dest) = old_cr;
995 TRACE_SINK3 (MY_INDEX, rSource, cr, Dest);
99631.Dest,26.Source,21.0b000010,15.1,14.UCRN::::swcr i
997 do_swcr (_SD, Dest, rSource, UCRN);
abe293a0 99831.Dest,26.Source,21.0b11000010,13.1,12.0,11./,4.INDCR::::swcr r
381f42ef 999 do_swcr (_SD, Dest, rSource, UCRN);
abe293a0 100031.Dest,26.Source,21.0b11000010,13.1,12.1,11./::::swcr l
381f42ef
AC		 1001 long_immediate (LongUnsignedControlRegister);
1002 do_swcr (_SD, Dest, rSource, LongUnsignedControlRegister);
15c16493
AC		 1003
1004
1005// trap
381f42ef
AC		 1006void::function::do_trap:unsigned32 trap_number
1007 TRACE_SINK1 (MY_INDEX, trap_number);
d5e2c74e 1008 switch (trap_number)
15c16493 1009 {
d5e2c74e
AC		 1010 case 72:
1011 switch (GPR(15))
15c16493
AC		 1012 {
1013 case 1: /* EXIT */
1014 {
d5e2c74e 1015 engine_halt (SD, CPU, cia, sim_exited, GPR(2));
15c16493
AC		 1016 break;
1017 }
1018 case 4: /* WRITE */
1019 {
1020 int i;
3971886a
AC		 1021 if (GPR(2) == 1)
1022 for (i = 0; i < GPR(6); i++)
1023 {
1024 char c;
1025 c = MEM (unsigned, GPR(4) + i, 1);
1026 sim_io_write_stdout (SD, &c, 1);
1027 }
1028 else if (GPR(2) == 2)
1029 for (i = 0; i < GPR(6); i++)
1030 {
1031 char c;
1032 c = MEM (unsigned, GPR(4) + i, 1);
1033 sim_io_write_stderr (SD, &c, 1);
1034 }
1035 else
c1c77d40
AC		 1036 engine_error (SD, CPU, cia,
1037 "0x%lx: write to invalid fid %d",
1038 (unsigned long) cia.ip, GPR(2));
d5e2c74e 1039 GPR(2) = GPR(6);
15c16493
AC		 1040 break;
1041 }
1042 default:
c1c77d40
AC		 1043 engine_error (SD, CPU, cia,
1044 "0x%lx: unknown syscall %d",
1045 (unsigned long) cia.ip, GPR(15));
15c16493 1046 }
d5e2c74e 1047 break;
c1c77d40
AC		 1048 case 73:
1049 engine_halt (SD, CPU, cia, sim_stopped, SIGTRAP);
d5e2c74e 1050 default:
c1c77d40
AC		 1051 engine_error (SD, CPU, cia,
1052 "0x%lx: unsupported trap %d",
1053 (unsigned long) cia.ip, trap_number);
15c16493
AC		 1054 }
105531./,27.0,26./,21.0b0000001,14.UTN::::trap i
381f42ef 1056 do_trap (_SD, UTN);
15c16493 105731./,27.0,26./,21.0b110000001,12.0,11./,4.INDTR::::trap r
381f42ef 1058 do_trap (_SD, UTN);
15c16493
AC		 105931./,27.0,26./,21.0b110000001,12.1,11./::::trap l
1060 long_immediate (UTN);
381f42ef 1061 do_trap (_SD, UTN);
15c16493
AC		 1062
1063
1064// vadd.{s|d}{s|d}
381f42ef
AC		 106531.*,26.Dest,21.0b11110,16./,15.0b000,12.0,11./,10.*,9.*,7.PD,6.*,5.P1,4.Source::f::vadd r
106631.*,26.Dest,21.0b11110,16./,15.0b000,12.1,11./,10.*,9.*,7.PD,6.*,5.P1,4.Source::f::vadd l
15c16493
AC		 1067
1068
abe293a0 1069// vld{0|1}.{s|d} - see above - same instruction
381f42ef 1070#31.Dest,26.*,21.0b11110,16.*,10.1,9.S,8.*,6.p,7.******::f::vld
15c16493
AC		 1071
1072
1073// vmac.ss{s|d}
381f42ef
AC		 1074#31.*, 26.Source2,21.0b11110,16.a0,15.0b110,12.0,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4.Source1::f::vmac.ss ra
107531.Dest,26.Source2,21.0b11110,16.a0,15.0b110,12.0,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4.Source1::f::vmac.ss rr
1076#31.*, 26.Source2,21.0b11110,16.a0,15.0b110,12.1,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4./::f::vmac.ss ia
107731.Dest,26.Source2,21.0b11110,16.a0,15.0b110,12.1,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4./::f::vmac.ss ir
15c16493
AC		 1078
1079
1080// vmpy.{s|d}{s|d}
381f42ef
AC		 108131.*,26.Dest,21.0b11110,16./,15.0b010,12.0,11./,10.*,8.*,7.PD,6.*,5.P1,4.Source::f::vmpy r
108231.*,26.Dest,21.0b11110,16./,15.0b010,12.1,11./,10.*,8.*,7.PD,6.*,5.P1,4./::f::vmpy l
15c16493
AC		 1083
1084
1085// vmsc.ss{s|d}
381f42ef
AC		 1086#31.*, 26.Source2,21.0b11110,16.a0,15.0b111,12.0,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4.Source1::f::vmsc.ss ra
108731.Dest,26.Source2,21.0b11110,16.a0,15.0b111,12.0,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4.Source1::f::vmsc.ss rr
1088#31.*, 26.Source2,21.0b11110,16.a0,15.0b111,12.1,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4./::f::vmsc.ss ia
108931.Dest,26.Source2,21.0b11110,16.a0,15.0b111,12.1,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4./::f::vmsc.ss ir
15c16493
AC		 1090
1091
1092// vmsub.{s|d}{s|d}
381f42ef
AC		 109331.*,26.Dest,21.0b11110,16.a0,15.0b011,12.0,11.a1,10.*,8.Z,7.PD,6.*,5./,4.Source::f::vmsub r
109431.*,26.Dest,21.0b11110,16.a0,15.0b011,12.1,11.a1,10.*,8.Z,7.PD,6.*,5./,4./::f::vmsub l
15c16493
AC		 1095
1096
1097// vrnd.{s|d}{s|d}
381f42ef
AC		 109831.*,26.Dest,21.0b11110,16.a0,15.0b100,12.0,11.a1,10.*,8.PD,6.*,5.P1,4.Source::f::vrnd f r
109931.*,26.Dest,21.0b11110,16.a0,15.0b100,12.1,11.a1,10.*,8.PD,6.*,5.P1,4./::f::vrnd f l
15c16493
AC		 1100
1101
1102// vrnd.{i|u}{s|d}
381f42ef
AC		 110331.*,26.Dest,21.0b11110,16./,15.0b101,12.0,11./,10.*,8./,7.PD,6.*,5.P1,4.Source::f::vrnd i r
110431.*,26.Dest,21.0b11110,16./,15.0b101,12.1,11./,10.*,8./,7.PD,6.*,5.P1,4./::f::vrnd i l
15c16493
AC		 1105
1106
abe293a0 1107// vst.{s|d} - see above - same instruction
381f42ef 1108#31.Source,26.*,21.0b11110,16.*,10.0,9.S,8.*,6.1,5.*::f::vst
15c16493
AC		 1109
1110
1111// vsub.{i|u}{s|d}
381f42ef
AC		 111231.*,26.Dest,21.0b11110,16./,15.0b001,12.0,11./,10.*,8./,7.PD,6.*,5.P1,4.Source::f::vsub r
111331.*,26.Dest,21.0b11110,16./,15.0b001,12.1,11./,10.*,8./,7.PD,6.*,5.P1,4./::f::vsub l
15c16493
AC		 1114
1115
abe293a0 1116// wrcr - see swcr, creg, source, r0
15c16493
AC		 1117
1118
1119// xnor
381f42ef 1120void::function::do_xnor:signed32 *rDest, signed32 Source1, signed32 Source2
7b167b09 1121 unsigned32 result = ~ (Source1 ^ Source2);
381f42ef 1122 TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
7b167b09 1123 *rDest = result;
abe293a0 112431.Dest,26.Source2,21.0b0011001,14.UnsignedImmediate::::xnor i
381f42ef 1125 do_xnor (_SD, rDest, vSource1, rSource2);
abe293a0 112631.Dest,26.Source2,21.0b110011001,12.0,11./,4.Source1::::xnor r
381f42ef 1127 do_xnor (_SD, rDest, rSource1, rSource2);
abe293a0 112831.Dest,26.Source2,21.0b110011001,12.1,11./::::xnor l
480e740c 1129 long_immediate (LongUnsignedImmediate);
381f42ef 1130 do_xnor (_SD, rDest, LongUnsignedImmediate, rSource2);
15c16493
AC		 1131
1132
1133// xor
381f42ef 1134void::function::do_xor:signed32 *rDest, signed32 Source1, signed32 Source2
7b167b09 1135 unsigned32 result = Source1 ^ Source2;
381f42ef 1136 TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
7b167b09 1137 *rDest = result;
480e740c 113831.Dest,26.Source2,21.0b0010110,14.UnsignedImmediate::::xor i
381f42ef 1139 do_xor (_SD, rDest, vSource1, rSource2);
480e740c 114031.Dest,26.Source2,21.0b110010110,13.0,12.0,11./,4.Source1::::xor r
381f42ef 1141 do_xor (_SD, rDest, rSource1, rSource2);
480e740c
AC		 114231.Dest,26.Source2,21.0b110010110,13.0,12.1,11./::::xor l
1143 long_immediate (LongUnsignedImmediate);
381f42ef 1144 do_xor (_SD, rDest, LongUnsignedImmediate, rSource2);
GDB Binutils - Deliverables
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