Commit | Line | Data |
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3971886a AC |
1 | // Texas Instruments TMS320C80 (MVP) Simulator. |
2 | // Copyright (C) 1997 Free Software Foundation, Inc. | |
3 | // Contributed by Cygnus Support. | |
4 | // | |
5 | // This file is part of GDB, the GNU debugger. | |
6 | // | |
7 | // This program is free software; you can redistribute it and/or modify | |
8 | // it under the terms of the GNU General Public License as published by | |
9 | // the Free Software Foundation; either version 2, or (at your option) | |
10 | // any later version. | |
11 | // | |
12 | // This program is distributed in the hope that it will be useful, | |
13 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | // GNU General Public License for more details. | |
16 | // | |
17 | // You should have received a copy of the GNU General Public License along | |
18 | // with this program; if not, write to the Free Software Foundation, Inc., | |
19 | // 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
20 | ||
21 | ||
381f42ef | 22 | // The following is called when ever an illegal instruction is encountered. |
15c16493 | 23 | ::internal::illegal |
84902350 AC |
24 | engine_error (SD, CPU, cia, |
25 | "illegal instruction at 0x%lx", cia.ip); | |
381f42ef AC |
26 | // The following is called when ever an FP op is attempted with FPU disabled. |
27 | ::internal::fp_unavailable | |
84902350 AC |
28 | engine_error (SD, CPU, cia, |
29 | "floating-point unavailable at 0x%lx", cia.ip); | |
30 | ||
31 | // Handle a branch instruction | |
32 | instruction_address::function::do_branch:int annul, address_word target, int rLink_p, unsigned32 *rLink | |
33 | instruction_address nia; | |
34 | if (annul) | |
35 | { | |
36 | if (rLink_p) | |
37 | *rLink = cia.dp; | |
38 | nia.ip = target; | |
39 | nia.dp = target + 4; | |
40 | } | |
41 | else | |
42 | { | |
43 | if (rLink_p) | |
44 | *rLink = cia.dp + sizeof (instruction_word); | |
45 | nia.ip = cia.dp; | |
46 | nia.dp = target; | |
47 | } | |
48 | return nia; | |
15c16493 AC |
49 | |
50 | // Signed Integer Add - add source1, source2, dest | |
381f42ef | 51 | void::function::do_add:signed32 *rDest, signed32 Source1, signed32 Source2 |
15c16493 AC |
52 | ALU_BEGIN (Source1); |
53 | ALU_ADD (Source2); | |
54 | ALU_END (*rDest); | |
381f42ef | 55 | TRACE_ALU3 (MY_INDEX, *rDest, Source1, Source2); |
480e740c AC |
56 | /* FIXME - a signed add may cause an exception */ |
57 | 31.Dest,26.Source2,21.0b101100,15.0,14.SignedImmediate::::add i | |
381f42ef | 58 | do_add (_SD, rDest, vSource1, rSource2); |
15c16493 | 59 | 31.Dest,26.Source2,21.0b11101100,13.0,12.0,11./,4.Source1::::add r |
381f42ef | 60 | do_add (_SD, rDest, rSource1, rSource2); |
15c16493 | 61 | 31.Dest,26.Source2,21.0b11101100,13.0,12.1,11./::::add l |
abe293a0 | 62 | long_immediate (LongSignedImmediate); |
381f42ef | 63 | do_add (_SD, rDest, LongSignedImmediate, rSource2); |
15c16493 AC |
64 | |
65 | ||
66 | // Unsigned Integer Add - addu source1, source2, dest | |
381f42ef | 67 | void::function::do_addu:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2 |
7b167b09 | 68 | unsigned32 result = Source1 + Source2; |
381f42ef | 69 | TRACE_ALU3 (MY_INDEX, result, Source1, Source2); |
7b167b09 MM |
70 | *rDest = result; |
71 | ||
480e740c | 72 | 31.Dest,26.Source2,21.0b101100,15.1,14.SignedImmediate::::addu i |
381f42ef | 73 | do_addu (_SD, rDest, vSource1, rSource2); |
15c16493 | 74 | 31.Dest,26.Source2,21.0b11101100,13.1,12.0,11./,4.Source1::::addu r |
381f42ef | 75 | do_addu (_SD, rDest, rSource1, rSource2); |
15c16493 | 76 | 31.Dest,26.Source2,21.0b11101100,13.1,12.1,11./::::addu l |
480e740c | 77 | long_immediate (LongSignedImmediate); |
381f42ef | 78 | do_addu (_SD, rDest, LongSignedImmediate, rSource2); |
15c16493 AC |
79 | |
80 | ||
381f42ef | 81 | void::function::do_and:signed32 *rDest, signed32 Source1, signed32 Source2 |
7b167b09 | 82 | unsigned32 result = Source1 & Source2; |
381f42ef | 83 | TRACE_ALU3 (MY_INDEX, result, Source1, Source2); |
7b167b09 | 84 | *rDest = result; |
15c16493 AC |
85 | |
86 | ||
87 | // and, and.tt | |
20b2f9bc | 88 | 31.Dest,26.Source2,21.0b0010001,14.UnsignedImmediate::::and.tt i |
381f42ef | 89 | do_and (_SD, rDest, vSource1, rSource2); |
480e740c | 90 | 31.Dest,26.Source2,21.0b110010001,12.0,11./,4.Source1::::and.tt r |
381f42ef | 91 | do_and (_SD, rDest, rSource1, rSource2); |
480e740c AC |
92 | 31.Dest,26.Source2,21.0b110010001,12.1,11./::::and.tt l |
93 | long_immediate (LongSignedImmediate); | |
381f42ef | 94 | do_and (_SD, rDest, LongSignedImmediate, rSource2); |
15c16493 AC |
95 | |
96 | ||
97 | // and.ff | |
20b2f9bc | 98 | 31.Dest,26.Source2,21.0b0011000,14.UnsignedImmediate::::and.ff i |
381f42ef | 99 | do_and (_SD, rDest, ~vSource1, ~rSource2); |
480e740c | 100 | 31.Dest,26.Source2,21.0b110011000,12.0,11./,4.Source1::::and.ff r |
381f42ef | 101 | do_and (_SD, rDest, ~rSource1, ~rSource2); |
480e740c AC |
102 | 31.Dest,26.Source2,21.0b110011000,12.1,11./::::and.ff l |
103 | long_immediate (LongSignedImmediate); | |
381f42ef | 104 | do_and (_SD, rDest, ~LongSignedImmediate, ~rSource2); |
15c16493 AC |
105 | |
106 | ||
107 | // and.ft | |
20b2f9bc | 108 | 31.Dest,26.Source2,21.0b0010100,14.UnsignedImmediate::::and.ft i |
381f42ef | 109 | do_and (_SD, rDest, ~vSource1, rSource2); |
480e740c | 110 | 31.Dest,26.Source2,21.0b110010100,12.0,11./,4.Source1::::and.ft r |
381f42ef | 111 | do_and (_SD, rDest, ~rSource1, rSource2); |
480e740c AC |
112 | 31.Dest,26.Source2,21.0b110010100,12.1,11./::::and.ft l |
113 | long_immediate (LongSignedImmediate); | |
381f42ef | 114 | do_and (_SD, rDest, ~LongSignedImmediate, rSource2); |
15c16493 AC |
115 | |
116 | ||
117 | // and.tf | |
20b2f9bc | 118 | 31.Dest,26.Source2,21.0b0010010,14.UnsignedImmediate::::and.tf i |
381f42ef | 119 | do_and (_SD, rDest, vSource1, ~rSource2); |
480e740c | 120 | 31.Dest,26.Source2,21.0b110010010,12.0,11./,4.Source1::::and.tf r |
381f42ef | 121 | do_and (_SD, rDest, rSource1, ~rSource2); |
480e740c AC |
122 | 31.Dest,26.Source2,21.0b110010010,12.1,11./::::and.tf l |
123 | long_immediate (LongSignedImmediate); | |
381f42ef | 124 | do_and (_SD, rDest, LongSignedImmediate, ~rSource2); |
15c16493 AC |
125 | |
126 | ||
127 | // bbo.[a] | |
381f42ef | 128 | instruction_address::function::do_bbo:instruction_address nia, int bitnum, unsigned32 source, int annul, unsigned32 offset |
7b167b09 | 129 | int jump_p; |
84902350 | 130 | address_word target = cia.ip + 4 * offset; |
c3cad878 MM |
131 | bitnum = (~ bitnum) & 0x1f; |
132 | if (MASKED32 (source, bitnum, bitnum)) | |
480e740c | 133 | { |
84902350 | 134 | nia = do_branch (_SD, annul, target, 0, NULL); |
7b167b09 | 135 | jump_p = 1; |
480e740c | 136 | } |
7b167b09 MM |
137 | else |
138 | jump_p = 0; | |
381f42ef | 139 | TRACE_COND_BR(MY_INDEX, jump_p, bitnum, target); |
480e740c AC |
140 | return nia; |
141 | 31.BITNUM,26.Source,21.0b100101,15.A,14.SignedOffset::::bbo i | |
381f42ef | 142 | nia = do_bbo (_SD, nia, BITNUM, rSource, A, vSignedOffset); |
480e740c | 143 | 31.BITNUM,26.Source,21.0b11100101,13.A,12.0,11./,4.IndOff::::bbo r |
381f42ef | 144 | nia = do_bbo (_SD, nia, BITNUM, rSource, A, rIndOff); |
480e740c AC |
145 | 31.BITNUM,26.Source,21.0b11100101,13.A,12.1,11./::::bbo l |
146 | long_immediate (LongSignedImmediate); | |
381f42ef | 147 | nia = do_bbo (_SD, nia, BITNUM, rSource, A, LongSignedImmediate); |
15c16493 AC |
148 | |
149 | ||
150 | // bbz[.a] | |
381f42ef | 151 | instruction_address::function::do_bbz:instruction_address nia, int bitnum, unsigned32 source, int annul, unsigned32 offset |
7b167b09 | 152 | int jump_p; |
84902350 | 153 | address_word target = cia.ip + 4 * offset; |
c3cad878 MM |
154 | bitnum = (~ bitnum) & 0x1f; |
155 | if (!MASKED32 (source, bitnum, bitnum)) | |
15c16493 | 156 | { |
84902350 | 157 | nia = do_branch (_SD, annul, target, 0, NULL); |
7b167b09 | 158 | jump_p = 1; |
15c16493 | 159 | } |
7b167b09 MM |
160 | else |
161 | jump_p = 0; | |
381f42ef | 162 | TRACE_COND_BR(MY_INDEX, jump_p, bitnum, target); |
15c16493 | 163 | return nia; |
480e740c | 164 | 31.BITNUM,26.Source,21.0b100100,15.A,14.SignedOffset::::bbz i |
381f42ef | 165 | nia = do_bbz (_SD, nia, BITNUM, rSource, A, vSignedOffset); |
15c16493 | 166 | 31.BITNUM,26.Source,21.0b11100100,13.A,12.0,11./,4.IndOff::::bbz r |
381f42ef | 167 | nia = do_bbz (_SD, nia, BITNUM, rSource, A, rIndOff); |
15c16493 | 168 | 31.BITNUM,26.Source,21.0b11100100,13.A,12.1,11./::::bbz l |
480e740c | 169 | long_immediate (LongSignedImmediate); |
381f42ef | 170 | nia = do_bbz (_SD, nia, BITNUM, rSource, A, LongSignedImmediate); |
15c16493 AC |
171 | |
172 | ||
173 | // bcnd[.a] | |
381f42ef | 174 | instruction_address::function::do_bcnd:instruction_address nia, int Cond, unsigned32 source, int annul, unsigned32 offset |
480e740c AC |
175 | int condition; |
176 | int size = EXTRACTED32 (Cond, 31 - 27, 30 - 27); | |
177 | int code = EXTRACTED32 (Cond, 29 - 27, 27 - 27); | |
178 | signed32 val = 0; | |
84902350 | 179 | address_word target = cia.ip + 4 * offset; |
480e740c AC |
180 | switch (size) |
181 | { | |
182 | case 0: val = SEXT32 (source, 7); break; | |
183 | case 1: val = SEXT32 (source, 15); break; | |
184 | case 2: val = source; break; | |
abe293a0 | 185 | default: engine_error (SD, CPU, cia, "bcnd - reserved size"); |
480e740c AC |
186 | } |
187 | switch (code) | |
188 | { | |
189 | case 0: condition = 0; break; | |
190 | case 1: condition = val > 0; break; | |
191 | case 2: condition = val == 0; break; | |
192 | case 3: condition = val >= 0; break; | |
193 | case 4: condition = val < 0; break; | |
194 | case 5: condition = val != 0; break; | |
195 | case 6: condition = val <= 0; break; | |
196 | default: condition = 1; break; | |
197 | } | |
198 | if (condition) | |
199 | { | |
84902350 | 200 | nia = do_branch (_SD, annul, target, 0, NULL); |
480e740c | 201 | } |
381f42ef | 202 | TRACE_COND_BR(MY_INDEX, condition, source, target); |
480e740c AC |
203 | return nia; |
204 | 31.Code,26.Source,21.0b100110,15.A,14.SignedOffset::::bcnd i | |
381f42ef | 205 | nia = do_bcnd (_SD, nia, Code, rSource, A, vSignedOffset); |
480e740c | 206 | 31.Code,26.Source,21.0b11100110,13.A,12.0,11./,4.IndOff::::bcnd r |
381f42ef | 207 | nia = do_bcnd (_SD, nia, Code, rSource, A, rIndOff); |
480e740c AC |
208 | 31.Code,26.Source,21.0b11100110,13.A,12.1,11./::::bcnd l |
209 | long_immediate (LongSignedImmediate); | |
381f42ef | 210 | nia = do_bcnd (_SD, nia, Code, rSource, A, LongSignedImmediate); |
15c16493 AC |
211 | |
212 | ||
213 | // br[.a] - see bbz[.a] | |
214 | ||
215 | ||
216 | // brcr | |
381f42ef AC |
217 | sim_cia::function::do_brcr:instruction_address nia, int cr |
218 | if (cr >= 0x4000 || !(CPU)->is_user_mode) | |
219 | { | |
220 | unsigned32 control = CR (cr); | |
221 | unsigned32 ie = control & 0x00000001; | |
222 | unsigned32 pc = control & 0xfffffffc; | |
223 | unsigned32 is_user_mode = control & 0x00000002; | |
224 | (CPU)->is_user_mode = is_user_mode; | |
225 | nia.dp = pc; | |
226 | if (ie) | |
227 | (CPU)->cr[IE_CR] |= IE_CR_IE; | |
228 | else | |
229 | (CPU)->cr[IE_CR] &= ~IE_CR_IE; | |
230 | } | |
231 | TRACE_UCOND_BR (MY_INDEX, nia.dp); | |
232 | return nia; | |
233 | 31.//,27.0,26.//,21.0b0000110,14.UCRN::::brcr i | |
234 | nia = do_brcr (_SD, nia, UCRN); | |
235 | 31.//,27.0,26.//,21.0b110000110,12.0,11./,4.INDCR::::brcr r | |
236 | nia = do_brcr (_SD, nia, UCRN); | |
abe293a0 | 237 | 31.//,27.0,26.//,21.0b110000110,12.1,11./::::brcr l |
381f42ef AC |
238 | long_immediate (UnsignedControlRegisterNumber) |
239 | nia = do_brcr (_SD, nia, UnsignedControlRegisterNumber); | |
15c16493 AC |
240 | |
241 | ||
242 | // bsr[.a] | |
381f42ef | 243 | instruction_address::function::do_bsr:instruction_address nia, signed32 *rLink, int annul, unsigned32 offset |
84902350 AC |
244 | address_word target = cia.ip + 4 * offset; |
245 | nia = do_branch (_SD, annul, target, 1, rLink); | |
246 | TRACE_UCOND_BR (MY_INDEX, target); | |
480e740c AC |
247 | return nia; |
248 | 31.Link,26./,21.0b100000,15.A,14.SignedOffset::::bsr i | |
381f42ef | 249 | nia = do_bsr (_SD, nia, rLink, A, vSignedOffset); |
480e740c | 250 | 31.Link,26./,21.0b11100000,13.A,12.0,11./,4.IndOff::::bsr r |
381f42ef | 251 | nia = do_bsr (_SD, nia, rLink, A, rIndOff); |
480e740c AC |
252 | 31.Link,26./,21.0b11100000,13.A,12.1,11./::::bsr l |
253 | long_immediate (LongSignedImmediate); | |
381f42ef | 254 | nia = do_bsr (_SD, nia, rLink, A, LongSignedImmediate); |
15c16493 AC |
255 | |
256 | ||
257 | // cmnd | |
381f42ef | 258 | void::function::do_cmnd:signed32 source |
3971886a AC |
259 | int Reset = EXTRACTED32 (source, 31, 31); |
260 | int Halt = EXTRACTED32 (source, 30, 30); | |
261 | int Unhalt = EXTRACTED32 (source, 29, 29); | |
262 | /* int ICR = EXTRACTED32 (source, 28, 28); */ | |
263 | /* int DCR = EXTRACTED32 (source, 27, 27); */ | |
264 | int Task = EXTRACTED32 (source, 14, 14); | |
265 | int Msg = EXTRACTED32 (source, 13, 13); | |
266 | int VC = EXTRACTED32 (source, 10, 10); | |
267 | int TC = EXTRACTED32 (source, 9, 9); | |
268 | int MP = EXTRACTED32 (source, 8, 8); | |
269 | int PP = EXTRACTED32 (source, 3, 0); | |
270 | /* what is implemented? */ | |
271 | if (PP != 0) | |
272 | engine_error (SD, CPU, cia, "0x%lx: cmnd - PPs not supported", | |
273 | (unsigned long) cia.ip); | |
274 | if (VC != 0) | |
275 | engine_error (SD, CPU, cia, "0x%lx: cmnd - VC not supported", | |
276 | (unsigned long) cia.ip); | |
277 | if (TC != 0) | |
278 | engine_error (SD, CPU, cia, "0x%lx: cmnd - TC not supported", | |
279 | (unsigned long) cia.ip); | |
280 | if (MP) | |
281 | { | |
282 | if (Reset || Halt) | |
283 | engine_halt (SD, CPU, cia, sim_exited, 0); | |
284 | if (Unhalt) | |
285 | engine_error (SD, CPU, cia, "0x%lx: cmnd - Can not unhalt the MP", | |
286 | (unsigned long) cia.ip); | |
287 | /* if (ICR || DCR); */ | |
288 | if (Task) | |
289 | engine_error (SD, CPU, cia, "0x%lx: cmnd - Can not Task the MP", | |
290 | (unsigned long) cia.ip); | |
291 | if (Msg) | |
292 | engine_error (SD, CPU, cia, "0x%lx: cmnd - Msg to MP not suported", | |
293 | (unsigned long) cia.ip); | |
294 | } | |
381f42ef | 295 | TRACE_SINK1 (MY_INDEX, source); |
abe293a0 | 296 | 31./,21.0b0000010,14.UI::::cmnd i |
381f42ef | 297 | do_cmnd (_SD, UI); |
3971886a | 298 | 31./,21.0b110000010,12.0,11./,4.Source::::cmnd r |
381f42ef | 299 | do_cmnd (_SD, rSource); |
abe293a0 | 300 | 31./,21.0b110000010,12.1,11./::::cmnd l |
3971886a | 301 | long_immediate (LongUnsignedImmediate); |
381f42ef | 302 | do_cmnd (_SD, LongUnsignedImmediate); |
15c16493 AC |
303 | |
304 | // cmp | |
480e740c AC |
305 | unsigned32::function::cmp_vals:signed32 s1, unsigned32 u1, signed32 s2, unsigned32 u2 |
306 | unsigned32 field = 0; | |
aaa7b252 MM |
307 | if (s1 == s2) field |= 0x001; |
308 | if (s1 != s2) field |= 0x002; | |
309 | if (s1 > s2) field |= 0x004; | |
310 | if (s1 <= s2) field |= 0x008; | |
311 | if (s1 < s2) field |= 0x010; | |
312 | if (s1 >= s2) field |= 0x020; | |
313 | if (u1 > u2) field |= 0x040; | |
314 | if (u1 <= u2) field |= 0x080; | |
315 | if (u1 < u2) field |= 0x100; | |
316 | if (u1 >= u2) field |= 0x200; | |
480e740c | 317 | return field; |
381f42ef | 318 | void::function::do_cmp:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2 |
480e740c | 319 | unsigned32 field = 0; |
aaa7b252 MM |
320 | field |= cmp_vals (_SD, Source1, Source1, Source2, Source2) << 20; |
321 | field |= cmp_vals (_SD, (signed16)Source1, (unsigned16)Source1, | |
322 | (signed16)Source2, (unsigned16)Source2) << 10; | |
323 | field |= cmp_vals (_SD, (signed8)Source1, (unsigned8)Source1, | |
324 | (signed8)Source2, (unsigned8)Source2); | |
381f42ef | 325 | TRACE_ALU3 (MY_INDEX, field, Source1, Source2); |
480e740c AC |
326 | *rDest = field; |
327 | 31.Dest,26.Source2,21.0b1010000,14.SignedImmediate::::cmp i | |
381f42ef | 328 | do_cmp (_SD, rDest, vSource1, rSource2); |
480e740c | 329 | 31.Dest,26.Source2,21.0b111010000,12.0,11./,4.Source1::::cmp r |
381f42ef | 330 | do_cmp (_SD, rDest, rSource1, rSource2); |
480e740c AC |
331 | 31.Dest,26.Source2,21.0b111010000,12.1,11./::::cmp l |
332 | long_immediate (LongSignedImmediate); | |
381f42ef | 333 | do_cmp (_SD, rDest, LongSignedImmediate, rSource2); |
15c16493 AC |
334 | |
335 | ||
336 | // dcache | |
480e740c | 337 | 31./,27.F,26.Source2,21.0b0111,17.M,16.0b00,14.SignedOffset::::dcache i |
7b167b09 | 338 | TRACE_NOP (MY_INDEX); |
480e740c AC |
339 | /* NOP */ |
340 | 31./,27.F,26.Source2,21.0b110111,15.M,14.0b00,12.0,11./,4.Source1::::dcache r | |
7b167b09 | 341 | TRACE_NOP (MY_INDEX); |
480e740c AC |
342 | /* NOP */ |
343 | 31./,27.F,26.Source2,21.0b110111,15.M,14.0b00,12.1,11./::::dcache l | |
344 | long_immediate (LongSignedImmediate); | |
c1c77d40 | 345 | LongSignedImmediate++; |
7b167b09 | 346 | TRACE_NOP (MY_INDEX); |
480e740c | 347 | /* NOP */ |
15c16493 AC |
348 | |
349 | ||
350 | // dld[{.b|.h|.d}] | |
381f42ef AC |
351 | void::function::do_dld:int Dest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset |
352 | do_ld (_SD, Dest, Base, rBase, m, sz, S, Offset); | |
abe293a0 | 353 | 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dld r |
381f42ef | 354 | do_dld (_SD, Dest, rBase, &GPR(Base), m, sz, S, rIndOff); |
abe293a0 | 355 | 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.1,11.S,10.1,9./::::dld l |
d5e2c74e | 356 | long_immediate (LongSignedImmediateOffset); |
381f42ef | 357 | do_dld (_SD, Dest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset); |
15c16493 AC |
358 | |
359 | ||
360 | // dld.u[{.b|.h|.d}] | |
381f42ef AC |
361 | void::function::do_dld_u:unsigned32 *rDest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset |
362 | do_ld_u (_SD, rDest, Base, rBase, m, sz, S, Offset); | |
abe293a0 | 363 | 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dld.u r |
381f42ef | 364 | do_dld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, rIndOff); |
abe293a0 | 365 | 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.1,11.S,10.1,9./::::dld.u l |
d5e2c74e | 366 | long_immediate (LongSignedImmediateOffset); |
381f42ef | 367 | do_dld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset); |
15c16493 AC |
368 | |
369 | ||
370 | // dst[{.b|.h|.d}] | |
381f42ef AC |
371 | void::function::do_dst:int Source, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset |
372 | do_st (_SD, Source, Base, rBase, m, sz, S, Offset); | |
d5e2c74e | 373 | 31.Source,26.Base,21.0b110110,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dst r |
381f42ef | 374 | do_dst (_SD, Source, rBase, &GPR(Base), m, sz, S, rIndOff); |
d5e2c74e AC |
375 | 31.Source,26.Base,21.0b110110,15.m,14.sz,12.1,11.S,10.1,9./::::dst l |
376 | long_immediate (LongSignedImmediateOffset); | |
381f42ef | 377 | do_dst (_SD, Source, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset); |
15c16493 AC |
378 | |
379 | ||
380 | // estop | |
abe293a0 | 381 | 31./,21.0b1111111,14.1,13.0,12.0,11./::::estop |
15c16493 | 382 | |
15c16493 | 383 | // etrap |
abe293a0 AC |
384 | 31./,27.1,26./,21.0b0000001,14.UTN::::etrap i |
385 | 31./,27.1,26./,21.0b110000001,12.0,11./,4.iUTN::::etrap r | |
386 | 31./,27.1,26./,21.0b110000001,12.1,11./::::etrap l | |
15c16493 AC |
387 | |
388 | ||
389 | // exts - see shift.ds | |
390 | ||
391 | ||
392 | // extu - see shift.dz | |
393 | ||
394 | ||
3971886a AC |
395 | sim_fpu::function::get_fp_reg:int reg, unsigned32 val, int precision |
396 | switch (precision) | |
397 | { | |
398 | case 0: /* single */ | |
aa3a0447 | 399 | return sim_fpu_32to (val); |
3971886a AC |
400 | case 1: /* double */ |
401 | if (reg < 0) | |
aa3a0447 | 402 | engine_error (SD, CPU, cia, "DP immediate invalid"); |
3971886a AC |
403 | if (reg & 1) |
404 | engine_error (SD, CPU, cia, "DP FP register must be even"); | |
405 | if (reg <= 1) | |
406 | engine_error (SD, CPU, cia, "DP FP register must be >= 2"); | |
407 | return sim_fpu_64to (INSERTED64 (GPR(reg + 1), 63, 32) | |
408 | | INSERTED64 (GPR(reg), 31, 0)); | |
409 | case 2: /* 32 bit signed integer */ | |
aa3a0447 | 410 | return sim_fpu_i32to (val); |
3971886a | 411 | case 3: /* 32 bit unsigned integer */ |
aa3a0447 | 412 | return sim_fpu_u32to (val); |
3971886a AC |
413 | default: |
414 | engine_error (SD, CPU, cia, "Unsupported FP precision"); | |
415 | } | |
aa3a0447 | 416 | return sim_fpu_i32to (0); |
3971886a AC |
417 | void::function::set_fp_reg:int Dest, sim_fpu val, int PD |
418 | switch (PD) | |
419 | { | |
420 | case 0: /* single */ | |
421 | { | |
422 | GPR (Dest) = sim_fpu_to32 (val); | |
423 | break; | |
424 | } | |
425 | case 1: /* double */ | |
426 | { | |
aa3a0447 | 427 | unsigned64 v = sim_fpu_to64 (val); |
3971886a AC |
428 | if (Dest & 1) |
429 | engine_error (SD, CPU, cia, "DP FP Dest register must be even"); | |
430 | if (Dest <= 1) | |
431 | engine_error (SD, CPU, cia, "DP FP Dest register must be >= 2"); | |
aa3a0447 AC |
432 | GPR (Dest + 0) = VL4_8 (v); |
433 | GPR (Dest + 1) = VH4_8 (v); | |
3971886a AC |
434 | break; |
435 | } | |
436 | case 2: /* signed */ | |
07b4c0a6 AC |
437 | { |
438 | GPR (Dest) = sim_fpu_to32i (val); | |
439 | break; | |
440 | } | |
3971886a | 441 | case 3: /* unsigned */ |
07b4c0a6 AC |
442 | { |
443 | GPR (Dest) = sim_fpu_to32u (val); | |
444 | break; | |
445 | } | |
3971886a AC |
446 | default: |
447 | engine_error (SD, CPU, cia, "Unsupported FP precision"); | |
448 | } | |
449 | ||
15c16493 | 450 | // fadd.{s|d}{s|d}{s|d} |
3971886a AC |
451 | void::function::do_fadd:int Dest, int PD, sim_fpu s1, sim_fpu s2 |
452 | sim_fpu ans = sim_fpu_add (s1, s2); | |
381f42ef | 453 | TRACE_FPU3 (MY_INDEX, ans, s1, s2); |
3971886a | 454 | set_fp_reg (_SD, Dest, ans, PD); |
381f42ef | 455 | 31.Dest,26.Source2,21.0b111110000,12.0,11.r,10.PD,8.P2,6.P1,4.Source1::f::fadd r |
3971886a AC |
456 | do_fadd (_SD, Dest, PD, |
457 | get_fp_reg (_SD, Source1, rSource1, P1), | |
458 | get_fp_reg (_SD, Source2, rSource2, P2)); | |
381f42ef | 459 | 31.Dest,26.Source2,21.0b111110000,12.1,11.r,10.PD,8.P2,6.P1,4./::f::fadd l |
3971886a AC |
460 | long_immediate (SinglePrecisionFloatingPoint); |
461 | do_fadd (_SD, Dest, PD, | |
462 | get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1), | |
463 | get_fp_reg (_SD, Source2, rSource2, P2)); | |
15c16493 AC |
464 | |
465 | ||
466 | // fcmp.{s|d}{s|d}{s|d} | |
aa3a0447 AC |
467 | void::function::do_fcmp:int Dest, sim_fpu s1, sim_fpu s2 |
468 | unsigned32 result = 0; | |
3971886a | 469 | if (sim_fpu_is_nan (s1) || sim_fpu_is_nan (s2)) |
aa3a0447 | 470 | result |= BIT32 (30); |
3971886a AC |
471 | else |
472 | { | |
aa3a0447 AC |
473 | result |= BIT32 (31); |
474 | if (sim_fpu_is_eq (s1, s2)) result |= BIT32(20); | |
475 | if (sim_fpu_is_ne (s1, s2)) result |= BIT32(21); | |
476 | if (sim_fpu_is_gt (s1, s2)) result |= BIT32(22); | |
477 | if (sim_fpu_is_le (s1, s2)) result |= BIT32(23); | |
478 | if (sim_fpu_is_lt (s1, s2)) result |= BIT32(24); | |
479 | if (sim_fpu_is_ge (s1, s2)) result |= BIT32(25); | |
480 | if (sim_fpu_is_lt (s1, sim_fpu_i32to (0)) | |
481 | || sim_fpu_is_gt (s1, s2)) result |= BIT32(26); | |
482 | if (sim_fpu_is_lt (sim_fpu_i32to (0), s1) | |
483 | && sim_fpu_is_lt (s1, s2)) result |= BIT32(27); | |
484 | if (sim_fpu_is_le (sim_fpu_i32to (0), s1) | |
485 | && sim_fpu_is_le (s1, s2)) result |= BIT32(28); | |
486 | if (sim_fpu_is_le (s1, sim_fpu_i32to (0)) | |
487 | || sim_fpu_is_ge (s1, s2)) result |= BIT32(29); | |
3971886a | 488 | } |
aa3a0447 AC |
489 | GPR (Dest) = result; |
490 | TRACE_FPU2I (MY_INDEX, result, s1, s2); | |
381f42ef | 491 | 31.Dest,26.Source2,21.0b111110101,12.0,11./,10.0,8.P2,6.P1,4.Source1::f::fcmp r |
aa3a0447 | 492 | do_fcmp (_SD, Dest, |
3971886a AC |
493 | get_fp_reg (_SD, Source1, rSource1, P1), |
494 | get_fp_reg (_SD, Source2, rSource2, P2)); | |
381f42ef | 495 | 31.Dest,26.Source2,21.0b111110101,12.1,11./,10.0,8.P2,6.P1,4./::f::fcmp l |
3971886a | 496 | long_immediate (SinglePrecisionFloatingPoint); |
aa3a0447 | 497 | do_fcmp (_SD, Dest, |
3971886a AC |
498 | get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1), |
499 | get_fp_reg (_SD, Source2, rSource2, P2)); | |
500 | ||
15c16493 AC |
501 | |
502 | ||
503 | // fdiv.{s|d}{s|d}{s|d} | |
3971886a AC |
504 | void::function::do_fdiv:int Dest, int PD, sim_fpu s1, sim_fpu s2 |
505 | sim_fpu ans = sim_fpu_div (s1, s2); | |
381f42ef | 506 | TRACE_FPU3 (MY_INDEX, ans, s1, s2); |
3971886a | 507 | set_fp_reg (_SD, Dest, ans, PD); |
381f42ef | 508 | 31.Dest,26.Source2,21.0b111110011,12.0,11./,10.PD,8.P2,6.P1,4.Source1::f::fdiv r |
3971886a AC |
509 | do_fdiv (_SD, Dest, PD, |
510 | get_fp_reg (_SD, Source1, rSource1, P1), | |
511 | get_fp_reg (_SD, Source2, rSource2, P2)); | |
381f42ef | 512 | 31.Dest,26.Source2,21.0b111110011,12.1,11./,10.PD,8.P2,6.P1,4./::f::fdiv l |
3971886a AC |
513 | long_immediate (SinglePrecisionFloatingPoint); |
514 | do_fdiv (_SD, Dest, PD, | |
515 | get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1), | |
516 | get_fp_reg (_SD, Source2, rSource2, P2)); | |
15c16493 AC |
517 | |
518 | ||
519 | // fmpy.{s|d|i|u}{s|d|i|u}{s|d|i|u} | |
3971886a | 520 | void::function::do_fmpy:int Dest, int PD, sim_fpu s1, sim_fpu s2 |
07b4c0a6 AC |
521 | switch (PD) |
522 | { | |
523 | case 2: /* signed */ | |
524 | { | |
525 | GPR (Dest) = sim_fpu_to64i (s1) * sim_fpu_to64i (s2); | |
526 | TRACE_FPU2I (MY_INDEX, GPR (Dest), s1, s2); | |
527 | break; | |
528 | } | |
529 | case 3: /* unsigned */ | |
530 | { | |
531 | GPR (Dest) = sim_fpu_to64u (s1) * sim_fpu_to64u (s2); | |
532 | TRACE_FPU2I (MY_INDEX, GPR (Dest), s1, s2); | |
533 | break; | |
534 | } | |
535 | default: | |
536 | { | |
537 | sim_fpu ans = sim_fpu_mul (s1, s2); | |
538 | set_fp_reg (_SD, Dest, ans, PD); | |
539 | TRACE_FPU3 (MY_INDEX, ans, s1, s2); | |
540 | } | |
541 | } | |
381f42ef | 542 | 31.Dest,26.Source2,21.0b111110010,12.0,11./,10.PD,8.P2,6.P1,4.Source1::f::fmpy r |
3971886a AC |
543 | do_fmpy (_SD, Dest, PD, |
544 | get_fp_reg (_SD, Source1, rSource1, P1), | |
545 | get_fp_reg (_SD, Source2, rSource2, P2)); | |
381f42ef | 546 | 31.Dest,26.Source2,21.0b111110010,12.1,11./,10.PD,8.P2,6.P1,4./::f::fmpy l |
3971886a AC |
547 | long_immediate (SinglePrecisionFloatingPoint); |
548 | do_fmpy (_SD, Dest, PD, | |
549 | get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1), | |
550 | get_fp_reg (_SD, Source2, rSource2, P2)); | |
15c16493 AC |
551 | |
552 | ||
553 | // frndm.{s|d|i|u}{s|d|i|u}{s|d|i|u} | |
3971886a AC |
554 | void::function::do_frnd:int Dest, int PD, sim_fpu s1 |
555 | set_fp_reg (_SD, Dest, s1, PD); | |
aa3a0447 | 556 | TRACE_FPU1 (MY_INDEX, s1); |
381f42ef | 557 | 31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b11,6.P1,4.Source::f::frndm r |
3971886a AC |
558 | do_frnd (_SD, Dest, PD, |
559 | get_fp_reg (_SD, Source, rSource, P1)); | |
381f42ef | 560 | 31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b11,6.P1,4./::f::frndm l |
3971886a AC |
561 | long_immediate (SinglePrecisionFloatingPoint); |
562 | do_frnd (_SD, Dest, PD, | |
563 | get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1)); | |
15c16493 AC |
564 | |
565 | ||
566 | // frndn.{s|d|i|u}{s|d|i|u}{s|d|i|u} | |
381f42ef | 567 | 31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b00,6.P1,4.Source::f::frndn r |
3971886a AC |
568 | do_frnd (_SD, Dest, PD, |
569 | get_fp_reg (_SD, Source, rSource, P1)); | |
381f42ef | 570 | 31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b00,6.P1,4./::f::frndn l |
3971886a AC |
571 | long_immediate (SinglePrecisionFloatingPoint); |
572 | do_frnd (_SD, Dest, PD, | |
573 | get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1)); | |
15c16493 AC |
574 | |
575 | ||
576 | // frndp.{s|d|i|u}{s|d|i|u}{s|d|i|u} | |
381f42ef | 577 | 31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b10,6.P1,4.Source::f::frndp r |
3971886a AC |
578 | do_frnd (_SD, Dest, PD, |
579 | get_fp_reg (_SD, Source, rSource, P1)); | |
381f42ef | 580 | 31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b10,6.P1,4./::f::frndp l |
3971886a AC |
581 | long_immediate (SinglePrecisionFloatingPoint); |
582 | do_frnd (_SD, Dest, PD, | |
583 | get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1)); | |
15c16493 AC |
584 | |
585 | ||
586 | // frndz.{s|d|i|u}{s|d|i|u}{s|d|i|u} | |
381f42ef | 587 | 31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b01,6.P1,4.Source::f::frndz r |
3971886a AC |
588 | do_frnd (_SD, Dest, PD, |
589 | get_fp_reg (_SD, Source, rSource, P1)); | |
381f42ef | 590 | 31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b01,6.P1,4./::f::frndz l |
3971886a AC |
591 | long_immediate (SinglePrecisionFloatingPoint); |
592 | do_frnd (_SD, Dest, PD, | |
593 | get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1)); | |
15c16493 AC |
594 | |
595 | ||
596 | // fsqrt.{s|d}{s|d}{s|d} | |
480e740c | 597 | #void::function::do_fsqrt:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2 |
15c16493 | 598 | # sim_io_error ("fsqrt"); |
381f42ef | 599 | 31.Dest,26.Source2,21.0b111110111,12.0,11./,10.PD,8.//,6.P1,4.Source1::f::fsqrt r |
480e740c | 600 | # do_fsqrt (_SD, rDest, rSource1, rSource2); |
381f42ef | 601 | 31.Dest,26.Source2,21.0b111110111,12.1,11./,10.PD,8.//,6.P1,4./::f::fsqrt l |
480e740c | 602 | # do_fsqrt (_SD, rDest, LongSignedImmediate, rSource2); |
15c16493 AC |
603 | |
604 | ||
605 | // fsub.{s|d}{s|d}{s|d} | |
3971886a AC |
606 | void::function::do_fsub:int Dest, int PD, sim_fpu s1, sim_fpu s2 |
607 | sim_fpu ans = sim_fpu_sub (s1, s2); | |
381f42ef | 608 | TRACE_FPU3 (MY_INDEX, ans, s1, s2); |
3971886a | 609 | set_fp_reg (_SD, Dest, ans, PD); |
381f42ef | 610 | 31.Dest,26.Source2,21.0b111110001,12.0,11.r,10.PD,8.P2,6.P1,4.Source1::f::fsub r |
3971886a AC |
611 | do_fsub (_SD, Dest, PD, |
612 | get_fp_reg (_SD, Source1, rSource1, P1), | |
613 | get_fp_reg (_SD, Source2, rSource2, P2)); | |
381f42ef | 614 | 31.Dest,26.Source2,21.0b111110001,12.1,11.r,10.PD,8.P2,6.P1,4./::f::fsub l |
3971886a AC |
615 | long_immediate (SinglePrecisionFloatingPoint); |
616 | do_fsub (_SD, Dest, PD, | |
617 | get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1), | |
618 | get_fp_reg (_SD, Source2, rSource2, P2)); | |
15c16493 AC |
619 | |
620 | ||
621 | // illop | |
abe293a0 AC |
622 | 31./,21.0b0000000,14./::::illop |
623 | 31./,21.0b111111111,12./::::illop l | |
15c16493 AC |
624 | |
625 | ||
abe293a0 | 626 | // ins - see sl.im |
15c16493 AC |
627 | |
628 | ||
629 | // jsr[.a] | |
381f42ef | 630 | instruction_address::function::do_jsr:instruction_address nia, signed32 *rLink, int annul, unsigned32 offset, unsigned32 base |
84902350 AC |
631 | address_word target = offset + base; |
632 | TRACE_UCOND_BR (MY_INDEX, target); | |
633 | nia = do_branch (_SD, annul, target, 1, rLink); | |
d5e2c74e | 634 | if (nia.dp & 0x3) |
3971886a AC |
635 | engine_error (SD, CPU, cia, |
636 | "0x%lx: destination address 0x%lx misaligned", | |
637 | (unsigned long) cia.ip, | |
d5e2c74e | 638 | (unsigned long) nia.dp); |
480e740c AC |
639 | return nia; |
640 | 31.Link,26.Base,21.0b100010,15.A,14.SignedOffset::::jsr i | |
381f42ef | 641 | nia = do_jsr (_SD, nia, rLink, A, vSignedOffset, rBase); |
480e740c | 642 | 31.Link,26.Base,21.0b11100010,13.A,12.0,11./,4.Source1::::jsr r |
381f42ef | 643 | nia = do_jsr (_SD, nia, rLink, A, rSource1, rBase); |
480e740c AC |
644 | 31.Link,26.Base,21.0b11100010,13.A,12.1,11./::::jsr l |
645 | long_immediate (LongSignedImmediate); | |
381f42ef | 646 | nia = do_jsr (_SD, nia, rLink, A, LongSignedImmediate, rBase); |
15c16493 AC |
647 | |
648 | ||
649 | // ld[{.b.h.d}] | |
381f42ef | 650 | void::function::do_ld:int Dest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset |
abe293a0 AC |
651 | unsigned32 addr; |
652 | switch (sz) | |
653 | { | |
654 | case 0: | |
655 | addr = Base + (S ? (Offset << 0) : Offset); | |
d5e2c74e AC |
656 | if (m) |
657 | *rBase = addr; | |
658 | GPR(Dest) = MEM (signed, addr, 1); | |
abe293a0 AC |
659 | break; |
660 | case 1: | |
661 | addr = Base + (S ? (Offset << 1) : Offset); | |
d5e2c74e AC |
662 | if (m) |
663 | *rBase = addr; | |
664 | GPR(Dest) = MEM (signed, addr, 2); | |
abe293a0 AC |
665 | break; |
666 | case 2: | |
667 | addr = Base + (S ? (Offset << 2) : Offset); | |
d5e2c74e AC |
668 | if (m) |
669 | *rBase = addr; | |
670 | GPR(Dest) = MEM (signed, addr, 4); | |
abe293a0 AC |
671 | break; |
672 | case 3: | |
c445af5a AC |
673 | { |
674 | signed64 val; | |
675 | if (Dest & 0x1) | |
676 | engine_error (SD, CPU, cia, "0x%lx: ld.d to odd register %d", | |
677 | cia.ip, Dest); | |
678 | addr = Base + (S ? (Offset << 3) : Offset); | |
679 | if (m) | |
680 | *rBase = addr; | |
681 | val = MEM (signed, addr, 8); | |
682 | GPR(Dest + 1) = VH4_8 (val); | |
683 | GPR(Dest + 0) = VL4_8 (val); | |
684 | } | |
abe293a0 AC |
685 | break; |
686 | default: | |
687 | addr = -1; | |
688 | engine_error (SD, CPU, cia, "ld - invalid sz %d", sz); | |
689 | } | |
d01082ad | 690 | TRACE_LD (MY_INDEX, GPR(Dest), m, S, Base, Offset); |
abe293a0 | 691 | 31.Dest,26.Base,21.0b0100,17.m,16.sz,14.SignedOffset::::ld i |
381f42ef | 692 | do_ld (_SD, Dest, rBase, &GPR(Base), m, sz, 0, vSignedOffset); |
abe293a0 | 693 | 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::ld r |
381f42ef | 694 | do_ld (_SD, Dest, rBase, &GPR(Base), m, sz, S, rIndOff); |
abe293a0 AC |
695 | 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.1,11.S,10.0,9./::::ld l |
696 | long_immediate (LongSignedImmediateOffset); | |
381f42ef | 697 | do_ld (_SD, Dest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset); |
15c16493 AC |
698 | |
699 | ||
700 | // ld.u[{.b.h.d}] | |
381f42ef | 701 | void::function::do_ld_u:unsigned32 *rDest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset |
abe293a0 AC |
702 | unsigned32 addr; |
703 | switch (sz) | |
704 | { | |
705 | case 0: | |
706 | addr = Base + (S ? (Offset << 0) : Offset); | |
707 | *rDest = MEM (unsigned, addr, 1); | |
708 | break; | |
709 | case 1: | |
710 | addr = Base + (S ? (Offset << 1) : Offset); | |
711 | *rDest = MEM (unsigned, addr, 2); | |
712 | break; | |
713 | default: | |
714 | addr = -1; | |
715 | engine_error (SD, CPU, cia, "ld.u - invalid sz %d", sz); | |
716 | } | |
717 | if (m) | |
718 | *rBase = addr; | |
381f42ef | 719 | TRACE_LD (MY_INDEX, m, S, *rDest, Base, Offset); |
abe293a0 | 720 | 31.Dest,26.Base,21.0b0101,17.m,16.sz,14.SignedOffset::::ld.u i |
381f42ef | 721 | do_ld_u (_SD, rDest, rBase, &GPR(Base), m, sz, 0, vSignedOffset); |
abe293a0 | 722 | 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::ld.u r |
381f42ef | 723 | do_ld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, rIndOff); |
abe293a0 AC |
724 | 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.1,11.S,10.0,9./::::ld.u l |
725 | long_immediate (LongSignedImmediateOffset); | |
381f42ef | 726 | do_ld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset); |
15c16493 AC |
727 | |
728 | ||
729 | // lmo | |
450be234 | 730 | 31.Dest,26.Source,21.0b111111000,12.0,11./::::lmo |
381f42ef AC |
731 | int b; |
732 | for (b = 0; b < 32; b++) | |
733 | if (rSource & BIT32 (31 - b)) | |
734 | break; | |
735 | TRACE_ALU2 (MY_INDEX, b, rSource); | |
736 | *rDest = b; | |
737 | ||
15c16493 | 738 | |
abe293a0 | 739 | // nop - see rdcr 0, r0 |
15c16493 AC |
740 | |
741 | ||
381f42ef | 742 | void::function::do_or:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2 |
7b167b09 | 743 | unsigned32 result = Source1 | Source2; |
381f42ef | 744 | TRACE_ALU3 (MY_INDEX, result, Source1, Source2); |
7b167b09 | 745 | *rDest = result; |
15c16493 AC |
746 | |
747 | ||
748 | // or, or.tt | |
480e740c | 749 | 31.Dest,26.Source2,21.0b0010111,14.UnsignedImmediate::::or.tt i |
381f42ef | 750 | do_or (_SD, rDest, vSource1, rSource2); |
480e740c | 751 | 31.Dest,26.Source2,21.0b110010111,12.0,11./,4.Source1::::or.tt r |
381f42ef | 752 | do_or (_SD, rDest, rSource1, rSource2); |
480e740c AC |
753 | 31.Dest,26.Source2,21.0b110010111,12.1,11./::::or.tt l |
754 | long_immediate (LongUnsignedImmediate); | |
381f42ef | 755 | do_or (_SD, rDest, LongUnsignedImmediate, rSource2); |
15c16493 AC |
756 | |
757 | ||
758 | // or.ff | |
480e740c | 759 | 31.Dest,26.Source2,21.0b0011110,14.UnsignedImmediate::::or.ff i |
381f42ef | 760 | do_or (_SD, rDest, ~vSource1, ~rSource2); |
480e740c | 761 | 31.Dest,26.Source2,21.0b110011110,12.0,11./,4.Source1::::or.ff r |
381f42ef | 762 | do_or (_SD, rDest, ~rSource1, ~rSource2); |
480e740c AC |
763 | 31.Dest,26.Source2,21.0b110011110,12.1,11./::::or.ff l |
764 | long_immediate (LongUnsignedImmediate); | |
381f42ef | 765 | do_or (_SD, rDest, ~LongUnsignedImmediate, ~rSource2); |
15c16493 AC |
766 | |
767 | ||
768 | // or.ft | |
480e740c | 769 | 31.Dest,26.Source2,21.0b0011101,14.UnsignedImmediate::::or.ft i |
381f42ef | 770 | do_or (_SD, rDest, ~vSource1, rSource2); |
480e740c | 771 | 31.Dest,26.Source2,21.0b110011101,12.0,11./,4.Source1::::or.ft r |
381f42ef | 772 | do_or (_SD, rDest, ~rSource1, rSource2); |
480e740c AC |
773 | 31.Dest,26.Source2,21.0b110011101,12.1,11./::::or.ft l |
774 | long_immediate (LongUnsignedImmediate); | |
381f42ef | 775 | do_or (_SD, rDest, ~LongUnsignedImmediate, rSource2); |
15c16493 AC |
776 | |
777 | ||
778 | // or.tf | |
480e740c | 779 | 31.Dest,26.Source2,21.0b0011011,14.UnsignedImmediate::::or.tf i |
381f42ef | 780 | do_or (_SD, rDest, vSource1, ~rSource2); |
480e740c | 781 | 31.Dest,26.Source2,21.0b110011011,12.0,11./,4.Source1::::or.tf r |
381f42ef | 782 | do_or (_SD, rDest, rSource1, ~rSource2); |
480e740c AC |
783 | 31.Dest,26.Source2,21.0b110011011,12.1,11./::::or.tf l |
784 | long_immediate (LongUnsignedImmediate); | |
381f42ef | 785 | do_or (_SD, rDest, LongUnsignedImmediate, ~rSource2); |
15c16493 AC |
786 | |
787 | ||
788 | // rdcr | |
381f42ef AC |
789 | void::function::do_rdcr:unsigned32 Dest, int cr |
790 | TRACE_SINK2 (MY_INDEX, Dest, cr); | |
791 | GPR (Dest) = CR (cr); | |
abe293a0 | 792 | 31.Dest,26.0,21.0b0000100,14.UCRN::::rdcr i |
381f42ef | 793 | do_rdcr (_SD, Dest, UCRN); |
abe293a0 | 794 | 31.Dest,26.0,21.0b110000100,12.0,11./,4.INDCR::::rdcr r |
381f42ef | 795 | do_rdcr (_SD, Dest, UCRN); |
abe293a0 | 796 | 31.Dest,26.0,21.0b110000100,12.1,11./::::rdcr l |
d5e2c74e | 797 | long_immediate (UnsignedControlRegisterNumber); |
381f42ef | 798 | do_rdcr (_SD, Dest, UnsignedControlRegisterNumber); |
15c16493 AC |
799 | |
800 | ||
801 | // rmo | |
abe293a0 | 802 | 31.Dest,26.Source,21.0b111111001,12.0,11./::::rmo |
381f42ef AC |
803 | int b; |
804 | for (b = 0; b < 32; b++) | |
805 | if (rSource & BIT32 (b)) | |
806 | break; | |
807 | if (b < 32) | |
808 | b = 31 - b; | |
809 | TRACE_ALU2 (MY_INDEX, b, rSource); | |
810 | *rDest = b; | |
15c16493 AC |
811 | |
812 | ||
abe293a0 | 813 | // rotl - see sl.dz |
15c16493 AC |
814 | |
815 | ||
381f42ef | 816 | // rotr - see sl.dz |
15c16493 AC |
817 | |
818 | ||
abe293a0 | 819 | // shl - see sl.iz |
15c16493 AC |
820 | |
821 | ||
822 | // sl.{d|e|i}{m|s|z} | |
381f42ef | 823 | void::function::do_shift:int Dest, int Source, int Merge, int i, int n, int EndMask, int Rotate |
c1c77d40 | 824 | /* see 10-30 for a reasonable description */ |
7b167b09 | 825 | unsigned32 input = GPR (Source); |
c1c77d40 AC |
826 | unsigned32 rotated; |
827 | unsigned32 endmask; | |
828 | unsigned32 shiftmask; | |
829 | unsigned32 cm; | |
830 | int nRotate; | |
831 | /* rotate the source */ | |
832 | if (n) | |
833 | { | |
834 | rotated = ROTR32 (GPR (Source), Rotate); | |
835 | nRotate = (- Rotate) & 31; | |
836 | } | |
837 | else | |
838 | { | |
839 | rotated = ROTL32 (GPR (Source), Rotate); | |
840 | nRotate = Rotate; | |
841 | } | |
842 | /* form the end mask */ | |
843 | if (EndMask == 0) | |
450be234 | 844 | endmask = ~ (unsigned32)0; |
c1c77d40 AC |
845 | else |
846 | endmask = (1 << EndMask) - 1; | |
847 | if (i) | |
848 | endmask = ~endmask; | |
849 | /* form the shiftmask */ | |
850 | switch (Merge) | |
851 | { | |
852 | case 0: case 1: case 2: | |
450be234 | 853 | shiftmask = ~ (unsigned32)0; /* disabled */ |
c1c77d40 | 854 | break; |
07b4c0a6 AC |
855 | case 3: case 5: /* enabled - 0 -> 32 */ |
856 | if (nRotate == 0) | |
857 | shiftmask = ~ (unsigned32)0; | |
858 | else | |
859 | shiftmask = ((1 << nRotate) - 1); /* enabled - 0 -> 0 */ | |
860 | break; | |
861 | case 4: | |
862 | shiftmask = ((1 << nRotate) - 1); /* enabled - 0 -> 0 */ | |
c1c77d40 AC |
863 | break; |
864 | case 6: case 7: | |
450be234 | 865 | shiftmask = ~((1 << nRotate) - 1); /* inverted */ |
c1c77d40 AC |
866 | break; |
867 | default: | |
868 | engine_error (SD, CPU, cia, | |
869 | "0x%lx: Invalid merge (%d) for shift", | |
870 | cia.ip, Source); | |
871 | shiftmask = 0; | |
872 | } | |
873 | /* and the composite mask */ | |
874 | cm = shiftmask & endmask; | |
875 | /* and merge */ | |
876 | switch (Merge) | |
877 | { | |
450be234 | 878 | case 0: case 3: case 6: /* zero */ |
c1c77d40 AC |
879 | GPR (Dest) = rotated & cm; |
880 | break; | |
450be234 | 881 | case 1: case 4: case 7: /* merge */ |
c1c77d40 AC |
882 | GPR (Dest) = (rotated & cm) | (GPR (Dest) & ~cm); |
883 | break; | |
450be234 | 884 | case 2: case 5: /* sign */ |
c1c77d40 AC |
885 | { |
886 | int b; | |
887 | GPR (Dest) = rotated & cm; | |
888 | for (b = 1; b <= 31; b++) | |
889 | if (!MASKED32 (cm, b, b)) | |
890 | GPR (Dest) |= INSERTED32 (EXTRACTED32 (GPR (Dest), b - 1, b - 1), | |
891 | b, b); | |
892 | } | |
893 | break; | |
894 | default: | |
895 | engine_error (SD, CPU, cia, | |
896 | "0x%lx: Invalid merge (%d)", | |
897 | cia.ip, Source); | |
898 | ||
899 | } | |
450be234 | 900 | TRACE_SHIFT (MY_INDEX, GPR (Dest), input, i, n, Merge, EndMask, Rotate); |
c1c77d40 | 901 | 31.Dest,26.Source,21.0b0001,17.Merge,14./,11.i,10.n,9.EndMask,4.Rotate::::sl i |
381f42ef | 902 | do_shift (_SD, Dest, Source, Merge, i, n, EndMask, Rotate); |
c1c77d40 | 903 | 31.Dest,26.Source,21.0b110001,15.Merge,12.0,11.i,10.n,9.EndMask,4.RotReg::::sl r |
450be234 | 904 | do_shift (_SD, Dest, Source, Merge, i, n, EndMask, GPR (RotReg) & 31); |
15c16493 AC |
905 | |
906 | ||
381f42ef | 907 | // sli.{d|e|i}{m|s|z} - see shift |
15c16493 AC |
908 | |
909 | ||
381f42ef | 910 | // sr.{d|e|i}{m|s|z} - see shift |
15c16493 AC |
911 | |
912 | ||
381f42ef | 913 | // sra - see sr.es - see shift |
15c16493 AC |
914 | |
915 | ||
381f42ef | 916 | // sri.{d|e|i}{m|s|z} - see shift |
15c16493 AC |
917 | |
918 | ||
919 | // srl - see sr.ez | |
920 | ||
921 | ||
922 | // st[{.b|.h|.d}] | |
381f42ef | 923 | void::function::do_st:int Source, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset |
abe293a0 AC |
924 | unsigned32 addr; |
925 | switch (sz) | |
926 | { | |
927 | case 0: | |
928 | addr = Base + (S ? (Offset << 0) : Offset); | |
d5e2c74e | 929 | STORE (addr, 1, GPR(Source)); |
abe293a0 AC |
930 | break; |
931 | case 1: | |
932 | addr = Base + (S ? (Offset << 1) : Offset); | |
d5e2c74e | 933 | STORE (addr, 2, GPR(Source)); |
abe293a0 AC |
934 | break; |
935 | case 2: | |
936 | addr = Base + (S ? (Offset << 2) : Offset); | |
d5e2c74e | 937 | STORE (addr, 4, GPR(Source)); |
abe293a0 AC |
938 | break; |
939 | case 3: | |
c445af5a AC |
940 | { |
941 | signed64 val; | |
942 | if (Source & 0x1) | |
943 | engine_error (SD, CPU, cia, | |
944 | "0x%lx: st.d with odd source register %d", | |
945 | cia.ip, Source); | |
946 | addr = Base + (S ? (Offset << 3) : Offset); | |
947 | val = (V4_H8 (GPR(Source + 1)) | V4_L8 (GPR(Source))); | |
948 | STORE (addr, 8, val); | |
949 | } | |
abe293a0 AC |
950 | break; |
951 | default: | |
952 | addr = -1; | |
d5e2c74e | 953 | engine_error (SD, CPU, cia, "st - invalid sz %d", sz); |
abe293a0 AC |
954 | } |
955 | if (m) | |
956 | *rBase = addr; | |
d01082ad | 957 | TRACE_ST (MY_INDEX, Source, m, S, Base, Offset); |
abe293a0 | 958 | 31.Source,26.Base,21.0b0110,17.m,16.sz,14.SignedOffset::::st i |
381f42ef | 959 | do_st (_SD, Source, rBase, &GPR(Base), m, sz, 0, vSignedOffset); |
abe293a0 | 960 | 31.Source,26.Base,21.0b110110,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::st r |
381f42ef | 961 | do_st (_SD, Source, rBase, &GPR(Base), m, sz, S, rIndOff); |
abe293a0 AC |
962 | 31.Source,26.Base,21.0b110110,15.m,14.sz,12.1,11.S,10.0,9./::::st l |
963 | long_immediate (LongSignedImmediateOffset); | |
381f42ef | 964 | do_st (_SD, Source, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset); |
15c16493 AC |
965 | |
966 | ||
967 | // sub | |
381f42ef | 968 | void::function::do_sub:signed32 *rDest, signed32 Source1, signed32 Source2 |
abe293a0 AC |
969 | ALU_BEGIN (Source1); |
970 | ALU_SUB (Source2); | |
7b167b09 | 971 | ALU_END (*rDest); |
381f42ef | 972 | TRACE_ALU3 (MY_INDEX, *rDest, Source1, Source2); |
abe293a0 | 973 | 31.Dest,26.Source2,21.0b101101,15.0,14.SignedImmediate::::sub i |
381f42ef | 974 | do_sub (_SD, rDest, vSource1, rSource2); |
abe293a0 | 975 | 31.Dest,26.Source2,21.0b11101101,13.0,12.0,11./,4.Source1::::sub r |
381f42ef | 976 | do_sub (_SD, rDest, rSource1, rSource2); |
abe293a0 AC |
977 | 31.Dest,26.Source2,21.0b11101101,13.0,12.1,11./::::sub l |
978 | long_immediate (LongSignedImmediate); | |
381f42ef | 979 | do_sub (_SD, rDest, LongSignedImmediate, rSource2); |
15c16493 AC |
980 | |
981 | ||
982 | // subu | |
450be234 | 983 | void::function::do_subu:unsigned32 *rDest, unsigned32 Source1, signed32 Source2 |
7b167b09 | 984 | unsigned32 result = Source1 - Source2; |
381f42ef | 985 | TRACE_ALU3 (MY_INDEX, result, Source1, Source2); |
7b167b09 | 986 | *rDest = result; |
d5e2c74e | 987 | // NOTE - the book has 15.1 which conflicts with subu. |
450be234 | 988 | 31.Dest,26.Source2,21.0b101101,15.1,14.UnsignedImmediate::::subu i |
381f42ef | 989 | do_subu (_SD, rDest, vSource1, rSource2); |
abe293a0 | 990 | 31.Dest,26.Source2,21.0b11101101,13.1,12.0,11./,4.Source1::::subu r |
381f42ef | 991 | do_subu (_SD, rDest, rSource1, rSource2); |
abe293a0 AC |
992 | 31.Dest,26.Source2,21.0b11101101,13.1,12.1,11./::::subu l |
993 | long_immediate (LongSignedImmediate); | |
381f42ef | 994 | do_subu (_SD, rDest, LongSignedImmediate, rSource2); |
15c16493 AC |
995 | |
996 | ||
997 | // swcr | |
381f42ef AC |
998 | void::function::do_swcr:int Dest, signed32 rSource, signed32 cr |
999 | tic80_control_regs reg = tic80_index2cr (cr); | |
1000 | /* cache the old CR value */ | |
1001 | unsigned32 old_cr = CR (cr); | |
1002 | /* Handle the write if allowed */ | |
1003 | if (cr >= 0x4000 || !(CPU)->is_user_mode) | |
1004 | switch (reg) | |
1005 | { | |
1006 | case INTPEN_CR: | |
1007 | CR (cr) &= ~rSource; | |
1008 | break; | |
1009 | default: | |
1010 | CR (cr) = rSource; | |
1011 | break; | |
1012 | } | |
1013 | /* Finish off the read */ | |
1014 | GPR (Dest) = old_cr; | |
1015 | TRACE_SINK3 (MY_INDEX, rSource, cr, Dest); | |
1016 | 31.Dest,26.Source,21.0b000010,15.1,14.UCRN::::swcr i | |
1017 | do_swcr (_SD, Dest, rSource, UCRN); | |
abe293a0 | 1018 | 31.Dest,26.Source,21.0b11000010,13.1,12.0,11./,4.INDCR::::swcr r |
381f42ef | 1019 | do_swcr (_SD, Dest, rSource, UCRN); |
abe293a0 | 1020 | 31.Dest,26.Source,21.0b11000010,13.1,12.1,11./::::swcr l |
381f42ef AC |
1021 | long_immediate (LongUnsignedControlRegister); |
1022 | do_swcr (_SD, Dest, rSource, LongUnsignedControlRegister); | |
15c16493 AC |
1023 | |
1024 | ||
1025 | // trap | |
381f42ef | 1026 | void::function::do_trap:unsigned32 trap_number |
1b6f4dde | 1027 | int i; |
381f42ef | 1028 | TRACE_SINK1 (MY_INDEX, trap_number); |
d5e2c74e | 1029 | switch (trap_number) |
15c16493 | 1030 | { |
d5e2c74e AC |
1031 | case 72: |
1032 | switch (GPR(15)) | |
15c16493 AC |
1033 | { |
1034 | case 1: /* EXIT */ | |
1035 | { | |
d5e2c74e | 1036 | engine_halt (SD, CPU, cia, sim_exited, GPR(2)); |
15c16493 AC |
1037 | break; |
1038 | } | |
1039 | case 4: /* WRITE */ | |
1040 | { | |
1041 | int i; | |
3971886a AC |
1042 | if (GPR(2) == 1) |
1043 | for (i = 0; i < GPR(6); i++) | |
1044 | { | |
1045 | char c; | |
1046 | c = MEM (unsigned, GPR(4) + i, 1); | |
1047 | sim_io_write_stdout (SD, &c, 1); | |
1048 | } | |
1049 | else if (GPR(2) == 2) | |
1050 | for (i = 0; i < GPR(6); i++) | |
1051 | { | |
1052 | char c; | |
1053 | c = MEM (unsigned, GPR(4) + i, 1); | |
1054 | sim_io_write_stderr (SD, &c, 1); | |
1055 | } | |
1056 | else | |
c1c77d40 AC |
1057 | engine_error (SD, CPU, cia, |
1058 | "0x%lx: write to invalid fid %d", | |
1059 | (unsigned long) cia.ip, GPR(2)); | |
d5e2c74e | 1060 | GPR(2) = GPR(6); |
15c16493 AC |
1061 | break; |
1062 | } | |
1063 | default: | |
1b6f4dde MM |
1064 | /* For system calls which are defined, just return EINVAL instead of trapping */ |
1065 | if (GPR(15) <= 204) | |
1066 | { | |
1067 | GPR(2) = -22; /* -EINVAL */ | |
1068 | break; | |
1069 | } | |
c1c77d40 AC |
1070 | engine_error (SD, CPU, cia, |
1071 | "0x%lx: unknown syscall %d", | |
1072 | (unsigned long) cia.ip, GPR(15)); | |
15c16493 | 1073 | } |
d5e2c74e | 1074 | break; |
c1c77d40 AC |
1075 | case 73: |
1076 | engine_halt (SD, CPU, cia, sim_stopped, SIGTRAP); | |
1b6f4dde MM |
1077 | |
1078 | /* Add a few traps for now to print the register state */ | |
1079 | case 74: | |
1080 | case 75: | |
1081 | case 76: | |
1082 | case 77: | |
1083 | case 78: | |
1084 | case 79: | |
1085 | if (!TRACE_ALU_P (CPU)) | |
1086 | trace_one_insn (SD, CPU, cia.ip, 1, itable[MY_INDEX].file, | |
1087 | itable[MY_INDEX].line_nr, "trap", | |
2310e3c2 | 1088 | "Trap %ld", (long) trap_number); |
1b6f4dde MM |
1089 | |
1090 | for (i = 0; i < 32; i++) | |
1091 | sim_io_eprintf (SD, "%s0x%.8lx%s", ((i % 8) == 0) ? "\t" : " ", (long)GPR(i), | |
1092 | (((i+1) % 8) == 0) ? "\n" : ""); | |
1093 | sim_io_write_stderr (SD, "\n", 1); | |
1094 | break; | |
1095 | ||
d5e2c74e | 1096 | default: |
c1c77d40 AC |
1097 | engine_error (SD, CPU, cia, |
1098 | "0x%lx: unsupported trap %d", | |
1099 | (unsigned long) cia.ip, trap_number); | |
15c16493 AC |
1100 | } |
1101 | 31./,27.0,26./,21.0b0000001,14.UTN::::trap i | |
381f42ef | 1102 | do_trap (_SD, UTN); |
15c16493 | 1103 | 31./,27.0,26./,21.0b110000001,12.0,11./,4.INDTR::::trap r |
381f42ef | 1104 | do_trap (_SD, UTN); |
15c16493 AC |
1105 | 31./,27.0,26./,21.0b110000001,12.1,11./::::trap l |
1106 | long_immediate (UTN); | |
381f42ef | 1107 | do_trap (_SD, UTN); |
15c16493 AC |
1108 | |
1109 | ||
1110 | // vadd.{s|d}{s|d} | |
381f42ef AC |
1111 | 31.*,26.Dest,21.0b11110,16./,15.0b000,12.0,11./,10.*,9.*,7.PD,6.*,5.P1,4.Source::f::vadd r |
1112 | 31.*,26.Dest,21.0b11110,16./,15.0b000,12.1,11./,10.*,9.*,7.PD,6.*,5.P1,4.Source::f::vadd l | |
15c16493 AC |
1113 | |
1114 | ||
abe293a0 | 1115 | // vld{0|1}.{s|d} - see above - same instruction |
381f42ef | 1116 | #31.Dest,26.*,21.0b11110,16.*,10.1,9.S,8.*,6.p,7.******::f::vld |
15c16493 AC |
1117 | |
1118 | ||
1119 | // vmac.ss{s|d} | |
381f42ef AC |
1120 | #31.*, 26.Source2,21.0b11110,16.a0,15.0b110,12.0,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4.Source1::f::vmac.ss ra |
1121 | 31.Dest,26.Source2,21.0b11110,16.a0,15.0b110,12.0,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4.Source1::f::vmac.ss rr | |
1122 | #31.*, 26.Source2,21.0b11110,16.a0,15.0b110,12.1,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4./::f::vmac.ss ia | |
1123 | 31.Dest,26.Source2,21.0b11110,16.a0,15.0b110,12.1,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4./::f::vmac.ss ir | |
15c16493 AC |
1124 | |
1125 | ||
1126 | // vmpy.{s|d}{s|d} | |
381f42ef AC |
1127 | 31.*,26.Dest,21.0b11110,16./,15.0b010,12.0,11./,10.*,8.*,7.PD,6.*,5.P1,4.Source::f::vmpy r |
1128 | 31.*,26.Dest,21.0b11110,16./,15.0b010,12.1,11./,10.*,8.*,7.PD,6.*,5.P1,4./::f::vmpy l | |
15c16493 AC |
1129 | |
1130 | ||
1131 | // vmsc.ss{s|d} | |
381f42ef AC |
1132 | #31.*, 26.Source2,21.0b11110,16.a0,15.0b111,12.0,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4.Source1::f::vmsc.ss ra |
1133 | 31.Dest,26.Source2,21.0b11110,16.a0,15.0b111,12.0,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4.Source1::f::vmsc.ss rr | |
1134 | #31.*, 26.Source2,21.0b11110,16.a0,15.0b111,12.1,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4./::f::vmsc.ss ia | |
1135 | 31.Dest,26.Source2,21.0b11110,16.a0,15.0b111,12.1,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4./::f::vmsc.ss ir | |
15c16493 AC |
1136 | |
1137 | ||
1138 | // vmsub.{s|d}{s|d} | |
381f42ef AC |
1139 | 31.*,26.Dest,21.0b11110,16.a0,15.0b011,12.0,11.a1,10.*,8.Z,7.PD,6.*,5./,4.Source::f::vmsub r |
1140 | 31.*,26.Dest,21.0b11110,16.a0,15.0b011,12.1,11.a1,10.*,8.Z,7.PD,6.*,5./,4./::f::vmsub l | |
15c16493 AC |
1141 | |
1142 | ||
1143 | // vrnd.{s|d}{s|d} | |
381f42ef AC |
1144 | 31.*,26.Dest,21.0b11110,16.a0,15.0b100,12.0,11.a1,10.*,8.PD,6.*,5.P1,4.Source::f::vrnd f r |
1145 | 31.*,26.Dest,21.0b11110,16.a0,15.0b100,12.1,11.a1,10.*,8.PD,6.*,5.P1,4./::f::vrnd f l | |
15c16493 AC |
1146 | |
1147 | ||
1148 | // vrnd.{i|u}{s|d} | |
381f42ef AC |
1149 | 31.*,26.Dest,21.0b11110,16./,15.0b101,12.0,11./,10.*,8./,7.PD,6.*,5.P1,4.Source::f::vrnd i r |
1150 | 31.*,26.Dest,21.0b11110,16./,15.0b101,12.1,11./,10.*,8./,7.PD,6.*,5.P1,4./::f::vrnd i l | |
15c16493 AC |
1151 | |
1152 | ||
abe293a0 | 1153 | // vst.{s|d} - see above - same instruction |
381f42ef | 1154 | #31.Source,26.*,21.0b11110,16.*,10.0,9.S,8.*,6.1,5.*::f::vst |
15c16493 AC |
1155 | |
1156 | ||
1157 | // vsub.{i|u}{s|d} | |
381f42ef AC |
1158 | 31.*,26.Dest,21.0b11110,16./,15.0b001,12.0,11./,10.*,8./,7.PD,6.*,5.P1,4.Source::f::vsub r |
1159 | 31.*,26.Dest,21.0b11110,16./,15.0b001,12.1,11./,10.*,8./,7.PD,6.*,5.P1,4./::f::vsub l | |
15c16493 AC |
1160 | |
1161 | ||
abe293a0 | 1162 | // wrcr - see swcr, creg, source, r0 |
15c16493 AC |
1163 | |
1164 | ||
1165 | // xnor | |
381f42ef | 1166 | void::function::do_xnor:signed32 *rDest, signed32 Source1, signed32 Source2 |
7b167b09 | 1167 | unsigned32 result = ~ (Source1 ^ Source2); |
381f42ef | 1168 | TRACE_ALU3 (MY_INDEX, result, Source1, Source2); |
7b167b09 | 1169 | *rDest = result; |
abe293a0 | 1170 | 31.Dest,26.Source2,21.0b0011001,14.UnsignedImmediate::::xnor i |
381f42ef | 1171 | do_xnor (_SD, rDest, vSource1, rSource2); |
abe293a0 | 1172 | 31.Dest,26.Source2,21.0b110011001,12.0,11./,4.Source1::::xnor r |
381f42ef | 1173 | do_xnor (_SD, rDest, rSource1, rSource2); |
abe293a0 | 1174 | 31.Dest,26.Source2,21.0b110011001,12.1,11./::::xnor l |
480e740c | 1175 | long_immediate (LongUnsignedImmediate); |
381f42ef | 1176 | do_xnor (_SD, rDest, LongUnsignedImmediate, rSource2); |
15c16493 AC |
1177 | |
1178 | ||
1179 | // xor | |
381f42ef | 1180 | void::function::do_xor:signed32 *rDest, signed32 Source1, signed32 Source2 |
7b167b09 | 1181 | unsigned32 result = Source1 ^ Source2; |
381f42ef | 1182 | TRACE_ALU3 (MY_INDEX, result, Source1, Source2); |
7b167b09 | 1183 | *rDest = result; |
480e740c | 1184 | 31.Dest,26.Source2,21.0b0010110,14.UnsignedImmediate::::xor i |
381f42ef | 1185 | do_xor (_SD, rDest, vSource1, rSource2); |
89d1a478 | 1186 | 31.Dest,26.Source2,21.0b110010110,12.0,11./,4.Source1::::xor r |
381f42ef | 1187 | do_xor (_SD, rDest, rSource1, rSource2); |
89d1a478 | 1188 | 31.Dest,26.Source2,21.0b110010110,12.1,11./::::xor l |
480e740c | 1189 | long_immediate (LongUnsignedImmediate); |
381f42ef | 1190 | do_xor (_SD, rDest, LongUnsignedImmediate, rSource2); |