Extend xor-endian and per-cpu support in core module.
[deliverable/binutils-gdb.git] / sim / tic80 / sim-calls.c
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1/* This file is part of the program psim.
2
3 Copyright (C) 1994-1996, Andrew Cagney <cagney@highland.com.au>
4 Copyright (C) 1997, Free Software Foundation
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 */
21
22
23#include <signal.h> /* FIXME - should be machine dependant version */
24#include <stdarg.h>
25#include <ctype.h>
26
27#include "bfd.h"
28#include "sim-main.h"
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29#include "sim-utils.h"
30#include "sim-options.h"
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31
32#ifdef HAVE_STDLIB_H
33#include <stdlib.h>
34#endif
35
36#ifdef HAVE_STRING_H
37#include <string.h>
38#else
39#ifdef HAVE_STRINGS_H
40#include <strings.h>
41#endif
42#endif
43
44
45#define SIM_ADDR unsigned
46
47/* Structures used by the simulator, for gdb just have static structures */
48
49struct sim_state simulation = { 0 };
50
51
52SIM_DESC
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53sim_open (SIM_OPEN_KIND kind,
54 host_callback *callback,
55 char **argv)
15c16493 56{
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57 SIM_DESC sd = &simulation;
58 STATE_OPEN_KIND (sd) = kind;
59 STATE_MAGIC (sd) = SIM_MAGIC_NUMBER;
24aa2b57 60 STATE_CALLBACK (&simulation) = callback;
15c16493 61
2e61a3ad 62 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
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63 return 0;
64
65 /* getopt will print the error message so we just have to exit if this fails.
66 FIXME: Hmmm... in the case of gdb we need getopt to call
67 print_filtered. */
2e61a3ad 68 if (sim_parse_args (sd, argv) != SIM_RC_OK)
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69 {
70 /* Uninstall the modules to avoid memory leaks,
71 file descriptor leaks, etc. */
2e61a3ad 72 sim_module_uninstall (sd);
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73 return 0;
74 }
75
2e61a3ad 76 if (sim_post_argv_init (sd) != SIM_RC_OK)
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77 {
78 /* Uninstall the modules to avoid memory leaks,
79 file descriptor leaks, etc. */
2e61a3ad 80 sim_module_uninstall (sd);
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81 return 0;
82 }
15c16493 83
f03b093c 84 /* Initialize the main processor */
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85 memset (&STATE_CPU (sd, 0)->reg, 0, sizeof STATE_CPU (sd, 0)->reg);
86 memset (&STATE_CPU (sd, 0)->acc, 0, sizeof STATE_CPU (sd, 0)->acc);
87 memset (&STATE_CPU (sd, 0)->cr, 0, sizeof STATE_CPU (sd, 0)->cr);
88 STATE_CPU (sd, 0)->is_user_mode = 0;
89 memset (&STATE_CPU (sd, 0)->cia, 0, sizeof STATE_CPU (sd, 0)->cia);
90 CPU_STATE (STATE_CPU (sd, 0)) = sd;
91
92 /* establish the simulator configuration */
93 sim_config (sd, LITTLE_ENDIAN/*d30v always big endian*/);
15c16493 94
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95#define TIC80_MEM_START 0x2000000
96#define TIC80_MEM_SIZE 0x100000
97
15c16493 98 /* external memory */
2e61a3ad 99 sim_core_attach(sd,
7a418800 100 NULL,
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101 attach_raw_memory,
102 access_read_write_exec,
d5e2c74e 103 0, TIC80_MEM_START, TIC80_MEM_SIZE, NULL, NULL);
2e61a3ad 104 sim_core_attach(sd,
7a418800 105 NULL,
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106 attach_raw_memory,
107 access_read_write_exec,
108 0, 0, TIC80_MEM_SIZE, NULL, NULL);
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109
110 /* FIXME: for now */
2e61a3ad 111 return sd;
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112}
113
114
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115void
116sim_close (SIM_DESC sd, int quitting)
117{
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118 /* Uninstall the modules to avoid memory leaks,
119 file descriptor leaks, etc. */
2e61a3ad 120 sim_module_uninstall (sd);
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121}
122
123
124SIM_RC
125sim_load (SIM_DESC sd, char *prog, bfd *abfd, int from_tty)
126{
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127 bfd *prog_bfd;
128
129 prog_bfd = sim_load_file (sd, STATE_MY_NAME (sd),
130 STATE_CALLBACK (sd),
131 prog,
132 /* pass NULL for abfd, we always open our own */
133 NULL,
134 STATE_OPEN_KIND (sd) == SIM_OPEN_DEBUG);
135 if (prog_bfd == NULL)
136 return SIM_RC_FAIL;
137 sim_analyze_program (sd, prog_bfd);
138 return SIM_RC_OK;
139}
140
141
142void
143sim_kill (SIM_DESC sd)
144{
145}
146
147
148int
149sim_read (SIM_DESC sd, SIM_ADDR mem, unsigned char *buf, int length)
150{
2f2e6c5d 151 return sim_core_read_buffer (sd, NULL, sim_core_write_map,
abe293a0 152 buf, mem, length);
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153}
154
155
156int
157sim_write (SIM_DESC sd, SIM_ADDR mem, unsigned char *buf, int length)
158{
2f2e6c5d 159 return sim_core_write_buffer (sd, NULL, sim_core_write_map,
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160 buf, mem, length);
161}
162
163
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164/* FIXME - these magic numbers need to be moved elsewhere */
165
166#define SP_REGNUM 1 /* Contains address of top of stack */
167#define FP_REGNUM 31 /* Contains address of executing stack frame */
168#define PC_REGNUM 32 /* Contains program counter (FIXME?) */
169#define NPC_REGNUM 33 /* Contains the next program counter (FIXME?) */
170#define A0_REGNUM 34 /* Accumulator register 0 */
171#define A3_REGNUM 37 /* Accumulator register 1 */
172
173#define R0_REGNUM 0 /* General Purpose Register 0 - for sim */
174#define Rn_REGNUM 31 /* Last General Purpose Register - for sim */
175#define An_REGNUM A3_REGNUM /* Last Accumulator register - for sim */
176
15c16493 177void
abe293a0 178sim_fetch_register (SIM_DESC sd, int regnr, unsigned char *buf)
15c16493 179{
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180 if (regnr == R0_REGNUM)
181 memset (buf, 0, sizeof (unsigned32));
182 else if (regnr > R0_REGNUM && regnr <= Rn_REGNUM)
c445af5a 183 *(unsigned32*)buf = H2T_4 (STATE_CPU (sd, 0)->reg[regnr - R0_REGNUM]);
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184 else if (regnr == PC_REGNUM)
185 *(unsigned32*)buf = H2T_4 (STATE_CPU (sd, 0)->cia.ip);
186 else if (regnr == NPC_REGNUM)
187 *(unsigned32*)buf = H2T_4 (STATE_CPU (sd, 0)->cia.dp);
188 else if (regnr >= A0_REGNUM && regnr <= An_REGNUM)
189 *(unsigned64*)buf = H2T_8 (STATE_CPU (sd, 0)->acc[regnr - A0_REGNUM]);
190 else
191 sim_io_error (sd, "sim_fetch_register - unknown register nr %d", regnr);
192 return;
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193}
194
195
196void
abe293a0 197sim_store_register (SIM_DESC sd, int regnr, unsigned char *buf)
15c16493 198{
abe293a0 199 if (regnr >= R0_REGNUM && regnr <= Rn_REGNUM)
c445af5a 200 STATE_CPU (sd, 0)->reg[regnr - R0_REGNUM] = T2H_4 (*(unsigned32*)buf);
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201 else if (regnr == PC_REGNUM)
202 STATE_CPU (sd, 0)->cia.ip = T2H_4 (*(unsigned32*)buf);
203 else if (regnr == NPC_REGNUM)
204 STATE_CPU (sd, 0)->cia.dp = T2H_4 (*(unsigned32*)buf);
205 else if (regnr == A0_REGNUM && regnr <= An_REGNUM)
43c53e07 206 STATE_CPU (sd, 0)->acc[regnr - A0_REGNUM] = T2H_8 (*(unsigned64*)buf);
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207 else
208 sim_io_error (sd, "sim_fetch_register - unknown register nr %d", regnr);
209 return;
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210}
211
212
213void
214sim_info (SIM_DESC sd, int verbose)
215{
216}
217
218
219SIM_RC
220sim_create_inferior (SIM_DESC sd,
221 char **argv,
222 char **envp)
223{
224 STATE_CPU (sd, 0)->cia.ip = STATE_START_ADDR(sd);
225 STATE_CPU (sd, 0)->cia.dp = (STATE_START_ADDR(sd)
226 + sizeof (instruction_word));
381f42ef 227 STATE_CPU (sd, 0)->cr[IE_CR] |= IE_CR_IE;
d5e2c74e 228 STATE_CPU (sd, 0)->reg[1] = TIC80_MEM_START + TIC80_MEM_SIZE - 16;
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229 return SIM_RC_OK;
230}
231
232
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233void
234sim_do_command (SIM_DESC sd, char *cmd)
235{
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236 if (sim_args_command (sd, cmd) != SIM_RC_OK)
237 sim_io_eprintf (sd, "Unknown command `%s'\n", cmd);
15c16493 238}
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