Commit | Line | Data |
---|---|---|
6c29acca AC |
1 | cache:Dest:Dest: |
2 | cache:Dest:rDest:signed_word *:(&(CPU)->reg[Dest]) | |
3 | # | |
4 | cache:Source1:Source1: | |
5 | cache:Source1:vSource1:signed_word:(GPR (Source1) + 0) | |
6 | #cache:Source1:vSource1:signed_word:(Source1 == 0 ? 0 : (CPU)->reg[Source1]) | |
7 | # | |
8 | cache:Source2:Source2: | |
9 | cache:Source2:vSource2:signed_word:(GPR (Source2) + 0) | |
10 | #cache:Source2:vSource2:signed_word:(Source2 == 0 ? 0 : (CPU)->reg[Source2]) | |
11 | # | |
12 | cache:Source:Source: | |
13 | cache:Source:vSource:signed_word:(GPR (Source) + 0) | |
14 | #cache:Source:vSource:signed_word:(Source == 0 ? 0 : (CPU)->reg[Source]) | |
15 | # | |
16 | cache:IndOff:IndOff: | |
17 | cache:IndOff:rIndOff:signed_word:(GPR (IndOff) + 0) | |
18 | #cache:IndOff:rIndOff:signed_word:(IndOff == 0 ? 0 : (CPU)->reg[IndOff]) | |
19 | # | |
20 | cache:Base:Base: | |
21 | cache:Base:vBase:signed_word:(GPR (Base) + 0) | |
22 | cache:Base:rBase:signed_word*:(&GPR (Base)) | |
23 | #cache:Base:vBase:signed_word:(Base == 0 ? 0 : (CPU)->reg[Base]) | |
24 | # | |
25 | cache:Link:Link: | |
26 | cache:Link:rLink:signed_word*:(&(CPU)->reg[Link]) | |
27 | # | |
28 | # Trap Number | |
29 | cache:UTN:UTN: | |
30 | cache:INDTR:INDTR: | |
31 | cache:INDTR:UTN:unsigned_word:(INDTR == 0 ? 0 : (CPU)->reg[INDTR]) | |
32 | # | |
33 | cache:A:A: | |
34 | # | |
35 | cache:SignedImmediate:SignedImmediate: | |
36 | cache:SignedImmediate:vSource1:signed_word:SEXT (SignedImmediate, 14) | |
37 | # | |
38 | cache:UnsignedImmediate:UnsignedImmediate: | |
39 | cache:UnsignedImmediate:vSource1:signed_word:UnsignedImmediate | |
40 | # | |
41 | cache:BITNUM:BITNUM: | |
42 | cache:Code:Code: | |
43 | cache:BITNUM:bitnum:int:(~BITNUM) & 0x1f | |
44 | ||
45 | # | |
46 | cache:SignedOffset:SignedOffset: | |
47 | cache:SignedOffset:vSignedOffset:signed_word:SEXT (SignedOffset, 14) | |
48 | # | |
49 | cache:UCRN:UCRN: | |
50 | cache:INDCR:INDCR: | |
51 | cache:INDCR:UCRN:unsigned32:(GPR (INDCR) + 0) | |
52 | #cache:INDCR:UCRN:unsigned32:(INDCR == 0 ? 0 : (CPU)->reg[INDCR]) |