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1e1e3b61 IC |
1 | /*> interp.c <*/ |
2 | /* Simulator for the MIPS architecture. | |
3 | ||
4 | This file is part of the MIPS sim | |
5 | ||
6 | THIS SOFTWARE IS NOT COPYRIGHTED | |
7 | ||
8 | Cygnus offers the following for use in the public domain. Cygnus | |
9 | makes no warranty with regard to the software or it's performance | |
10 | and the user accepts the software "AS IS" with all faults. | |
11 | ||
12 | CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO | |
13 | THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
14 | MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. | |
15 | ||
16 | $Revision$ | |
17 | $Author$ | |
18 | $Date$ | |
19 | ||
20 | NOTEs: | |
21 | ||
22 | The IDT monitor (found on the VR4300 board), seems to lie about | |
23 | register contents. It seems to treat the registers as sign-extended | |
24 | 32-bit values. This cause *REAL* problems when single-stepping 64-bit | |
25 | code on the hardware. | |
26 | ||
27 | */ | |
28 | ||
29 | /* The TRACE manifests enable the provision of extra features. If they | |
30 | are not defined then a simpler (quicker) simulator is constructed | |
31 | without the required run-time checks, etc. */ | |
32 | #if 1 /* 0 to allow user build selection, 1 to force inclusion */ | |
33 | #define TRACE (1) | |
34 | #endif | |
35 | ||
36 | #include "bfd.h" | |
37 | #include "sim-main.h" | |
38 | #include "sim-utils.h" | |
39 | #include "sim-options.h" | |
40 | #include "sim-assert.h" | |
41 | ||
42 | #include "config.h" | |
43 | ||
44 | #include <stdio.h> | |
45 | #include <stdarg.h> | |
46 | #include <ansidecl.h> | |
47 | #include <ctype.h> | |
48 | #include <limits.h> | |
49 | #include <math.h> | |
50 | #ifdef HAVE_STDLIB_H | |
51 | #include <stdlib.h> | |
52 | #endif | |
53 | #ifdef HAVE_STRING_H | |
54 | #include <string.h> | |
55 | #else | |
56 | #ifdef HAVE_STRINGS_H | |
57 | #include <strings.h> | |
58 | #endif | |
59 | #endif | |
60 | ||
61 | #include "getopt.h" | |
62 | #include "libiberty.h" | |
63 | #include "bfd.h" | |
64 | #include "callback.h" /* GDB simulator callback interface */ | |
65 | #include "remote-sim.h" /* GDB simulator interface */ | |
66 | ||
67 | #include "sysdep.h" | |
68 | ||
69 | #ifndef PARAMS | |
70 | #define PARAMS(x) | |
71 | #endif | |
72 | ||
73 | #include "hardware.h" | |
74 | ||
75 | char* pr_addr PARAMS ((SIM_ADDR addr)); | |
76 | char* pr_uword64 PARAMS ((uword64 addr)); | |
77 | ||
78 | ||
79 | /* Get the simulator engine description, without including the code: */ | |
80 | #define SIM_MANIFESTS | |
81 | #include "oengine.c" | |
82 | #undef SIM_MANIFESTS | |
83 | ||
84 | ||
85 | /* The following reserved instruction value is used when a simulator | |
86 | trap is required. NOTE: Care must be taken, since this value may be | |
87 | used in later revisions of the MIPS ISA. */ | |
88 | #define RSVD_INSTRUCTION (0x00000005) | |
89 | #define RSVD_INSTRUCTION_MASK (0xFC00003F) | |
90 | ||
91 | #define RSVD_INSTRUCTION_ARG_SHIFT 6 | |
92 | #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF | |
93 | ||
94 | ||
95 | /* Bits in the Debug register */ | |
96 | #define Debug_DBD 0x80000000 /* Debug Branch Delay */ | |
97 | #define Debug_DM 0x40000000 /* Debug Mode */ | |
98 | #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */ | |
99 | ||
100 | ||
101 | ||
102 | ||
103 | ||
104 | /*---------------------------------------------------------------------------*/ | |
105 | /*-- GDB simulator interface ------------------------------------------------*/ | |
106 | /*---------------------------------------------------------------------------*/ | |
107 | ||
108 | static void ColdReset PARAMS((SIM_DESC sd)); | |
109 | ||
110 | /*---------------------------------------------------------------------------*/ | |
111 | ||
112 | ||
113 | ||
114 | #define DELAYSLOT() {\ | |
115 | if (STATE & simDELAYSLOT)\ | |
116 | sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\ | |
117 | STATE |= simDELAYSLOT;\ | |
118 | } | |
119 | ||
120 | #define JALDELAYSLOT() {\ | |
121 | DELAYSLOT ();\ | |
122 | STATE |= simJALDELAYSLOT;\ | |
123 | } | |
124 | ||
125 | #define NULLIFY() {\ | |
126 | STATE &= ~simDELAYSLOT;\ | |
127 | STATE |= simSKIPNEXT;\ | |
128 | } | |
129 | ||
130 | #define CANCELDELAYSLOT() {\ | |
131 | DSSTATE = 0;\ | |
132 | STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\ | |
133 | } | |
134 | ||
135 | #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0) | |
136 | #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0) | |
137 | ||
138 | #define K0BASE (0x80000000) | |
139 | #define K0SIZE (0x20000000) | |
140 | #define K1BASE (0xA0000000) | |
141 | #define K1SIZE (0x20000000) | |
142 | #define MONITOR_BASE (0xBFC00000) | |
143 | #define MONITOR_SIZE (1 << 11) | |
144 | #define MEM_SIZE (2 << 20) | |
145 | ||
146 | #if defined(TRACE) | |
147 | static char *tracefile = "trace.din"; /* default filename for trace log */ | |
148 | FILE *tracefh = NULL; | |
149 | static void open_trace PARAMS((SIM_DESC sd)); | |
150 | #endif /* TRACE */ | |
151 | ||
152 | #define OPTION_DINERO_TRACE 200 | |
153 | #define OPTION_DINERO_FILE 201 | |
154 | ||
155 | static SIM_RC | |
156 | mips_option_handler (sd, opt, arg) | |
157 | SIM_DESC sd; | |
158 | int opt; | |
159 | char *arg; | |
160 | { | |
161 | switch (opt) | |
162 | { | |
163 | case OPTION_DINERO_TRACE: /* ??? */ | |
164 | #if defined(TRACE) | |
165 | /* Eventually the simTRACE flag could be treated as a toggle, to | |
166 | allow external control of the program points being traced | |
167 | (i.e. only from main onwards, excluding the run-time setup, | |
168 | etc.). */ | |
169 | if (arg == NULL) | |
170 | STATE |= simTRACE; | |
171 | else if (strcmp (arg, "yes") == 0) | |
172 | STATE |= simTRACE; | |
173 | else if (strcmp (arg, "no") == 0) | |
174 | STATE &= ~simTRACE; | |
175 | else if (strcmp (arg, "on") == 0) | |
176 | STATE |= simTRACE; | |
177 | else if (strcmp (arg, "off") == 0) | |
178 | STATE &= ~simTRACE; | |
179 | else | |
180 | { | |
181 | fprintf (stderr, "Unreconized dinero-trace option `%s'\n", arg); | |
182 | return SIM_RC_FAIL; | |
183 | } | |
184 | return SIM_RC_OK; | |
185 | #else /* !TRACE */ | |
186 | fprintf(stderr,"\ | |
187 | Simulator constructed without dinero tracing support (for performance).\n\ | |
188 | Re-compile simulator with \"-DTRACE\" to enable this option.\n"); | |
189 | return SIM_RC_FAIL; | |
190 | #endif /* !TRACE */ | |
191 | ||
192 | case OPTION_DINERO_FILE: | |
193 | #if defined(TRACE) | |
194 | if (optarg != NULL) { | |
195 | char *tmp; | |
196 | tmp = (char *)malloc(strlen(optarg) + 1); | |
197 | if (tmp == NULL) | |
198 | { | |
199 | sim_io_printf(sd,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg); | |
200 | return SIM_RC_FAIL; | |
201 | } | |
202 | else { | |
203 | strcpy(tmp,optarg); | |
204 | tracefile = tmp; | |
205 | sim_io_printf(sd,"Placing trace information into file \"%s\"\n",tracefile); | |
206 | } | |
207 | } | |
208 | #endif /* TRACE */ | |
209 | return SIM_RC_OK; | |
210 | ||
211 | } | |
212 | ||
213 | return SIM_RC_OK; | |
214 | } | |
215 | ||
216 | static const OPTION mips_options[] = | |
217 | { | |
218 | { {"dinero-trace", optional_argument, NULL, OPTION_DINERO_TRACE}, | |
219 | '\0', "on|off", "Enable dinero tracing", | |
220 | mips_option_handler }, | |
221 | { {"dinero-file", required_argument, NULL, OPTION_DINERO_FILE}, | |
222 | '\0', "FILE", "Write dinero trace to FILE", | |
223 | mips_option_handler }, | |
224 | { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL } | |
225 | }; | |
226 | ||
227 | ||
228 | int interrupt_pending; | |
229 | ||
230 | static void | |
231 | interrupt_event (SIM_DESC sd, void *data) | |
232 | { | |
233 | if (SR & status_IE) | |
234 | { | |
235 | interrupt_pending = 0; | |
236 | SignalExceptionInterrupt (); | |
237 | } | |
238 | else if (!interrupt_pending) | |
239 | sim_events_schedule (sd, 1, interrupt_event, data); | |
240 | } | |
241 | ||
242 | extern device gpuif_device; | |
243 | ||
244 | /*---------------------------------------------------------------------------*/ | |
245 | /*-- GDB simulator interface ------------------------------------------------*/ | |
246 | /*---------------------------------------------------------------------------*/ | |
247 | ||
248 | SIM_DESC | |
249 | sim_open (kind, cb, abfd, argv) | |
250 | SIM_OPEN_KIND kind; | |
251 | host_callback *cb; | |
252 | struct _bfd *abfd; | |
253 | char **argv; | |
254 | { | |
255 | SIM_DESC sd = sim_state_alloc (kind, cb); | |
256 | sim_cpu *cpu = STATE_CPU (sd, 0); | |
257 | ||
258 | SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); | |
259 | ||
260 | /* FIXME: watchpoints code shouldn't need this */ | |
261 | STATE_WATCHPOINTS (sd)->pc = &(PC); | |
262 | STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC); | |
263 | STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event; | |
264 | ||
265 | STATE = 0; | |
266 | ||
267 | if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) | |
268 | return 0; | |
269 | sim_add_option_table (sd, mips_options); | |
270 | ||
271 | /* Allocate core managed memory */ | |
272 | ||
273 | /* the monitor */ | |
274 | sim_do_commandf (sd, "memory region 0x%lx,0x%lx", MONITOR_BASE, MONITOR_SIZE); | |
275 | /* For compatibility with the old code - under this (at level one) | |
276 | are the kernel spaces K0 & K1. Both of these map to a single | |
277 | smaller sub region */ | |
278 | sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x", | |
279 | K1BASE, K0SIZE, | |
280 | MEM_SIZE, /* actual size */ | |
281 | K0BASE); | |
282 | ||
283 | register_devices(sd); | |
284 | ||
285 | /* getopt will print the error message so we just have to exit if this fails. | |
286 | FIXME: Hmmm... in the case of gdb we need getopt to call | |
287 | print_filtered. */ | |
288 | if (sim_parse_args (sd, argv) != SIM_RC_OK) | |
289 | { | |
290 | /* Uninstall the modules to avoid memory leaks, | |
291 | file descriptor leaks, etc. */ | |
292 | sim_module_uninstall (sd); | |
293 | return 0; | |
294 | } | |
295 | ||
296 | /* check for/establish the a reference program image */ | |
297 | if (sim_analyze_program (sd, | |
298 | (STATE_PROG_ARGV (sd) != NULL | |
299 | ? *STATE_PROG_ARGV (sd) | |
300 | : NULL), | |
301 | abfd) != SIM_RC_OK) | |
302 | { | |
303 | sim_module_uninstall (sd); | |
304 | return 0; | |
305 | } | |
306 | ||
307 | /* Configure/verify the target byte order and other runtime | |
308 | configuration options */ | |
309 | if (sim_config (sd) != SIM_RC_OK) | |
310 | { | |
311 | sim_module_uninstall (sd); | |
312 | return 0; | |
313 | } | |
314 | ||
315 | if (sim_post_argv_init (sd) != SIM_RC_OK) | |
316 | { | |
317 | /* Uninstall the modules to avoid memory leaks, | |
318 | file descriptor leaks, etc. */ | |
319 | sim_module_uninstall (sd); | |
320 | return 0; | |
321 | } | |
322 | ||
323 | /* verify assumptions the simulator made about the host type system. | |
324 | This macro does not return if there is a problem */ | |
325 | SIM_ASSERT (sizeof(int) == (4 * sizeof(char))); | |
326 | SIM_ASSERT (sizeof(word64) == (8 * sizeof(char))); | |
327 | ||
328 | #if defined(HASFPU) | |
329 | /* Check that the host FPU conforms to IEEE 754-1985 for the SINGLE | |
330 | and DOUBLE binary formats. This is a bit nasty, requiring that we | |
331 | trust the explicit manifests held in the source: */ | |
332 | /* TODO: We need to cope with the simulated target and the host not | |
333 | having the same endianness. This will require the high and low | |
334 | words of a (double) to be swapped when converting between the | |
335 | host and the simulated target. */ | |
336 | { | |
337 | union { | |
338 | unsigned int i[2]; | |
339 | double d; | |
340 | float f[2]; | |
341 | } s; | |
342 | ||
343 | s.d = (double)523.2939453125; | |
344 | ||
345 | if ((s.i[0] == 0 && (s.f[1] != (float)4.01102924346923828125 | |
346 | || s.i[1] != 0x40805A5A)) | |
347 | || (s.i[1] == 0 && (s.f[0] != (float)4.01102924346923828125 | |
348 | || s.i[0] != 0x40805A5A))) | |
349 | { | |
350 | fprintf(stderr,"The host executing the simulator does not seem to have IEEE 754-1985 std FP\n"); | |
351 | return 0; | |
352 | } | |
353 | } | |
354 | #endif /* HASFPU */ | |
355 | ||
356 | /* This is NASTY, in that we are assuming the size of specific | |
357 | registers: */ | |
358 | { | |
359 | int rn; | |
360 | for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++) { | |
361 | if (rn < 32) | |
362 | cpu->register_widths[rn] = GPRLEN; | |
363 | else if ((rn >= FGRIDX) && (rn < (FGRIDX + 32))) | |
364 | cpu->register_widths[rn] = GPRLEN; | |
365 | else if ((rn >= 33) && (rn <= 37)) | |
366 | cpu->register_widths[rn] = GPRLEN; | |
367 | else if ((rn == SRIDX) || (rn == FCR0IDX) || (rn == FCR31IDX) || ((rn >= 72) && (rn <= 89))) | |
368 | cpu->register_widths[rn] = 32; | |
369 | else | |
370 | cpu->register_widths[rn] = 0; | |
371 | } | |
372 | /* start-sanitize-r5900 */ | |
373 | ||
374 | /* set the 5900 "upper" registers to 64 bits */ | |
375 | for( rn = LAST_EMBED_REGNUM+1; rn < NUM_REGS; rn++) | |
376 | cpu->register_widths[rn] = 64; | |
377 | /* end-sanitize-r5900 */ | |
378 | } | |
379 | ||
380 | #if defined(TRACE) | |
381 | if (STATE & simTRACE) | |
382 | open_trace(sd); | |
383 | #endif /* TRACE */ | |
384 | ||
385 | /* Write the monitor trap address handlers into the monitor (eeprom) | |
386 | address space. This can only be done once the target endianness | |
387 | has been determined. */ | |
388 | { | |
389 | unsigned loop; | |
390 | /* Entry into the IDT monitor is via fixed address vectors, and | |
391 | not using machine instructions. To avoid clashing with use of | |
392 | the MIPS TRAP system, we place our own (simulator specific) | |
393 | "undefined" instructions into the relevant vector slots. */ | |
394 | for (loop = 0; (loop < MONITOR_SIZE); loop += 4) | |
395 | { | |
396 | address_word vaddr = (MONITOR_BASE + loop); | |
397 | unsigned32 insn = (RSVD_INSTRUCTION | (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK) << RSVD_INSTRUCTION_ARG_SHIFT)); | |
398 | H2T (insn); | |
399 | sim_write (sd, vaddr, (char *)&insn, sizeof (insn)); | |
400 | } | |
401 | /* The PMON monitor uses the same address space, but rather than | |
402 | branching into it the address of a routine is loaded. We can | |
403 | cheat for the moment, and direct the PMON routine to IDT style | |
404 | instructions within the monitor space. This relies on the IDT | |
405 | monitor not using the locations from 0xBFC00500 onwards as its | |
406 | entry points.*/ | |
407 | for (loop = 0; (loop < 24); loop++) | |
408 | { | |
409 | address_word vaddr = (MONITOR_BASE + 0x500 + (loop * 4)); | |
410 | unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */ | |
411 | switch (loop) | |
412 | { | |
413 | case 0: /* read */ | |
414 | value = 7; | |
415 | break; | |
416 | case 1: /* write */ | |
417 | value = 8; | |
418 | break; | |
419 | case 2: /* open */ | |
420 | value = 6; | |
421 | break; | |
422 | case 3: /* close */ | |
423 | value = 10; | |
424 | break; | |
425 | case 5: /* printf */ | |
426 | value = ((0x500 - 16) / 8); /* not an IDT reason code */ | |
427 | break; | |
428 | case 8: /* cliexit */ | |
429 | value = 17; | |
430 | break; | |
431 | case 11: /* flush_cache */ | |
432 | value = 28; | |
433 | break; | |
434 | } | |
435 | /* FIXME - should monitor_base be SIM_ADDR?? */ | |
436 | value = ((unsigned int)MONITOR_BASE + (value * 8)); | |
437 | H2T (value); | |
438 | sim_write (sd, vaddr, (char *)&value, sizeof (value)); | |
439 | ||
440 | /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */ | |
441 | vaddr -= 0x300; | |
442 | sim_write (sd, vaddr, (char *)&value, sizeof (value)); | |
443 | } | |
444 | } | |
445 | ||
446 | return sd; | |
447 | } | |
448 | ||
449 | #if defined(TRACE) | |
450 | static void | |
451 | open_trace(sd) | |
452 | SIM_DESC sd; | |
453 | { | |
454 | tracefh = fopen(tracefile,"wb+"); | |
455 | if (tracefh == NULL) | |
456 | { | |
457 | sim_io_eprintf(sd,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile); | |
458 | tracefh = stderr; | |
459 | } | |
460 | } | |
461 | #endif /* TRACE */ | |
462 | ||
463 | void | |
464 | sim_close (sd, quitting) | |
465 | SIM_DESC sd; | |
466 | int quitting; | |
467 | { | |
468 | #ifdef DEBUG | |
469 | printf("DBG: sim_close: entered (quitting = %d)\n",quitting); | |
470 | #endif | |
471 | ||
472 | /* "quitting" is non-zero if we cannot hang on errors */ | |
473 | ||
474 | /* Ensure that any resources allocated through the callback | |
475 | mechanism are released: */ | |
476 | sim_io_shutdown (sd); | |
477 | ||
478 | #if defined(TRACE) | |
479 | if (tracefh != NULL && tracefh != stderr) | |
480 | fclose(tracefh); | |
481 | tracefh = NULL; | |
482 | STATE &= ~simTRACE; | |
483 | #endif /* TRACE */ | |
484 | ||
485 | return; | |
486 | } | |
487 | ||
488 | ||
489 | int | |
490 | sim_write (sd,addr,buffer,size) | |
491 | SIM_DESC sd; | |
492 | SIM_ADDR addr; | |
493 | unsigned char *buffer; | |
494 | int size; | |
495 | { | |
496 | int index; | |
497 | ||
498 | /* Return the number of bytes written, or zero if error. */ | |
499 | #ifdef DEBUG | |
500 | sim_io_printf(sd,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr),size); | |
501 | #endif | |
502 | ||
503 | /* We use raw read and write routines, since we do not want to count | |
504 | the GDB memory accesses in our statistics gathering. */ | |
505 | ||
506 | for (index = 0; index < size; index++) | |
507 | { | |
508 | address_word vaddr = (address_word)addr + index; | |
509 | address_word paddr; | |
510 | int cca; | |
511 | if (!address_translation (sd, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW)) | |
512 | break; | |
eefc25e5 | 513 | if (sim_core_write_buffer (sd, NULL, read_map, buffer + index, paddr, 1) != 1) |
1e1e3b61 IC |
514 | break; |
515 | } | |
516 | ||
517 | return(index); | |
518 | } | |
519 | ||
520 | int | |
521 | sim_read (sd,addr,buffer,size) | |
522 | SIM_DESC sd; | |
523 | SIM_ADDR addr; | |
524 | unsigned char *buffer; | |
525 | int size; | |
526 | { | |
527 | int index; | |
528 | ||
529 | /* Return the number of bytes read, or zero if error. */ | |
530 | #ifdef DEBUG | |
531 | sim_io_printf(sd,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr),size); | |
532 | #endif /* DEBUG */ | |
533 | ||
534 | for (index = 0; (index < size); index++) | |
535 | { | |
536 | address_word vaddr = (address_word)addr + index; | |
537 | address_word paddr; | |
538 | int cca; | |
539 | if (!address_translation (sd, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW)) | |
540 | break; | |
eefc25e5 | 541 | if (sim_core_read_buffer (sd, NULL, read_map, buffer + index, paddr, 1) != 1) |
1e1e3b61 IC |
542 | break; |
543 | } | |
544 | ||
545 | return(index); | |
546 | } | |
547 | ||
548 | void | |
549 | sim_store_register (sd,rn,memory) | |
550 | SIM_DESC sd; | |
551 | int rn; | |
552 | unsigned char *memory; | |
553 | { | |
554 | sim_cpu *cpu = STATE_CPU (sd, 0); | |
555 | /* NOTE: gdb (the client) stores registers in target byte order | |
556 | while the simulator uses host byte order */ | |
557 | #ifdef DEBUG | |
558 | sim_io_printf(sd,"sim_store_register(%d,*memory=0x%s);\n",rn,pr_addr(*((SIM_ADDR *)memory))); | |
559 | #endif /* DEBUG */ | |
560 | ||
561 | /* Unfortunately this suffers from the same problem as the register | |
562 | numbering one. We need to know what the width of each logical | |
563 | register number is for the architecture being simulated. */ | |
564 | ||
565 | if (cpu->register_widths[rn] == 0) | |
566 | sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn); | |
567 | /* start-sanitize-r5900 */ | |
568 | else if (rn == REGISTER_SA) | |
569 | SA = T2H_8(*(uword64*)memory); | |
570 | else if (rn > LAST_EMBED_REGNUM) | |
571 | cpu->registers1[rn - LAST_EMBED_REGNUM - 1] = T2H_8(*(uword64*)memory); | |
572 | /* end-sanitize-r5900 */ | |
573 | else if (cpu->register_widths[rn] == 32) | |
574 | cpu->registers[rn] = T2H_4 (*(unsigned int*)memory); | |
575 | else | |
576 | cpu->registers[rn] = T2H_8 (*(uword64*)memory); | |
577 | ||
578 | return; | |
579 | } | |
580 | ||
581 | void | |
582 | sim_fetch_register (sd,rn,memory) | |
583 | SIM_DESC sd; | |
584 | int rn; | |
585 | unsigned char *memory; | |
586 | { | |
587 | sim_cpu *cpu = STATE_CPU (sd, 0); | |
588 | /* NOTE: gdb (the client) stores registers in target byte order | |
589 | while the simulator uses host byte order */ | |
590 | #ifdef DEBUG | |
591 | sim_io_printf(sd,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn,pr_addr(registers[rn])); | |
592 | #endif /* DEBUG */ | |
593 | ||
594 | if (cpu->register_widths[rn] == 0) | |
595 | sim_io_eprintf(sd,"Invalid register width for %d (register fetch ignored)\n",rn); | |
596 | /* start-sanitize-r5900 */ | |
597 | else if (rn == REGISTER_SA) | |
598 | *((uword64 *)memory) = H2T_8(SA); | |
599 | else if (rn > LAST_EMBED_REGNUM) | |
600 | *((uword64 *)memory) = H2T_8(cpu->registers1[rn - LAST_EMBED_REGNUM - 1]); | |
601 | /* end-sanitize-r5900 */ | |
602 | else if (cpu->register_widths[rn] == 32) | |
603 | *((unsigned int *)memory) = H2T_4 ((unsigned int)(cpu->registers[rn] & 0xFFFFFFFF)); | |
604 | else /* 64bit register */ | |
605 | *((uword64 *)memory) = H2T_8 (cpu->registers[rn]); | |
606 | ||
607 | return; | |
608 | } | |
609 | ||
610 | ||
611 | void | |
612 | sim_info (sd,verbose) | |
613 | SIM_DESC sd; | |
614 | int verbose; | |
615 | { | |
616 | /* Accessed from the GDB "info files" command: */ | |
617 | if (STATE_VERBOSE_P (sd) || verbose) | |
618 | { | |
619 | ||
620 | sim_io_printf (sd, "MIPS %d-bit %s endian simulator\n", | |
621 | (PROCESSOR_64BIT ? 64 : 32), | |
622 | (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN ? "Big" : "Little")); | |
623 | ||
624 | #if !defined(FASTSIM) | |
625 | /* It would be a useful feature, if when performing multi-cycle | |
626 | simulations (rather than single-stepping) we keep the start and | |
627 | end times of the execution, so that we can give a performance | |
628 | figure for the simulator. */ | |
629 | #endif /* !FASTSIM */ | |
630 | sim_io_printf (sd, "Number of execution cycles = %ld\n", | |
631 | (long) sim_events_time (sd)); | |
632 | ||
633 | /* print information pertaining to MIPS ISA and architecture being simulated */ | |
634 | /* things that may be interesting */ | |
635 | /* instructions executed - if available */ | |
636 | /* cycles executed - if available */ | |
637 | /* pipeline stalls - if available */ | |
638 | /* virtual time taken */ | |
639 | /* profiling size */ | |
640 | /* profiling frequency */ | |
641 | /* profile minpc */ | |
642 | /* profile maxpc */ | |
643 | } | |
644 | profile_print (sd, STATE_VERBOSE_P (sd), NULL, NULL); | |
645 | } | |
646 | ||
647 | ||
648 | SIM_RC | |
649 | sim_create_inferior (sd, abfd, argv,env) | |
650 | SIM_DESC sd; | |
651 | struct _bfd *abfd; | |
652 | char **argv; | |
653 | char **env; | |
654 | { | |
655 | ||
656 | #ifdef DEBUG | |
657 | printf("DBG: sim_create_inferior entered: start_address = 0x%s\n", | |
658 | pr_addr(PC)); | |
659 | #endif /* DEBUG */ | |
660 | ||
661 | ColdReset(sd); | |
662 | ||
663 | if (abfd != NULL) | |
664 | /* override PC value set by ColdReset () */ | |
665 | PC = (unsigned64) bfd_get_start_address (abfd); | |
666 | ||
667 | #if 0 /* def DEBUG */ | |
668 | if (argv || env) | |
669 | { | |
670 | /* We should really place the argv slot values into the argument | |
671 | registers, and onto the stack as required. However, this | |
672 | assumes that we have a stack defined, which is not | |
673 | necessarily true at the moment. */ | |
674 | char **cptr; | |
675 | sim_io_printf(sd,"sim_create_inferior() : passed arguments ignored\n"); | |
676 | for (cptr = argv; (cptr && *cptr); cptr++) | |
677 | printf("DBG: arg \"%s\"\n",*cptr); | |
678 | } | |
679 | #endif /* DEBUG */ | |
680 | ||
681 | return SIM_RC_OK; | |
682 | } | |
683 | ||
684 | void | |
685 | sim_do_command (sd,cmd) | |
686 | SIM_DESC sd; | |
687 | char *cmd; | |
688 | { | |
689 | if (sim_args_command (sd, cmd) != SIM_RC_OK) | |
690 | sim_io_printf (sd, "Error: \"%s\" is not a valid MIPS simulator command.\n", | |
691 | cmd); | |
692 | } | |
693 | ||
694 | /*---------------------------------------------------------------------------*/ | |
695 | /*-- Private simulator support interface ------------------------------------*/ | |
696 | /*---------------------------------------------------------------------------*/ | |
697 | ||
698 | /* Read a null terminated string from memory, return in a buffer */ | |
699 | static char * | |
700 | fetch_str (sd, addr) | |
701 | SIM_DESC sd; | |
702 | address_word addr; | |
703 | { | |
704 | char *buf; | |
705 | int nr = 0; | |
706 | char null; | |
707 | while (sim_read (sd, addr + nr, &null, 1) == 1 && null != 0) | |
708 | nr++; | |
709 | buf = NZALLOC (char, nr + 1); | |
710 | sim_read (sd, addr, buf, nr); | |
711 | return buf; | |
712 | } | |
713 | ||
714 | /* Simple monitor interface (currently setup for the IDT and PMON monitors) */ | |
715 | static void | |
716 | sim_monitor(sd,cia,reason) | |
717 | SIM_DESC sd; | |
718 | address_word cia; | |
719 | unsigned int reason; | |
720 | { | |
721 | #ifdef DEBUG | |
722 | printf("DBG: sim_monitor: entered (reason = %d)\n",reason); | |
723 | #endif /* DEBUG */ | |
724 | ||
725 | /* The IDT monitor actually allows two instructions per vector | |
726 | slot. However, the simulator currently causes a trap on each | |
727 | individual instruction. We cheat, and lose the bottom bit. */ | |
728 | reason >>= 1; | |
729 | ||
730 | /* The following callback functions are available, however the | |
731 | monitor we are simulating does not make use of them: get_errno, | |
732 | isatty, lseek, rename, system, time and unlink */ | |
733 | switch (reason) | |
734 | { | |
735 | ||
736 | case 6: /* int open(char *path,int flags) */ | |
737 | { | |
738 | char *path = fetch_str (sd, A0); | |
739 | V0 = sim_io_open (sd, path, (int)A1); | |
740 | zfree (path); | |
741 | break; | |
742 | } | |
743 | ||
744 | case 7: /* int read(int file,char *ptr,int len) */ | |
745 | { | |
746 | int fd = A0; | |
747 | int nr = A2; | |
748 | char *buf = zalloc (nr); | |
749 | V0 = sim_io_read (sd, fd, buf, nr); | |
750 | sim_write (sd, A1, buf, nr); | |
751 | zfree (buf); | |
752 | } | |
753 | break; | |
754 | ||
755 | case 8: /* int write(int file,char *ptr,int len) */ | |
756 | { | |
757 | int fd = A0; | |
758 | int nr = A2; | |
759 | char *buf = zalloc (nr); | |
760 | sim_read (sd, A1, buf, nr); | |
761 | V0 = sim_io_write (sd, fd, buf, nr); | |
762 | zfree (buf); | |
763 | break; | |
764 | } | |
765 | ||
766 | case 10: /* int close(int file) */ | |
767 | { | |
768 | V0 = sim_io_close (sd, (int)A0); | |
769 | break; | |
770 | } | |
771 | ||
772 | case 2: /* Densan monitor: char inbyte(int waitflag) */ | |
773 | { | |
774 | if (A0 == 0) /* waitflag == NOWAIT */ | |
775 | V0 = (ut_reg)-1; | |
776 | } | |
777 | /* Drop through to case 11 */ | |
778 | ||
779 | case 11: /* char inbyte(void) */ | |
780 | { | |
781 | char tmp; | |
782 | if (sim_io_read_stdin (sd, &tmp, sizeof(char)) != sizeof(char)) | |
783 | { | |
784 | sim_io_error(sd,"Invalid return from character read"); | |
785 | V0 = (ut_reg)-1; | |
786 | } | |
787 | else | |
788 | V0 = (ut_reg)tmp; | |
789 | break; | |
790 | } | |
791 | ||
792 | case 3: /* Densan monitor: void co(char chr) */ | |
793 | case 12: /* void outbyte(char chr) : write a byte to "stdout" */ | |
794 | { | |
795 | char tmp = (char)(A0 & 0xFF); | |
796 | sim_io_write_stdout (sd, &tmp, sizeof(char)); | |
797 | break; | |
798 | } | |
799 | ||
800 | case 17: /* void _exit() */ | |
801 | { | |
802 | sim_io_eprintf (sd, "sim_monitor(17): _exit(int reason) to be coded\n"); | |
803 | sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA, sim_exited, | |
804 | (unsigned int)(A0 & 0xFFFFFFFF)); | |
805 | break; | |
806 | } | |
807 | ||
808 | case 28 : /* PMON flush_cache */ | |
809 | break; | |
810 | ||
811 | case 55: /* void get_mem_info(unsigned int *ptr) */ | |
812 | /* in: A0 = pointer to three word memory location */ | |
813 | /* out: [A0 + 0] = size */ | |
814 | /* [A0 + 4] = instruction cache size */ | |
815 | /* [A0 + 8] = data cache size */ | |
816 | { | |
817 | address_word value = MEM_SIZE /* FIXME STATE_MEM_SIZE (sd) */; | |
818 | H2T (value); | |
819 | sim_write (sd, A0, (char *)&value, sizeof (value)); | |
820 | /* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */ | |
821 | break; | |
822 | } | |
823 | ||
824 | case 158 : /* PMON printf */ | |
825 | /* in: A0 = pointer to format string */ | |
826 | /* A1 = optional argument 1 */ | |
827 | /* A2 = optional argument 2 */ | |
828 | /* A3 = optional argument 3 */ | |
829 | /* out: void */ | |
830 | /* The following is based on the PMON printf source */ | |
831 | { | |
832 | address_word s = A0; | |
833 | char c; | |
834 | signed_word *ap = &A1; /* 1st argument */ | |
835 | /* This isn't the quickest way, since we call the host print | |
836 | routine for every character almost. But it does avoid | |
837 | having to allocate and manage a temporary string buffer. */ | |
838 | /* TODO: Include check that we only use three arguments (A1, | |
839 | A2 and A3) */ | |
840 | while (sim_read (sd, s++, &c, 1) && c != '\0') | |
841 | { | |
842 | if (c == '%') | |
843 | { | |
844 | char tmp[40]; | |
845 | enum {FMT_RJUST, FMT_LJUST, FMT_RJUST0, FMT_CENTER} fmt = FMT_RJUST; | |
846 | int width = 0, trunc = 0, haddot = 0, longlong = 0; | |
847 | while (sim_read (sd, s++, &c, 1) && c != '\0') | |
848 | { | |
849 | if (strchr ("dobxXulscefg%", s)) | |
850 | break; | |
851 | else if (c == '-') | |
852 | fmt = FMT_LJUST; | |
853 | else if (c == '0') | |
854 | fmt = FMT_RJUST0; | |
855 | else if (c == '~') | |
856 | fmt = FMT_CENTER; | |
857 | else if (c == '*') | |
858 | { | |
859 | if (haddot) | |
860 | trunc = (int)*ap++; | |
861 | else | |
862 | width = (int)*ap++; | |
863 | } | |
864 | else if (c >= '1' && c <= '9') | |
865 | { | |
866 | address_word t = s; | |
867 | unsigned int n; | |
868 | while (sim_read (sd, s++, &c, 1) == 1 && isdigit (c)) | |
869 | tmp[s - t] = c; | |
870 | tmp[s - t] = '\0'; | |
871 | n = (unsigned int)strtol(tmp,NULL,10); | |
872 | if (haddot) | |
873 | trunc = n; | |
874 | else | |
875 | width = n; | |
876 | s--; | |
877 | } | |
878 | else if (c == '.') | |
879 | haddot = 1; | |
880 | } | |
881 | switch (c) | |
882 | { | |
883 | case '%': | |
884 | sim_io_printf (sd, "%%"); | |
885 | break; | |
886 | case 's': | |
887 | if ((int)*ap != 0) | |
888 | { | |
889 | address_word p = *ap++; | |
890 | char ch; | |
891 | while (sim_read (sd, p++, &ch, 1) == 1 && ch != '\0') | |
892 | sim_io_printf(sd, "%c", ch); | |
893 | } | |
894 | else | |
895 | sim_io_printf(sd,"(null)"); | |
896 | break; | |
897 | case 'c': | |
898 | sim_io_printf (sd, "%c", (int)*ap++); | |
899 | break; | |
900 | default: | |
901 | if (c == 'l') | |
902 | { | |
903 | sim_read (sd, s++, &c, 1); | |
904 | if (c == 'l') | |
905 | { | |
906 | longlong = 1; | |
907 | sim_read (sd, s++, &c, 1); | |
908 | } | |
909 | } | |
910 | if (strchr ("dobxXu", c)) | |
911 | { | |
912 | word64 lv = (word64) *ap++; | |
913 | if (c == 'b') | |
914 | sim_io_printf(sd,"<binary not supported>"); | |
915 | else | |
916 | { | |
917 | sprintf (tmp, "%%%s%c", longlong ? "ll" : "", c); | |
918 | if (longlong) | |
919 | sim_io_printf(sd, tmp, lv); | |
920 | else | |
921 | sim_io_printf(sd, tmp, (int)lv); | |
922 | } | |
923 | } | |
924 | else if (strchr ("eEfgG", c)) | |
925 | { | |
926 | double dbl = *(double*)(ap++); | |
927 | sprintf (tmp, "%%%d.%d%c", width, trunc, c); | |
928 | sim_io_printf (sd, tmp, dbl); | |
929 | trunc = 0; | |
930 | } | |
931 | } | |
932 | } | |
933 | else | |
934 | sim_io_printf(sd, "%c", c); | |
935 | } | |
936 | break; | |
937 | } | |
938 | ||
939 | default: | |
940 | sim_io_error (sd, "TODO: sim_monitor(%d) : PC = 0x%s\n", | |
941 | reason, pr_addr(cia)); | |
942 | break; | |
943 | } | |
944 | return; | |
945 | } | |
946 | ||
947 | /* Store a word into memory. */ | |
948 | ||
949 | static void | |
950 | store_word (sd, cia, vaddr, val) | |
951 | SIM_DESC sd; | |
952 | address_word cia; | |
953 | uword64 vaddr; | |
954 | t_reg val; | |
955 | { | |
956 | address_word paddr; | |
957 | int uncached; | |
958 | ||
959 | if ((vaddr & 3) != 0) | |
960 | SignalExceptionAddressStore (); | |
961 | else | |
962 | { | |
963 | if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, | |
964 | isTARGET, isREAL)) | |
965 | { | |
966 | const uword64 mask = 7; | |
967 | uword64 memval; | |
968 | unsigned int byte; | |
969 | ||
970 | paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)); | |
971 | byte = (vaddr & mask) ^ (BigEndianCPU << 2); | |
972 | memval = ((uword64) val) << (8 * byte); | |
973 | StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr, | |
974 | isREAL); | |
975 | } | |
976 | } | |
977 | } | |
978 | ||
979 | /* Load a word from memory. */ | |
980 | ||
981 | static t_reg | |
982 | load_word (sd, cia, vaddr) | |
983 | SIM_DESC sd; | |
984 | address_word cia; | |
985 | uword64 vaddr; | |
986 | { | |
987 | if ((vaddr & 3) != 0) | |
988 | SignalExceptionAddressLoad (); | |
989 | else | |
990 | { | |
991 | address_word paddr; | |
992 | int uncached; | |
993 | ||
994 | if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, | |
995 | isTARGET, isREAL)) | |
996 | { | |
997 | const uword64 mask = 0x7; | |
998 | const unsigned int reverse = ReverseEndian ? 1 : 0; | |
999 | const unsigned int bigend = BigEndianCPU ? 1 : 0; | |
1000 | uword64 memval; | |
1001 | unsigned int byte; | |
1002 | ||
1003 | paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2)); | |
1004 | LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr, | |
1005 | isDATA, isREAL); | |
1006 | byte = (vaddr & mask) ^ (bigend << 2); | |
1007 | return SIGNEXTEND (((memval >> (8 * byte)) & 0xffffffff), 32); | |
1008 | } | |
1009 | } | |
1010 | ||
1011 | return 0; | |
1012 | } | |
1013 | ||
1014 | /* Simulate the mips16 entry and exit pseudo-instructions. These | |
1015 | would normally be handled by the reserved instruction exception | |
1016 | code, but for ease of simulation we just handle them directly. */ | |
1017 | ||
1018 | static void | |
1019 | mips16_entry (sd,insn) | |
1020 | SIM_DESC sd; | |
1021 | unsigned int insn; | |
1022 | { | |
1023 | int aregs, sregs, rreg; | |
1024 | ||
1025 | #ifdef DEBUG | |
1026 | printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn); | |
1027 | #endif /* DEBUG */ | |
1028 | ||
1029 | aregs = (insn & 0x700) >> 8; | |
1030 | sregs = (insn & 0x0c0) >> 6; | |
1031 | rreg = (insn & 0x020) >> 5; | |
1032 | ||
1033 | /* This should be checked by the caller. */ | |
1034 | if (sregs == 3) | |
1035 | abort (); | |
1036 | ||
1037 | if (aregs < 5) | |
1038 | { | |
1039 | int i; | |
1040 | t_reg tsp; | |
1041 | ||
1042 | /* This is the entry pseudo-instruction. */ | |
1043 | ||
1044 | for (i = 0; i < aregs; i++) | |
1045 | store_word ((uword64) (SP + 4 * i), GPR[i + 4]); | |
1046 | ||
1047 | tsp = SP; | |
1048 | SP -= 32; | |
1049 | ||
1050 | if (rreg) | |
1051 | { | |
1052 | tsp -= 4; | |
1053 | store_word ((uword64) tsp, RA); | |
1054 | } | |
1055 | ||
1056 | for (i = 0; i < sregs; i++) | |
1057 | { | |
1058 | tsp -= 4; | |
1059 | store_word ((uword64) tsp, GPR[16 + i]); | |
1060 | } | |
1061 | } | |
1062 | else | |
1063 | { | |
1064 | int i; | |
1065 | t_reg tsp; | |
1066 | ||
1067 | /* This is the exit pseudo-instruction. */ | |
1068 | ||
1069 | tsp = SP + 32; | |
1070 | ||
1071 | if (rreg) | |
1072 | { | |
1073 | tsp -= 4; | |
1074 | RA = load_word ((uword64) tsp); | |
1075 | } | |
1076 | ||
1077 | for (i = 0; i < sregs; i++) | |
1078 | { | |
1079 | tsp -= 4; | |
1080 | GPR[i + 16] = load_word ((uword64) tsp); | |
1081 | } | |
1082 | ||
1083 | SP += 32; | |
1084 | ||
1085 | #if defined(HASFPU) | |
1086 | if (aregs == 5) | |
1087 | { | |
1088 | FGR[0] = WORD64LO (GPR[4]); | |
1089 | FPR_STATE[0] = fmt_uninterpreted; | |
1090 | } | |
1091 | else if (aregs == 6) | |
1092 | { | |
1093 | FGR[0] = WORD64LO (GPR[5]); | |
1094 | FGR[1] = WORD64LO (GPR[4]); | |
1095 | FPR_STATE[0] = fmt_uninterpreted; | |
1096 | FPR_STATE[1] = fmt_uninterpreted; | |
1097 | } | |
1098 | #endif /* defined(HASFPU) */ | |
1099 | ||
1100 | PC = RA; | |
1101 | } | |
1102 | } | |
1103 | ||
1104 | /*-- trace support ----------------------------------------------------------*/ | |
1105 | ||
1106 | /* The TRACE support is provided (if required) in the memory accessing | |
1107 | routines. Since we are also providing the architecture specific | |
1108 | features, the architecture simulation code can also deal with | |
1109 | notifying the TRACE world of cache flushes, etc. Similarly we do | |
1110 | not need to provide profiling support in the simulator engine, | |
1111 | since we can sample in the instruction fetch control loop. By | |
1112 | defining the TRACE manifest, we add tracing as a run-time | |
1113 | option. */ | |
1114 | ||
1115 | #if defined(TRACE) | |
1116 | /* Tracing by default produces "din" format (as required by | |
1117 | dineroIII). Each line of such a trace file *MUST* have a din label | |
1118 | and address field. The rest of the line is ignored, so comments can | |
1119 | be included if desired. The first field is the label which must be | |
1120 | one of the following values: | |
1121 | ||
1122 | 0 read data | |
1123 | 1 write data | |
1124 | 2 instruction fetch | |
1125 | 3 escape record (treated as unknown access type) | |
1126 | 4 escape record (causes cache flush) | |
1127 | ||
1128 | The address field is a 32bit (lower-case) hexadecimal address | |
1129 | value. The address should *NOT* be preceded by "0x". | |
1130 | ||
1131 | The size of the memory transfer is not important when dealing with | |
1132 | cache lines (as long as no more than a cache line can be | |
1133 | transferred in a single operation :-), however more information | |
1134 | could be given following the dineroIII requirement to allow more | |
1135 | complete memory and cache simulators to provide better | |
1136 | results. i.e. the University of Pisa has a cache simulator that can | |
1137 | also take bus size and speed as (variable) inputs to calculate | |
1138 | complete system performance (a much more useful ability when trying | |
1139 | to construct an end product, rather than a processor). They | |
1140 | currently have an ARM version of their tool called ChARM. */ | |
1141 | ||
1142 | ||
1143 | void | |
1144 | dotrace (SIM_DESC sd,FILE *tracefh,int type,SIM_ADDR address,int width,char *comment,...) | |
1145 | { | |
1146 | if (STATE & simTRACE) { | |
1147 | va_list ap; | |
1148 | fprintf(tracefh,"%d %s ; width %d ; ", | |
1149 | type, | |
1150 | pr_addr(address), | |
1151 | width); | |
1152 | va_start(ap,comment); | |
1153 | vfprintf(tracefh,comment,ap); | |
1154 | va_end(ap); | |
1155 | fprintf(tracefh,"\n"); | |
1156 | } | |
1157 | /* NOTE: Since the "din" format will only accept 32bit addresses, and | |
1158 | we may be generating 64bit ones, we should put the hi-32bits of the | |
1159 | address into the comment field. */ | |
1160 | ||
1161 | /* TODO: Provide a buffer for the trace lines. We can then avoid | |
1162 | performing writes until the buffer is filled, or the file is | |
1163 | being closed. */ | |
1164 | ||
1165 | /* NOTE: We could consider adding a comment field to the "din" file | |
1166 | produced using type 3 markers (unknown access). This would then | |
1167 | allow information about the program that the "din" is for, and | |
1168 | the MIPs world that was being simulated, to be placed into the | |
1169 | trace file. */ | |
1170 | ||
1171 | return; | |
1172 | } | |
1173 | #endif /* TRACE */ | |
1174 | ||
1175 | /*---------------------------------------------------------------------------*/ | |
1176 | /*-- simulator engine -------------------------------------------------------*/ | |
1177 | /*---------------------------------------------------------------------------*/ | |
1178 | ||
1179 | static void | |
1180 | ColdReset (sd) | |
1181 | SIM_DESC sd; | |
1182 | { | |
1183 | /* RESET: Fixed PC address: */ | |
1184 | PC = UNSIGNED64 (0xFFFFFFFFBFC00000); | |
1185 | /* The reset vector address is in the unmapped, uncached memory space. */ | |
1186 | ||
1187 | SR &= ~(status_SR | status_TS | status_RP); | |
1188 | SR |= (status_ERL | status_BEV); | |
1189 | ||
1190 | /* Cheat and allow access to the complete register set immediately */ | |
1191 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT | |
1192 | && WITH_TARGET_WORD_BITSIZE == 64) | |
1193 | SR |= status_FR; /* 64bit registers */ | |
1194 | ||
1195 | /* Ensure that any instructions with pending register updates are | |
1196 | cleared: */ | |
1197 | { | |
1198 | int loop; | |
1199 | for (loop = 0; (loop < PSLOTS); loop++) | |
1200 | PENDING_SLOT_REG[loop] = (LAST_EMBED_REGNUM + 1); | |
1201 | PENDING_IN = PENDING_OUT = PENDING_TOTAL = 0; | |
1202 | } | |
1203 | ||
1204 | /* Initialise the FPU registers to the unknown state */ | |
1205 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) | |
1206 | { | |
1207 | int rn; | |
1208 | for (rn = 0; (rn < 32); rn++) | |
1209 | FPR_STATE[rn] = fmt_uninterpreted; | |
1210 | } | |
1211 | ||
1212 | return; | |
1213 | } | |
1214 | ||
1215 | /* Description from page A-22 of the "MIPS IV Instruction Set" manual | |
1216 | (revision 3.1) */ | |
1217 | /* Translate a virtual address to a physical address and cache | |
1218 | coherence algorithm describing the mechanism used to resolve the | |
1219 | memory reference. Given the virtual address vAddr, and whether the | |
1220 | reference is to Instructions ot Data (IorD), find the corresponding | |
1221 | physical address (pAddr) and the cache coherence algorithm (CCA) | |
1222 | used to resolve the reference. If the virtual address is in one of | |
1223 | the unmapped address spaces the physical address and the CCA are | |
1224 | determined directly by the virtual address. If the virtual address | |
1225 | is in one of the mapped address spaces then the TLB is used to | |
1226 | determine the physical address and access type; if the required | |
1227 | translation is not present in the TLB or the desired access is not | |
1228 | permitted the function fails and an exception is taken. | |
1229 | ||
1230 | NOTE: Normally (RAW == 0), when address translation fails, this | |
1231 | function raises an exception and does not return. */ | |
1232 | ||
1233 | int | |
1234 | address_translation(sd,cia,vAddr,IorD,LorS,pAddr,CCA,raw) | |
1235 | SIM_DESC sd; | |
1236 | address_word cia; | |
1237 | address_word vAddr; | |
1238 | int IorD; | |
1239 | int LorS; | |
1240 | address_word *pAddr; | |
1241 | int *CCA; | |
1242 | int raw; | |
1243 | { | |
1244 | int res = -1; /* TRUE : Assume good return */ | |
1245 | ||
1246 | #ifdef DEBUG | |
1247 | sim_io_printf(sd,"AddressTranslation(0x%s,%s,%s,...);\n",pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "iSTORE" : "isLOAD")); | |
1248 | #endif | |
1249 | ||
1250 | /* Check that the address is valid for this memory model */ | |
1251 | ||
1252 | /* For a simple (flat) memory model, we simply pass virtual | |
1253 | addressess through (mostly) unchanged. */ | |
1254 | vAddr &= 0xFFFFFFFF; | |
1255 | ||
1256 | *pAddr = vAddr; /* default for isTARGET */ | |
1257 | *CCA = Uncached; /* not used for isHOST */ | |
1258 | ||
1259 | return(res); | |
1260 | } | |
1261 | ||
1262 | /* Description from page A-23 of the "MIPS IV Instruction Set" manual | |
1263 | (revision 3.1) */ | |
1264 | /* Prefetch data from memory. Prefetch is an advisory instruction for | |
1265 | which an implementation specific action is taken. The action taken | |
1266 | may increase performance, but must not change the meaning of the | |
1267 | program, or alter architecturally-visible state. */ | |
1268 | ||
1269 | void | |
1270 | prefetch(sd,cia,CCA,pAddr,vAddr,DATA,hint) | |
1271 | SIM_DESC sd; | |
1272 | address_word cia; | |
1273 | int CCA; | |
1274 | address_word pAddr; | |
1275 | address_word vAddr; | |
1276 | int DATA; | |
1277 | int hint; | |
1278 | { | |
1279 | #ifdef DEBUG | |
1280 | sim_io_printf(sd,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA,pr_addr(pAddr),pr_addr(vAddr),DATA,hint); | |
1281 | #endif /* DEBUG */ | |
1282 | ||
1283 | /* For our simple memory model we do nothing */ | |
1284 | return; | |
1285 | } | |
1286 | ||
1287 | /* Description from page A-22 of the "MIPS IV Instruction Set" manual | |
1288 | (revision 3.1) */ | |
1289 | /* Load a value from memory. Use the cache and main memory as | |
1290 | specified in the Cache Coherence Algorithm (CCA) and the sort of | |
1291 | access (IorD) to find the contents of AccessLength memory bytes | |
1292 | starting at physical location pAddr. The data is returned in the | |
1293 | fixed width naturally-aligned memory element (MemElem). The | |
1294 | low-order two (or three) bits of the address and the AccessLength | |
1295 | indicate which of the bytes within MemElem needs to be given to the | |
1296 | processor. If the memory access type of the reference is uncached | |
1297 | then only the referenced bytes are read from memory and valid | |
1298 | within the memory element. If the access type is cached, and the | |
1299 | data is not present in cache, an implementation specific size and | |
1300 | alignment block of memory is read and loaded into the cache to | |
1301 | satisfy a load reference. At a minimum, the block is the entire | |
1302 | memory element. */ | |
1303 | void | |
1304 | load_memory(sd,cia,memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD) | |
1305 | SIM_DESC sd; | |
1306 | address_word cia; | |
1307 | uword64* memvalp; | |
1308 | uword64* memval1p; | |
1309 | int CCA; | |
1310 | int AccessLength; | |
1311 | address_word pAddr; | |
1312 | address_word vAddr; | |
1313 | int IorD; | |
1314 | { | |
1315 | uword64 value = 0; | |
1316 | uword64 value1 = 0; | |
1317 | ||
1318 | #ifdef DEBUG | |
1319 | sim_io_printf(sd,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s)\n",memvalp,memval1p,CCA,AccessLength,pr_addr(pAddr),pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION")); | |
1320 | #endif /* DEBUG */ | |
1321 | ||
1322 | #if defined(WARN_MEM) | |
1323 | if (CCA != uncached) | |
1324 | sim_io_eprintf(sd,"LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA); | |
1325 | #endif /* WARN_MEM */ | |
1326 | ||
1327 | /* If instruction fetch then we need to check that the two lo-order | |
1328 | bits are zero, otherwise raise a InstructionFetch exception: */ | |
1329 | if ((IorD == isINSTRUCTION) | |
1330 | && ((pAddr & 0x3) != 0) | |
1331 | && (((pAddr & 0x1) != 0) || ((vAddr & 0x1) == 0))) | |
1332 | SignalExceptionInstructionFetch (); | |
1333 | ||
1334 | if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK) | |
1335 | { | |
1336 | /* In reality this should be a Bus Error */ | |
1337 | sim_io_error (sd, "AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n", | |
1338 | AccessLength, | |
1339 | (LOADDRMASK + 1) << 2, | |
1340 | pr_addr (pAddr)); | |
1341 | } | |
1342 | ||
1343 | #if defined(TRACE) | |
1344 | dotrace(sd,tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction")); | |
1345 | #endif /* TRACE */ | |
1346 | ||
1347 | /* Read the specified number of bytes from memory. Adjust for | |
1348 | host/target byte ordering/ Align the least significant byte | |
1349 | read. */ | |
1350 | ||
1351 | switch (AccessLength) | |
1352 | { | |
1353 | case AccessLength_QUADWORD : | |
1354 | { | |
eefc25e5 | 1355 | unsigned_16 val = sim_core_read_aligned_16 (STATE_CPU (sd, 0), NULL_CIA, read_map, pAddr); |
1e1e3b61 IC |
1356 | value1 = VH8_16 (val); |
1357 | value = VL8_16 (val); | |
1358 | break; | |
1359 | } | |
1360 | case AccessLength_DOUBLEWORD : | |
1361 | value = sim_core_read_aligned_8 (STATE_CPU (sd, 0), NULL_CIA, | |
eefc25e5 | 1362 | read_map, pAddr); |
1e1e3b61 IC |
1363 | break; |
1364 | case AccessLength_SEPTIBYTE : | |
1365 | value = sim_core_read_misaligned_7 (STATE_CPU (sd, 0), NULL_CIA, | |
eefc25e5 | 1366 | read_map, pAddr); |
1e1e3b61 IC |
1367 | case AccessLength_SEXTIBYTE : |
1368 | value = sim_core_read_misaligned_6 (STATE_CPU (sd, 0), NULL_CIA, | |
eefc25e5 | 1369 | read_map, pAddr); |
1e1e3b61 IC |
1370 | case AccessLength_QUINTIBYTE : |
1371 | value = sim_core_read_misaligned_5 (STATE_CPU (sd, 0), NULL_CIA, | |
eefc25e5 | 1372 | read_map, pAddr); |
1e1e3b61 IC |
1373 | case AccessLength_WORD : |
1374 | value = sim_core_read_aligned_4 (STATE_CPU (sd, 0), NULL_CIA, | |
eefc25e5 | 1375 | read_map, pAddr); |
1e1e3b61 IC |
1376 | break; |
1377 | case AccessLength_TRIPLEBYTE : | |
1378 | value = sim_core_read_misaligned_3 (STATE_CPU (sd, 0), NULL_CIA, | |
eefc25e5 | 1379 | read_map, pAddr); |
1e1e3b61 IC |
1380 | case AccessLength_HALFWORD : |
1381 | value = sim_core_read_aligned_2 (STATE_CPU (sd, 0), NULL_CIA, | |
eefc25e5 | 1382 | read_map, pAddr); |
1e1e3b61 IC |
1383 | break; |
1384 | case AccessLength_BYTE : | |
1385 | value = sim_core_read_aligned_1 (STATE_CPU (sd, 0), NULL_CIA, | |
eefc25e5 | 1386 | read_map, pAddr); |
1e1e3b61 IC |
1387 | break; |
1388 | default: | |
1389 | abort (); | |
1390 | } | |
1391 | ||
1392 | #ifdef DEBUG | |
1393 | printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n", | |
1394 | (int)(pAddr & LOADDRMASK),pr_uword64(value1),pr_uword64(value)); | |
1395 | #endif /* DEBUG */ | |
1396 | ||
1397 | /* See also store_memory. */ | |
1398 | if (AccessLength <= AccessLength_DOUBLEWORD) | |
1399 | { | |
1400 | if (BigEndianMem) | |
1401 | /* for big endian target, byte (pAddr&LOADDRMASK == 0) is | |
1402 | shifted to the most significant byte position. */ | |
1403 | value <<= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8); | |
1404 | else | |
1405 | /* For little endian target, byte (pAddr&LOADDRMASK == 0) | |
1406 | is already in the correct postition. */ | |
1407 | value <<= ((pAddr & LOADDRMASK) * 8); | |
1408 | } | |
1409 | ||
1410 | #ifdef DEBUG | |
1411 | printf("DBG: LoadMemory() : shifted value = 0x%s%s\n", | |
1412 | pr_uword64(value1),pr_uword64(value)); | |
1413 | #endif /* DEBUG */ | |
1414 | ||
1415 | *memvalp = value; | |
1416 | if (memval1p) *memval1p = value1; | |
1417 | } | |
1418 | ||
1419 | ||
1420 | /* Description from page A-23 of the "MIPS IV Instruction Set" manual | |
1421 | (revision 3.1) */ | |
1422 | /* Store a value to memory. The specified data is stored into the | |
1423 | physical location pAddr using the memory hierarchy (data caches and | |
1424 | main memory) as specified by the Cache Coherence Algorithm | |
1425 | (CCA). The MemElem contains the data for an aligned, fixed-width | |
1426 | memory element (word for 32-bit processors, doubleword for 64-bit | |
1427 | processors), though only the bytes that will actually be stored to | |
1428 | memory need to be valid. The low-order two (or three) bits of pAddr | |
1429 | and the AccessLength field indicates which of the bytes within the | |
1430 | MemElem data should actually be stored; only these bytes in memory | |
1431 | will be changed. */ | |
1432 | ||
1433 | void | |
1434 | store_memory(sd,cia,CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr) | |
1435 | SIM_DESC sd; | |
1436 | address_word cia; | |
1437 | int CCA; | |
1438 | int AccessLength; | |
1439 | uword64 MemElem; | |
1440 | uword64 MemElem1; /* High order 64 bits */ | |
1441 | address_word pAddr; | |
1442 | address_word vAddr; | |
1443 | { | |
1444 | #ifdef DEBUG | |
1445 | sim_io_printf(sd,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s)\n",CCA,AccessLength,pr_uword64(MemElem),pr_uword64(MemElem1),pr_addr(pAddr),pr_addr(vAddr)); | |
1446 | #endif /* DEBUG */ | |
1447 | ||
1448 | #if defined(WARN_MEM) | |
1449 | if (CCA != uncached) | |
1450 | sim_io_eprintf(sd,"StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA); | |
1451 | #endif /* WARN_MEM */ | |
1452 | ||
1453 | if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK) | |
1454 | sim_io_error(sd,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength,(LOADDRMASK + 1)<<2,pr_addr(pAddr)); | |
1455 | ||
1456 | #if defined(TRACE) | |
1457 | dotrace(sd,tracefh,1,(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"store"); | |
1458 | #endif /* TRACE */ | |
1459 | ||
1460 | #ifdef DEBUG | |
1461 | printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr & LOADDRMASK),pr_uword64(MemElem1),pr_uword64(MemElem)); | |
1462 | #endif /* DEBUG */ | |
1463 | ||
1464 | /* See also load_memory */ | |
1465 | if (AccessLength <= AccessLength_DOUBLEWORD) | |
1466 | { | |
1467 | if (BigEndianMem) | |
1468 | /* for big endian target, byte (pAddr&LOADDRMASK == 0) is | |
1469 | shifted to the most significant byte position. */ | |
1470 | MemElem >>= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8); | |
1471 | else | |
1472 | /* For little endian target, byte (pAddr&LOADDRMASK == 0) | |
1473 | is already in the correct postition. */ | |
1474 | MemElem >>= ((pAddr & LOADDRMASK) * 8); | |
1475 | } | |
1476 | ||
1477 | #ifdef DEBUG | |
1478 | printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift,pr_uword64(MemElem1),pr_uword64(MemElem)); | |
1479 | #endif /* DEBUG */ | |
1480 | ||
1481 | switch (AccessLength) | |
1482 | { | |
1483 | case AccessLength_QUADWORD : | |
1484 | { | |
1485 | unsigned_16 val = U16_8 (MemElem1, MemElem); | |
1486 | sim_core_write_aligned_16 (STATE_CPU (sd, 0), NULL_CIA, | |
eefc25e5 | 1487 | write_map, pAddr, val); |
1e1e3b61 IC |
1488 | break; |
1489 | } | |
1490 | case AccessLength_DOUBLEWORD : | |
1491 | sim_core_write_aligned_8 (STATE_CPU (sd, 0), NULL_CIA, | |
eefc25e5 | 1492 | write_map, pAddr, MemElem); |
1e1e3b61 IC |
1493 | break; |
1494 | case AccessLength_SEPTIBYTE : | |
1495 | sim_core_write_misaligned_7 (STATE_CPU (sd, 0), NULL_CIA, | |
eefc25e5 | 1496 | write_map, pAddr, MemElem); |
1e1e3b61 IC |
1497 | break; |
1498 | case AccessLength_SEXTIBYTE : | |
1499 | sim_core_write_misaligned_6 (STATE_CPU (sd, 0), NULL_CIA, | |
eefc25e5 | 1500 | write_map, pAddr, MemElem); |
1e1e3b61 IC |
1501 | break; |
1502 | case AccessLength_QUINTIBYTE : | |
1503 | sim_core_write_misaligned_5 (STATE_CPU (sd, 0), NULL_CIA, | |
eefc25e5 | 1504 | write_map, pAddr, MemElem); |
1e1e3b61 IC |
1505 | break; |
1506 | case AccessLength_WORD : | |
1507 | sim_core_write_aligned_4 (STATE_CPU (sd, 0), NULL_CIA, | |
eefc25e5 | 1508 | write_map, pAddr, MemElem); |
1e1e3b61 IC |
1509 | break; |
1510 | case AccessLength_TRIPLEBYTE : | |
1511 | sim_core_write_misaligned_3 (STATE_CPU (sd, 0), NULL_CIA, | |
eefc25e5 | 1512 | write_map, pAddr, MemElem); |
1e1e3b61 IC |
1513 | break; |
1514 | case AccessLength_HALFWORD : | |
1515 | sim_core_write_aligned_2 (STATE_CPU (sd, 0), NULL_CIA, | |
eefc25e5 | 1516 | write_map, pAddr, MemElem); |
1e1e3b61 IC |
1517 | break; |
1518 | case AccessLength_BYTE : | |
1519 | sim_core_write_aligned_1 (STATE_CPU (sd, 0), NULL_CIA, | |
eefc25e5 | 1520 | write_map, pAddr, MemElem); |
1e1e3b61 IC |
1521 | break; |
1522 | default: | |
1523 | abort (); | |
1524 | } | |
1525 | ||
1526 | return; | |
1527 | } | |
1528 | ||
1529 | ||
1530 | unsigned32 | |
1531 | ifetch32 (SIM_DESC sd, | |
1532 | address_word cia, | |
1533 | address_word vaddr) | |
1534 | { | |
1535 | /* Copy the action of the LW instruction */ | |
1536 | address_word reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0); | |
1537 | address_word bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0); | |
1538 | unsigned64 value; | |
1539 | address_word paddr; | |
1540 | unsigned32 instruction; | |
1541 | unsigned byte; | |
1542 | int cca; | |
1543 | AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &cca, isTARGET, isREAL); | |
1544 | paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2))); | |
1545 | LoadMemory (&value, NULL, cca, AccessLength_WORD, paddr, vaddr, isINSTRUCTION, isREAL); | |
1546 | byte = ((vaddr & LOADDRMASK) ^ (bigend << 2)); | |
1547 | instruction = ((value >> (8 * byte)) & 0xFFFFFFFF); | |
1548 | return instruction; | |
1549 | } | |
1550 | ||
1551 | ||
1552 | /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */ | |
1553 | /* Order loads and stores to synchronise shared memory. Perform the | |
1554 | action necessary to make the effects of groups of synchronizable | |
1555 | loads and stores indicated by stype occur in the same order for all | |
1556 | processors. */ | |
1557 | void | |
1558 | sync_operation(sd,cia,stype) | |
1559 | SIM_DESC sd; | |
1560 | address_word cia; | |
1561 | int stype; | |
1562 | { | |
1563 | #ifdef DEBUG | |
1564 | sim_io_printf(sd,"SyncOperation(%d) : TODO\n",stype); | |
1565 | #endif /* DEBUG */ | |
1566 | return; | |
1567 | } | |
1568 | ||
1569 | /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */ | |
1570 | /* Signal an exception condition. This will result in an exception | |
1571 | that aborts the instruction. The instruction operation pseudocode | |
1572 | will never see a return from this function call. */ | |
1573 | ||
1574 | void | |
1575 | signal_exception (SIM_DESC sd, | |
1576 | address_word cia, | |
1577 | int exception,...) | |
1578 | { | |
1579 | int vector; | |
1580 | ||
1581 | #ifdef DEBUG | |
1582 | sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia)); | |
1583 | #endif /* DEBUG */ | |
1584 | ||
1585 | /* Ensure that any active atomic read/modify/write operation will fail: */ | |
1586 | LLBIT = 0; | |
1587 | ||
1588 | switch (exception) { | |
1589 | /* TODO: For testing purposes I have been ignoring TRAPs. In | |
1590 | reality we should either simulate them, or allow the user to | |
1591 | ignore them at run-time. | |
1592 | Same for SYSCALL */ | |
1593 | case Trap : | |
1594 | sim_io_eprintf(sd,"Ignoring instruction TRAP (PC 0x%s)\n",pr_addr(cia)); | |
1595 | break; | |
1596 | ||
1597 | case SystemCall : | |
1598 | { | |
1599 | va_list ap; | |
1600 | unsigned int instruction; | |
1601 | unsigned int code; | |
1602 | ||
1603 | va_start(ap,exception); | |
1604 | instruction = va_arg(ap,unsigned int); | |
1605 | va_end(ap); | |
1606 | ||
1607 | code = (instruction >> 6) & 0xFFFFF; | |
1608 | ||
1609 | sim_io_eprintf(sd,"Ignoring instruction `syscall %d' (PC 0x%s)\n", | |
1610 | code, pr_addr(cia)); | |
1611 | } | |
1612 | break; | |
1613 | ||
1614 | case DebugBreakPoint : | |
1615 | if (! (Debug & Debug_DM)) | |
1616 | { | |
1617 | if (INDELAYSLOT()) | |
1618 | { | |
1619 | CANCELDELAYSLOT(); | |
1620 | ||
1621 | Debug |= Debug_DBD; /* signaled from within in delay slot */ | |
1622 | DEPC = cia - 4; /* reference the branch instruction */ | |
1623 | } | |
1624 | else | |
1625 | { | |
1626 | Debug &= ~Debug_DBD; /* not signaled from within a delay slot */ | |
1627 | DEPC = cia; | |
1628 | } | |
1629 | ||
1630 | Debug |= Debug_DM; /* in debugging mode */ | |
1631 | Debug |= Debug_DBp; /* raising a DBp exception */ | |
1632 | PC = 0xBFC00200; | |
1633 | sim_engine_restart (sd, STATE_CPU (sd, 0), NULL, NULL_CIA); | |
1634 | } | |
1635 | break; | |
1636 | ||
1637 | case ReservedInstruction : | |
1638 | { | |
1639 | va_list ap; | |
1640 | unsigned int instruction; | |
1641 | va_start(ap,exception); | |
1642 | instruction = va_arg(ap,unsigned int); | |
1643 | va_end(ap); | |
1644 | /* Provide simple monitor support using ReservedInstruction | |
1645 | exceptions. The following code simulates the fixed vector | |
1646 | entry points into the IDT monitor by causing a simulator | |
1647 | trap, performing the monitor operation, and returning to | |
1648 | the address held in the $ra register (standard PCS return | |
1649 | address). This means we only need to pre-load the vector | |
1650 | space with suitable instruction values. For systems were | |
1651 | actual trap instructions are used, we would not need to | |
1652 | perform this magic. */ | |
1653 | if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION) | |
1654 | { | |
1655 | sim_monitor(sd, cia, ((instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK) ); | |
1656 | /* NOTE: This assumes that a branch-and-link style | |
1657 | instruction was used to enter the vector (which is the | |
1658 | case with the current IDT monitor). */ | |
1659 | sim_engine_restart (sd, STATE_CPU (sd, 0), NULL, RA); | |
1660 | } | |
1661 | /* Look for the mips16 entry and exit instructions, and | |
1662 | simulate a handler for them. */ | |
1663 | else if ((cia & 1) != 0 | |
1664 | && (instruction & 0xf81f) == 0xe809 | |
1665 | && (instruction & 0x0c0) != 0x0c0) | |
1666 | { | |
1667 | mips16_entry (instruction); | |
1668 | sim_engine_restart (sd, NULL, NULL, NULL_CIA); | |
1669 | } | |
1670 | /* else fall through to normal exception processing */ | |
1671 | sim_io_eprintf(sd,"ReservedInstruction 0x%08X at PC = 0x%s\n",instruction,pr_addr(cia)); | |
1672 | } | |
1673 | ||
1674 | case BreakPoint: | |
1675 | #ifdef DEBUG | |
1676 | sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia)); | |
1677 | #endif /* DEBUG */ | |
1678 | /* Keep a copy of the current A0 in-case this is the program exit | |
1679 | breakpoint: */ | |
1680 | { | |
1681 | va_list ap; | |
1682 | unsigned int instruction; | |
1683 | va_start(ap,exception); | |
1684 | instruction = va_arg(ap,unsigned int); | |
1685 | va_end(ap); | |
1686 | /* Check for our special terminating BREAK: */ | |
1687 | if ((instruction & 0x03FFFFC0) == 0x03ff0000) { | |
1688 | sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, cia, | |
1689 | sim_exited, (unsigned int)(A0 & 0xFFFFFFFF)); | |
1690 | } | |
1691 | } | |
1692 | if (STATE & simDELAYSLOT) | |
1693 | PC = cia - 4; /* reference the branch instruction */ | |
1694 | else | |
1695 | PC = cia; | |
1696 | sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, cia, | |
1697 | sim_stopped, SIM_SIGTRAP); | |
1698 | ||
1699 | default: | |
1700 | /* Store exception code into current exception id variable (used | |
1701 | by exit code): */ | |
1702 | ||
1703 | /* TODO: If not simulating exceptions then stop the simulator | |
1704 | execution. At the moment we always stop the simulation. */ | |
1705 | ||
1706 | /* See figure 5-17 for an outline of the code below */ | |
1707 | if (! (SR & status_EXL)) | |
1708 | { | |
1709 | CAUSE = (exception << 2); | |
1710 | if (STATE & simDELAYSLOT) | |
1711 | { | |
1712 | STATE &= ~simDELAYSLOT; | |
1713 | CAUSE |= cause_BD; | |
1714 | EPC = (cia - 4); /* reference the branch instruction */ | |
1715 | } | |
1716 | else | |
1717 | EPC = cia; | |
1718 | /* FIXME: TLB et.al. */ | |
1719 | vector = 0x180; | |
1720 | } | |
1721 | else | |
1722 | { | |
1723 | CAUSE = (exception << 2); | |
1724 | vector = 0x180; | |
1725 | } | |
1726 | SR |= status_EXL; | |
1727 | /* Store exception code into current exception id variable (used | |
1728 | by exit code): */ | |
1729 | if (SR & status_BEV) | |
1730 | PC = (signed)0xBFC00200 + 0x180; | |
1731 | else | |
1732 | PC = (signed)0x80000000 + 0x180; | |
1733 | ||
1734 | switch ((CAUSE >> 2) & 0x1F) | |
1735 | { | |
1736 | case Interrupt: | |
1737 | /* Interrupts arrive during event processing, no need to | |
1738 | restart */ | |
1739 | return; | |
1740 | ||
1741 | case TLBModification: | |
1742 | case TLBLoad: | |
1743 | case TLBStore: | |
1744 | case AddressLoad: | |
1745 | case AddressStore: | |
1746 | case InstructionFetch: | |
1747 | case DataReference: | |
1748 | /* The following is so that the simulator will continue from the | |
1749 | exception address on breakpoint operations. */ | |
1750 | PC = EPC; | |
1751 | sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA, | |
1752 | sim_stopped, SIM_SIGBUS); | |
1753 | ||
1754 | case ReservedInstruction: | |
1755 | case CoProcessorUnusable: | |
1756 | PC = EPC; | |
1757 | sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA, | |
1758 | sim_stopped, SIM_SIGILL); | |
1759 | ||
1760 | case IntegerOverflow: | |
1761 | case FPE: | |
1762 | sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA, | |
1763 | sim_stopped, SIM_SIGFPE); | |
1764 | ||
1765 | case Trap: | |
1766 | case Watch: | |
1767 | case SystemCall: | |
1768 | PC = EPC; | |
1769 | sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA, | |
1770 | sim_stopped, SIM_SIGTRAP); | |
1771 | ||
1772 | case BreakPoint: | |
1773 | PC = EPC; | |
1774 | sim_engine_abort (sd, STATE_CPU (sd, 0), NULL_CIA, | |
1775 | "FATAL: Should not encounter a breakpoint\n"); | |
1776 | ||
1777 | default : /* Unknown internal exception */ | |
1778 | PC = EPC; | |
1779 | sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA, | |
1780 | sim_stopped, SIM_SIGABRT); | |
1781 | ||
1782 | } | |
1783 | ||
1784 | case SimulatorFault: | |
1785 | { | |
1786 | va_list ap; | |
1787 | char *msg; | |
1788 | va_start(ap,exception); | |
1789 | msg = va_arg(ap,char *); | |
1790 | va_end(ap); | |
1791 | sim_engine_abort (sd, STATE_CPU (sd, 0), NULL_CIA, | |
1792 | "FATAL: Simulator error \"%s\"\n",msg); | |
1793 | } | |
1794 | } | |
1795 | ||
1796 | return; | |
1797 | } | |
1798 | ||
1799 | #if defined(WARN_RESULT) | |
1800 | /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */ | |
1801 | /* This function indicates that the result of the operation is | |
1802 | undefined. However, this should not affect the instruction | |
1803 | stream. All that is meant to happen is that the destination | |
1804 | register is set to an undefined result. To keep the simulator | |
1805 | simple, we just don't bother updating the destination register, so | |
1806 | the overall result will be undefined. If desired we can stop the | |
1807 | simulator by raising a pseudo-exception. */ | |
1808 | #define UndefinedResult() undefined_result (sd,cia) | |
1809 | static void | |
1810 | undefined_result(sd,cia) | |
1811 | SIM_DESC sd; | |
1812 | address_word cia; | |
1813 | { | |
1814 | sim_io_eprintf(sd,"UndefinedResult: PC = 0x%s\n",pr_addr(cia)); | |
1815 | #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */ | |
1816 | state |= simSTOP; | |
1817 | #endif | |
1818 | return; | |
1819 | } | |
1820 | #endif /* WARN_RESULT */ | |
1821 | ||
1822 | void | |
1823 | cache_op(sd,cia,op,pAddr,vAddr,instruction) | |
1824 | SIM_DESC sd; | |
1825 | address_word cia; | |
1826 | int op; | |
1827 | address_word pAddr; | |
1828 | address_word vAddr; | |
1829 | unsigned int instruction; | |
1830 | { | |
1831 | #if 1 /* stop warning message being displayed (we should really just remove the code) */ | |
1832 | static int icache_warning = 1; | |
1833 | static int dcache_warning = 1; | |
1834 | #else | |
1835 | static int icache_warning = 0; | |
1836 | static int dcache_warning = 0; | |
1837 | #endif | |
1838 | ||
1839 | /* If CP0 is not useable (User or Supervisor mode) and the CP0 | |
1840 | enable bit in the Status Register is clear - a coprocessor | |
1841 | unusable exception is taken. */ | |
1842 | #if 0 | |
1843 | sim_io_printf(sd,"TODO: Cache availability checking (PC = 0x%s)\n",pr_addr(cia)); | |
1844 | #endif | |
1845 | ||
1846 | switch (op & 0x3) { | |
1847 | case 0: /* instruction cache */ | |
1848 | switch (op >> 2) { | |
1849 | case 0: /* Index Invalidate */ | |
1850 | case 1: /* Index Load Tag */ | |
1851 | case 2: /* Index Store Tag */ | |
1852 | case 4: /* Hit Invalidate */ | |
1853 | case 5: /* Fill */ | |
1854 | case 6: /* Hit Writeback */ | |
1855 | if (!icache_warning) | |
1856 | { | |
1857 | sim_io_eprintf(sd,"Instruction CACHE operation %d to be coded\n",(op >> 2)); | |
1858 | icache_warning = 1; | |
1859 | } | |
1860 | break; | |
1861 | ||
1862 | default: | |
1863 | SignalException(ReservedInstruction,instruction); | |
1864 | break; | |
1865 | } | |
1866 | break; | |
1867 | ||
1868 | case 1: /* data cache */ | |
1869 | switch (op >> 2) { | |
1870 | case 0: /* Index Writeback Invalidate */ | |
1871 | case 1: /* Index Load Tag */ | |
1872 | case 2: /* Index Store Tag */ | |
1873 | case 3: /* Create Dirty */ | |
1874 | case 4: /* Hit Invalidate */ | |
1875 | case 5: /* Hit Writeback Invalidate */ | |
1876 | case 6: /* Hit Writeback */ | |
1877 | if (!dcache_warning) | |
1878 | { | |
1879 | sim_io_eprintf(sd,"Data CACHE operation %d to be coded\n",(op >> 2)); | |
1880 | dcache_warning = 1; | |
1881 | } | |
1882 | break; | |
1883 | ||
1884 | default: | |
1885 | SignalException(ReservedInstruction,instruction); | |
1886 | break; | |
1887 | } | |
1888 | break; | |
1889 | ||
1890 | default: /* unrecognised cache ID */ | |
1891 | SignalException(ReservedInstruction,instruction); | |
1892 | break; | |
1893 | } | |
1894 | ||
1895 | return; | |
1896 | } | |
1897 | ||
1898 | /*-- FPU support routines ---------------------------------------------------*/ | |
1899 | ||
1900 | #if defined(HASFPU) /* Only needed when building FPU aware simulators */ | |
1901 | ||
1902 | /* Numbers are held in normalized form. The SINGLE and DOUBLE binary | |
1903 | formats conform to ANSI/IEEE Std 754-1985. */ | |
1904 | /* SINGLE precision floating: | |
1905 | * seeeeeeeefffffffffffffffffffffff | |
1906 | * s = 1bit = sign | |
1907 | * e = 8bits = exponent | |
1908 | * f = 23bits = fraction | |
1909 | */ | |
1910 | /* SINGLE precision fixed: | |
1911 | * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii | |
1912 | * s = 1bit = sign | |
1913 | * i = 31bits = integer | |
1914 | */ | |
1915 | /* DOUBLE precision floating: | |
1916 | * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff | |
1917 | * s = 1bit = sign | |
1918 | * e = 11bits = exponent | |
1919 | * f = 52bits = fraction | |
1920 | */ | |
1921 | /* DOUBLE precision fixed: | |
1922 | * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii | |
1923 | * s = 1bit = sign | |
1924 | * i = 63bits = integer | |
1925 | */ | |
1926 | ||
1927 | /* Extract sign-bit: */ | |
1928 | #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0) | |
1929 | #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0) | |
1930 | /* Extract biased exponent: */ | |
1931 | #define FP_S_be(v) (((v) >> 23) & 0xFF) | |
1932 | #define FP_D_be(v) (((v) >> 52) & 0x7FF) | |
1933 | /* Extract unbiased Exponent: */ | |
1934 | #define FP_S_e(v) (FP_S_be(v) - 0x7F) | |
1935 | #define FP_D_e(v) (FP_D_be(v) - 0x3FF) | |
1936 | /* Extract complete fraction field: */ | |
1937 | #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23)) | |
1938 | #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52)) | |
1939 | /* Extract numbered fraction bit: */ | |
1940 | #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0) | |
1941 | #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0) | |
1942 | ||
1943 | /* Explicit QNaN values used when value required: */ | |
1944 | #define FPQNaN_SINGLE (0x7FBFFFFF) | |
1945 | #define FPQNaN_WORD (0x7FFFFFFF) | |
1946 | #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF) | |
1947 | #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF) | |
1948 | ||
1949 | /* Explicit Infinity values used when required: */ | |
1950 | #define FPINF_SINGLE (0x7F800000) | |
1951 | #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000) | |
1952 | ||
1953 | #if 1 /* def DEBUG */ | |
1954 | #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor"))) | |
1955 | #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>")))))) | |
1956 | #endif /* DEBUG */ | |
1957 | ||
1958 | uword64 | |
1959 | value_fpr(sd,cia,fpr,fmt) | |
1960 | SIM_DESC sd; | |
1961 | address_word cia; | |
1962 | int fpr; | |
1963 | FP_formats fmt; | |
1964 | { | |
1965 | uword64 value = 0; | |
1966 | int err = 0; | |
1967 | ||
1968 | /* Treat unused register values, as fixed-point 64bit values: */ | |
1969 | if ((fmt == fmt_uninterpreted) || (fmt == fmt_unknown)) | |
1970 | #if 1 | |
1971 | /* If request to read data as "uninterpreted", then use the current | |
1972 | encoding: */ | |
1973 | fmt = FPR_STATE[fpr]; | |
1974 | #else | |
1975 | fmt = fmt_long; | |
1976 | #endif | |
1977 | ||
1978 | /* For values not yet accessed, set to the desired format: */ | |
1979 | if (FPR_STATE[fpr] == fmt_uninterpreted) { | |
1980 | FPR_STATE[fpr] = fmt; | |
1981 | #ifdef DEBUG | |
1982 | printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr,DOFMT(fmt)); | |
1983 | #endif /* DEBUG */ | |
1984 | } | |
1985 | if (fmt != FPR_STATE[fpr]) { | |
1986 | sim_io_eprintf(sd,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr,DOFMT(FPR_STATE[fpr]),DOFMT(fmt),pr_addr(cia)); | |
1987 | FPR_STATE[fpr] = fmt_unknown; | |
1988 | } | |
1989 | ||
1990 | if (FPR_STATE[fpr] == fmt_unknown) { | |
1991 | /* Set QNaN value: */ | |
1992 | switch (fmt) { | |
1993 | case fmt_single: | |
1994 | value = FPQNaN_SINGLE; | |
1995 | break; | |
1996 | ||
1997 | case fmt_double: | |
1998 | value = FPQNaN_DOUBLE; | |
1999 | break; | |
2000 | ||
2001 | case fmt_word: | |
2002 | value = FPQNaN_WORD; | |
2003 | break; | |
2004 | ||
2005 | case fmt_long: | |
2006 | value = FPQNaN_LONG; | |
2007 | break; | |
2008 | ||
2009 | default: | |
2010 | err = -1; | |
2011 | break; | |
2012 | } | |
2013 | } else if (SizeFGR() == 64) { | |
2014 | switch (fmt) { | |
2015 | case fmt_single: | |
2016 | case fmt_word: | |
2017 | value = (FGR[fpr] & 0xFFFFFFFF); | |
2018 | break; | |
2019 | ||
2020 | case fmt_uninterpreted: | |
2021 | case fmt_double: | |
2022 | case fmt_long: | |
2023 | value = FGR[fpr]; | |
2024 | break; | |
2025 | ||
2026 | default : | |
2027 | err = -1; | |
2028 | break; | |
2029 | } | |
2030 | } else { | |
2031 | switch (fmt) { | |
2032 | case fmt_single: | |
2033 | case fmt_word: | |
2034 | value = (FGR[fpr] & 0xFFFFFFFF); | |
2035 | break; | |
2036 | ||
2037 | case fmt_uninterpreted: | |
2038 | case fmt_double: | |
2039 | case fmt_long: | |
2040 | if ((fpr & 1) == 0) { /* even registers only */ | |
2041 | value = ((((uword64)FGR[fpr+1]) << 32) | (FGR[fpr] & 0xFFFFFFFF)); | |
2042 | } else { | |
2043 | SignalException(ReservedInstruction,0); | |
2044 | } | |
2045 | break; | |
2046 | ||
2047 | default : | |
2048 | err = -1; | |
2049 | break; | |
2050 | } | |
2051 | } | |
2052 | ||
2053 | if (err) | |
2054 | SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()"); | |
2055 | ||
2056 | #ifdef DEBUG | |
2057 | printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR()); | |
2058 | #endif /* DEBUG */ | |
2059 | ||
2060 | return(value); | |
2061 | } | |
2062 | ||
2063 | void | |
2064 | store_fpr(sd,cia,fpr,fmt,value) | |
2065 | SIM_DESC sd; | |
2066 | address_word cia; | |
2067 | int fpr; | |
2068 | FP_formats fmt; | |
2069 | uword64 value; | |
2070 | { | |
2071 | int err = 0; | |
2072 | ||
2073 | #ifdef DEBUG | |
2074 | printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR()); | |
2075 | #endif /* DEBUG */ | |
2076 | ||
2077 | if (SizeFGR() == 64) { | |
2078 | switch (fmt) { | |
2079 | case fmt_uninterpreted_32: | |
2080 | fmt = fmt_uninterpreted; | |
2081 | case fmt_single : | |
2082 | case fmt_word : | |
2083 | FGR[fpr] = (((uword64)0xDEADC0DE << 32) | (value & 0xFFFFFFFF)); | |
2084 | FPR_STATE[fpr] = fmt; | |
2085 | break; | |
2086 | ||
2087 | case fmt_uninterpreted_64: | |
2088 | fmt = fmt_uninterpreted; | |
2089 | case fmt_uninterpreted: | |
2090 | case fmt_double : | |
2091 | case fmt_long : | |
2092 | FGR[fpr] = value; | |
2093 | FPR_STATE[fpr] = fmt; | |
2094 | break; | |
2095 | ||
2096 | default : | |
2097 | FPR_STATE[fpr] = fmt_unknown; | |
2098 | err = -1; | |
2099 | break; | |
2100 | } | |
2101 | } else { | |
2102 | switch (fmt) { | |
2103 | case fmt_uninterpreted_32: | |
2104 | fmt = fmt_uninterpreted; | |
2105 | case fmt_single : | |
2106 | case fmt_word : | |
2107 | FGR[fpr] = (value & 0xFFFFFFFF); | |
2108 | FPR_STATE[fpr] = fmt; | |
2109 | break; | |
2110 | ||
2111 | case fmt_uninterpreted_64: | |
2112 | fmt = fmt_uninterpreted; | |
2113 | case fmt_uninterpreted: | |
2114 | case fmt_double : | |
2115 | case fmt_long : | |
2116 | if ((fpr & 1) == 0) { /* even register number only */ | |
2117 | FGR[fpr+1] = (value >> 32); | |
2118 | FGR[fpr] = (value & 0xFFFFFFFF); | |
2119 | FPR_STATE[fpr + 1] = fmt; | |
2120 | FPR_STATE[fpr] = fmt; | |
2121 | } else { | |
2122 | FPR_STATE[fpr] = fmt_unknown; | |
2123 | FPR_STATE[fpr + 1] = fmt_unknown; | |
2124 | SignalException(ReservedInstruction,0); | |
2125 | } | |
2126 | break; | |
2127 | ||
2128 | default : | |
2129 | FPR_STATE[fpr] = fmt_unknown; | |
2130 | err = -1; | |
2131 | break; | |
2132 | } | |
2133 | } | |
2134 | #if defined(WARN_RESULT) | |
2135 | else | |
2136 | UndefinedResult(); | |
2137 | #endif /* WARN_RESULT */ | |
2138 | ||
2139 | if (err) | |
2140 | SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()"); | |
2141 | ||
2142 | #ifdef DEBUG | |
2143 | printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr,pr_addr(FGR[fpr]),DOFMT(fmt)); | |
2144 | #endif /* DEBUG */ | |
2145 | ||
2146 | return; | |
2147 | } | |
2148 | ||
2149 | int | |
2150 | NaN(op,fmt) | |
2151 | uword64 op; | |
2152 | FP_formats fmt; | |
2153 | { | |
2154 | int boolean = 0; | |
2155 | switch (fmt) { | |
2156 | case fmt_single: | |
2157 | case fmt_word: | |
2158 | { | |
2159 | sim_fpu wop; | |
2160 | sim_fpu_32to (&wop, op); | |
2161 | boolean = sim_fpu_is_nan (&wop); | |
2162 | break; | |
2163 | } | |
2164 | case fmt_double: | |
2165 | case fmt_long: | |
2166 | { | |
2167 | sim_fpu wop; | |
2168 | sim_fpu_64to (&wop, op); | |
2169 | boolean = sim_fpu_is_nan (&wop); | |
2170 | break; | |
2171 | } | |
2172 | default: | |
2173 | fprintf (stderr, "Bad switch\n"); | |
2174 | abort (); | |
2175 | } | |
2176 | ||
2177 | #ifdef DEBUG | |
2178 | printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt)); | |
2179 | #endif /* DEBUG */ | |
2180 | ||
2181 | return(boolean); | |
2182 | } | |
2183 | ||
2184 | int | |
2185 | Infinity(op,fmt) | |
2186 | uword64 op; | |
2187 | FP_formats fmt; | |
2188 | { | |
2189 | int boolean = 0; | |
2190 | ||
2191 | #ifdef DEBUG | |
2192 | printf("DBG: Infinity: format %s 0x%s\n",DOFMT(fmt),pr_addr(op)); | |
2193 | #endif /* DEBUG */ | |
2194 | ||
2195 | switch (fmt) { | |
2196 | case fmt_single: | |
2197 | { | |
2198 | sim_fpu wop; | |
2199 | sim_fpu_32to (&wop, op); | |
2200 | boolean = sim_fpu_is_infinity (&wop); | |
2201 | break; | |
2202 | } | |
2203 | case fmt_double: | |
2204 | { | |
2205 | sim_fpu wop; | |
2206 | sim_fpu_64to (&wop, op); | |
2207 | boolean = sim_fpu_is_infinity (&wop); | |
2208 | break; | |
2209 | } | |
2210 | default: | |
2211 | printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt)); | |
2212 | break; | |
2213 | } | |
2214 | ||
2215 | #ifdef DEBUG | |
2216 | printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt)); | |
2217 | #endif /* DEBUG */ | |
2218 | ||
2219 | return(boolean); | |
2220 | } | |
2221 | ||
2222 | int | |
2223 | Less(op1,op2,fmt) | |
2224 | uword64 op1; | |
2225 | uword64 op2; | |
2226 | FP_formats fmt; | |
2227 | { | |
2228 | int boolean = 0; | |
2229 | ||
2230 | /* Argument checking already performed by the FPCOMPARE code */ | |
2231 | ||
2232 | #ifdef DEBUG | |
2233 | printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); | |
2234 | #endif /* DEBUG */ | |
2235 | ||
2236 | /* The format type should already have been checked: */ | |
2237 | switch (fmt) { | |
2238 | case fmt_single: | |
2239 | { | |
2240 | sim_fpu wop1; | |
2241 | sim_fpu wop2; | |
2242 | sim_fpu_32to (&wop1, op1); | |
2243 | sim_fpu_32to (&wop2, op2); | |
2244 | boolean = sim_fpu_is_lt (&wop1, &wop2); | |
2245 | break; | |
2246 | } | |
2247 | case fmt_double: | |
2248 | { | |
2249 | sim_fpu wop1; | |
2250 | sim_fpu wop2; | |
2251 | sim_fpu_64to (&wop1, op1); | |
2252 | sim_fpu_64to (&wop2, op2); | |
2253 | boolean = sim_fpu_is_lt (&wop1, &wop2); | |
2254 | break; | |
2255 | } | |
2256 | default: | |
2257 | fprintf (stderr, "Bad switch\n"); | |
2258 | abort (); | |
2259 | } | |
2260 | ||
2261 | #ifdef DEBUG | |
2262 | printf("DBG: Less: returning %d (format = %s)\n",boolean,DOFMT(fmt)); | |
2263 | #endif /* DEBUG */ | |
2264 | ||
2265 | return(boolean); | |
2266 | } | |
2267 | ||
2268 | int | |
2269 | Equal(op1,op2,fmt) | |
2270 | uword64 op1; | |
2271 | uword64 op2; | |
2272 | FP_formats fmt; | |
2273 | { | |
2274 | int boolean = 0; | |
2275 | ||
2276 | /* Argument checking already performed by the FPCOMPARE code */ | |
2277 | ||
2278 | #ifdef DEBUG | |
2279 | printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); | |
2280 | #endif /* DEBUG */ | |
2281 | ||
2282 | /* The format type should already have been checked: */ | |
2283 | switch (fmt) { | |
2284 | case fmt_single: | |
2285 | { | |
2286 | sim_fpu wop1; | |
2287 | sim_fpu wop2; | |
2288 | sim_fpu_32to (&wop1, op1); | |
2289 | sim_fpu_32to (&wop2, op2); | |
2290 | boolean = sim_fpu_is_eq (&wop1, &wop2); | |
2291 | break; | |
2292 | } | |
2293 | case fmt_double: | |
2294 | { | |
2295 | sim_fpu wop1; | |
2296 | sim_fpu wop2; | |
2297 | sim_fpu_64to (&wop1, op1); | |
2298 | sim_fpu_64to (&wop2, op2); | |
2299 | boolean = sim_fpu_is_eq (&wop1, &wop2); | |
2300 | break; | |
2301 | } | |
2302 | default: | |
2303 | fprintf (stderr, "Bad switch\n"); | |
2304 | abort (); | |
2305 | } | |
2306 | ||
2307 | #ifdef DEBUG | |
2308 | printf("DBG: Equal: returning %d (format = %s)\n",boolean,DOFMT(fmt)); | |
2309 | #endif /* DEBUG */ | |
2310 | ||
2311 | return(boolean); | |
2312 | } | |
2313 | ||
2314 | uword64 | |
2315 | AbsoluteValue(op,fmt) | |
2316 | uword64 op; | |
2317 | FP_formats fmt; | |
2318 | { | |
2319 | uword64 result = 0; | |
2320 | ||
2321 | #ifdef DEBUG | |
2322 | printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); | |
2323 | #endif /* DEBUG */ | |
2324 | ||
2325 | /* The format type should already have been checked: */ | |
2326 | switch (fmt) { | |
2327 | case fmt_single: | |
2328 | { | |
2329 | sim_fpu wop; | |
2330 | unsigned32 ans; | |
2331 | sim_fpu_32to (&wop, op); | |
2332 | sim_fpu_abs (&wop, &wop); | |
2333 | sim_fpu_to32 (&ans, &wop); | |
2334 | result = ans; | |
2335 | break; | |
2336 | } | |
2337 | case fmt_double: | |
2338 | { | |
2339 | sim_fpu wop; | |
2340 | unsigned64 ans; | |
2341 | sim_fpu_64to (&wop, op); | |
2342 | sim_fpu_abs (&wop, &wop); | |
2343 | sim_fpu_to64 (&ans, &wop); | |
2344 | result = ans; | |
2345 | break; | |
2346 | } | |
2347 | default: | |
2348 | fprintf (stderr, "Bad switch\n"); | |
2349 | abort (); | |
2350 | } | |
2351 | ||
2352 | return(result); | |
2353 | } | |
2354 | ||
2355 | uword64 | |
2356 | Negate(op,fmt) | |
2357 | uword64 op; | |
2358 | FP_formats fmt; | |
2359 | { | |
2360 | uword64 result = 0; | |
2361 | ||
2362 | #ifdef DEBUG | |
2363 | printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); | |
2364 | #endif /* DEBUG */ | |
2365 | ||
2366 | /* The format type should already have been checked: */ | |
2367 | switch (fmt) { | |
2368 | case fmt_single: | |
2369 | { | |
2370 | sim_fpu wop; | |
2371 | unsigned32 ans; | |
2372 | sim_fpu_32to (&wop, op); | |
2373 | sim_fpu_neg (&wop, &wop); | |
2374 | sim_fpu_to32 (&ans, &wop); | |
2375 | result = ans; | |
2376 | break; | |
2377 | } | |
2378 | case fmt_double: | |
2379 | { | |
2380 | sim_fpu wop; | |
2381 | unsigned64 ans; | |
2382 | sim_fpu_64to (&wop, op); | |
2383 | sim_fpu_neg (&wop, &wop); | |
2384 | sim_fpu_to64 (&ans, &wop); | |
2385 | result = ans; | |
2386 | break; | |
2387 | } | |
2388 | default: | |
2389 | fprintf (stderr, "Bad switch\n"); | |
2390 | abort (); | |
2391 | } | |
2392 | ||
2393 | return(result); | |
2394 | } | |
2395 | ||
2396 | uword64 | |
2397 | Add(op1,op2,fmt) | |
2398 | uword64 op1; | |
2399 | uword64 op2; | |
2400 | FP_formats fmt; | |
2401 | { | |
2402 | uword64 result = 0; | |
2403 | ||
2404 | #ifdef DEBUG | |
2405 | printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); | |
2406 | #endif /* DEBUG */ | |
2407 | ||
2408 | /* The registers must specify FPRs valid for operands of type | |
2409 | "fmt". If they are not valid, the result is undefined. */ | |
2410 | ||
2411 | /* The format type should already have been checked: */ | |
2412 | switch (fmt) { | |
2413 | case fmt_single: | |
2414 | { | |
2415 | sim_fpu wop1; | |
2416 | sim_fpu wop2; | |
2417 | sim_fpu ans; | |
2418 | unsigned32 res; | |
2419 | sim_fpu_32to (&wop1, op1); | |
2420 | sim_fpu_32to (&wop2, op2); | |
2421 | sim_fpu_add (&ans, &wop1, &wop2); | |
2422 | sim_fpu_to32 (&res, &ans); | |
2423 | result = res; | |
2424 | break; | |
2425 | } | |
2426 | case fmt_double: | |
2427 | { | |
2428 | sim_fpu wop1; | |
2429 | sim_fpu wop2; | |
2430 | sim_fpu ans; | |
2431 | unsigned64 res; | |
2432 | sim_fpu_64to (&wop1, op1); | |
2433 | sim_fpu_64to (&wop2, op2); | |
2434 | sim_fpu_add (&ans, &wop1, &wop2); | |
2435 | sim_fpu_to64 (&res, &ans); | |
2436 | result = res; | |
2437 | break; | |
2438 | } | |
2439 | default: | |
2440 | fprintf (stderr, "Bad switch\n"); | |
2441 | abort (); | |
2442 | } | |
2443 | ||
2444 | #ifdef DEBUG | |
2445 | printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); | |
2446 | #endif /* DEBUG */ | |
2447 | ||
2448 | return(result); | |
2449 | } | |
2450 | ||
2451 | uword64 | |
2452 | Sub(op1,op2,fmt) | |
2453 | uword64 op1; | |
2454 | uword64 op2; | |
2455 | FP_formats fmt; | |
2456 | { | |
2457 | uword64 result = 0; | |
2458 | ||
2459 | #ifdef DEBUG | |
2460 | printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); | |
2461 | #endif /* DEBUG */ | |
2462 | ||
2463 | /* The registers must specify FPRs valid for operands of type | |
2464 | "fmt". If they are not valid, the result is undefined. */ | |
2465 | ||
2466 | /* The format type should already have been checked: */ | |
2467 | switch (fmt) { | |
2468 | case fmt_single: | |
2469 | { | |
2470 | sim_fpu wop1; | |
2471 | sim_fpu wop2; | |
2472 | sim_fpu ans; | |
2473 | unsigned32 res; | |
2474 | sim_fpu_32to (&wop1, op1); | |
2475 | sim_fpu_32to (&wop2, op2); | |
2476 | sim_fpu_sub (&ans, &wop1, &wop2); | |
2477 | sim_fpu_to32 (&res, &ans); | |
2478 | result = res; | |
2479 | } | |
2480 | break; | |
2481 | case fmt_double: | |
2482 | { | |
2483 | sim_fpu wop1; | |
2484 | sim_fpu wop2; | |
2485 | sim_fpu ans; | |
2486 | unsigned64 res; | |
2487 | sim_fpu_64to (&wop1, op1); | |
2488 | sim_fpu_64to (&wop2, op2); | |
2489 | sim_fpu_sub (&ans, &wop1, &wop2); | |
2490 | sim_fpu_to64 (&res, &ans); | |
2491 | result = res; | |
2492 | } | |
2493 | break; | |
2494 | default: | |
2495 | fprintf (stderr, "Bad switch\n"); | |
2496 | abort (); | |
2497 | } | |
2498 | ||
2499 | #ifdef DEBUG | |
2500 | printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); | |
2501 | #endif /* DEBUG */ | |
2502 | ||
2503 | return(result); | |
2504 | } | |
2505 | ||
2506 | uword64 | |
2507 | Multiply(op1,op2,fmt) | |
2508 | uword64 op1; | |
2509 | uword64 op2; | |
2510 | FP_formats fmt; | |
2511 | { | |
2512 | uword64 result = 0; | |
2513 | ||
2514 | #ifdef DEBUG | |
2515 | printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); | |
2516 | #endif /* DEBUG */ | |
2517 | ||
2518 | /* The registers must specify FPRs valid for operands of type | |
2519 | "fmt". If they are not valid, the result is undefined. */ | |
2520 | ||
2521 | /* The format type should already have been checked: */ | |
2522 | switch (fmt) { | |
2523 | case fmt_single: | |
2524 | { | |
2525 | sim_fpu wop1; | |
2526 | sim_fpu wop2; | |
2527 | sim_fpu ans; | |
2528 | unsigned32 res; | |
2529 | sim_fpu_32to (&wop1, op1); | |
2530 | sim_fpu_32to (&wop2, op2); | |
2531 | sim_fpu_mul (&ans, &wop1, &wop2); | |
2532 | sim_fpu_to32 (&res, &ans); | |
2533 | result = res; | |
2534 | break; | |
2535 | } | |
2536 | case fmt_double: | |
2537 | { | |
2538 | sim_fpu wop1; | |
2539 | sim_fpu wop2; | |
2540 | sim_fpu ans; | |
2541 | unsigned64 res; | |
2542 | sim_fpu_64to (&wop1, op1); | |
2543 | sim_fpu_64to (&wop2, op2); | |
2544 | sim_fpu_mul (&ans, &wop1, &wop2); | |
2545 | sim_fpu_to64 (&res, &ans); | |
2546 | result = res; | |
2547 | break; | |
2548 | } | |
2549 | default: | |
2550 | fprintf (stderr, "Bad switch\n"); | |
2551 | abort (); | |
2552 | } | |
2553 | ||
2554 | #ifdef DEBUG | |
2555 | printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); | |
2556 | #endif /* DEBUG */ | |
2557 | ||
2558 | return(result); | |
2559 | } | |
2560 | ||
2561 | uword64 | |
2562 | Divide(op1,op2,fmt) | |
2563 | uword64 op1; | |
2564 | uword64 op2; | |
2565 | FP_formats fmt; | |
2566 | { | |
2567 | uword64 result = 0; | |
2568 | ||
2569 | #ifdef DEBUG | |
2570 | printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); | |
2571 | #endif /* DEBUG */ | |
2572 | ||
2573 | /* The registers must specify FPRs valid for operands of type | |
2574 | "fmt". If they are not valid, the result is undefined. */ | |
2575 | ||
2576 | /* The format type should already have been checked: */ | |
2577 | switch (fmt) { | |
2578 | case fmt_single: | |
2579 | { | |
2580 | sim_fpu wop1; | |
2581 | sim_fpu wop2; | |
2582 | sim_fpu ans; | |
2583 | unsigned32 res; | |
2584 | sim_fpu_32to (&wop1, op1); | |
2585 | sim_fpu_32to (&wop2, op2); | |
2586 | sim_fpu_div (&ans, &wop1, &wop2); | |
2587 | sim_fpu_to32 (&res, &ans); | |
2588 | result = res; | |
2589 | break; | |
2590 | } | |
2591 | case fmt_double: | |
2592 | { | |
2593 | sim_fpu wop1; | |
2594 | sim_fpu wop2; | |
2595 | sim_fpu ans; | |
2596 | unsigned64 res; | |
2597 | sim_fpu_64to (&wop1, op1); | |
2598 | sim_fpu_64to (&wop2, op2); | |
2599 | sim_fpu_div (&ans, &wop1, &wop2); | |
2600 | sim_fpu_to64 (&res, &ans); | |
2601 | result = res; | |
2602 | break; | |
2603 | } | |
2604 | default: | |
2605 | fprintf (stderr, "Bad switch\n"); | |
2606 | abort (); | |
2607 | } | |
2608 | ||
2609 | #ifdef DEBUG | |
2610 | printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); | |
2611 | #endif /* DEBUG */ | |
2612 | ||
2613 | return(result); | |
2614 | } | |
2615 | ||
2616 | uword64 UNUSED | |
2617 | Recip(op,fmt) | |
2618 | uword64 op; | |
2619 | FP_formats fmt; | |
2620 | { | |
2621 | uword64 result = 0; | |
2622 | ||
2623 | #ifdef DEBUG | |
2624 | printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); | |
2625 | #endif /* DEBUG */ | |
2626 | ||
2627 | /* The registers must specify FPRs valid for operands of type | |
2628 | "fmt". If they are not valid, the result is undefined. */ | |
2629 | ||
2630 | /* The format type should already have been checked: */ | |
2631 | switch (fmt) { | |
2632 | case fmt_single: | |
2633 | { | |
2634 | sim_fpu wop; | |
2635 | sim_fpu ans; | |
2636 | unsigned32 res; | |
2637 | sim_fpu_32to (&wop, op); | |
2638 | sim_fpu_inv (&ans, &wop); | |
2639 | sim_fpu_to32 (&res, &ans); | |
2640 | result = res; | |
2641 | break; | |
2642 | } | |
2643 | case fmt_double: | |
2644 | { | |
2645 | sim_fpu wop; | |
2646 | sim_fpu ans; | |
2647 | unsigned64 res; | |
2648 | sim_fpu_64to (&wop, op); | |
2649 | sim_fpu_inv (&ans, &wop); | |
2650 | sim_fpu_to64 (&res, &ans); | |
2651 | result = res; | |
2652 | break; | |
2653 | } | |
2654 | default: | |
2655 | fprintf (stderr, "Bad switch\n"); | |
2656 | abort (); | |
2657 | } | |
2658 | ||
2659 | #ifdef DEBUG | |
2660 | printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); | |
2661 | #endif /* DEBUG */ | |
2662 | ||
2663 | return(result); | |
2664 | } | |
2665 | ||
2666 | uword64 | |
2667 | SquareRoot(op,fmt) | |
2668 | uword64 op; | |
2669 | FP_formats fmt; | |
2670 | { | |
2671 | uword64 result = 0; | |
2672 | ||
2673 | #ifdef DEBUG | |
2674 | printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); | |
2675 | #endif /* DEBUG */ | |
2676 | ||
2677 | /* The registers must specify FPRs valid for operands of type | |
2678 | "fmt". If they are not valid, the result is undefined. */ | |
2679 | ||
2680 | /* The format type should already have been checked: */ | |
2681 | switch (fmt) { | |
2682 | case fmt_single: | |
2683 | { | |
2684 | sim_fpu wop; | |
2685 | sim_fpu ans; | |
2686 | unsigned32 res; | |
2687 | sim_fpu_32to (&wop, op); | |
2688 | sim_fpu_sqrt (&ans, &wop); | |
2689 | sim_fpu_to32 (&res, &ans); | |
2690 | result = res; | |
2691 | break; | |
2692 | } | |
2693 | case fmt_double: | |
2694 | { | |
2695 | sim_fpu wop; | |
2696 | sim_fpu ans; | |
2697 | unsigned64 res; | |
2698 | sim_fpu_64to (&wop, op); | |
2699 | sim_fpu_sqrt (&ans, &wop); | |
2700 | sim_fpu_to64 (&res, &ans); | |
2701 | result = res; | |
2702 | break; | |
2703 | } | |
2704 | default: | |
2705 | fprintf (stderr, "Bad switch\n"); | |
2706 | abort (); | |
2707 | } | |
2708 | ||
2709 | #ifdef DEBUG | |
2710 | printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); | |
2711 | #endif /* DEBUG */ | |
2712 | ||
2713 | return(result); | |
2714 | } | |
2715 | ||
2716 | uword64 | |
2717 | convert(sd,cia,rm,op,from,to) | |
2718 | SIM_DESC sd; | |
2719 | address_word cia; | |
2720 | int rm; | |
2721 | uword64 op; | |
2722 | FP_formats from; | |
2723 | FP_formats to; | |
2724 | { | |
2725 | sim_fpu wop; | |
2726 | sim_fpu_round round; | |
2727 | unsigned32 result32; | |
2728 | unsigned64 result64; | |
2729 | ||
2730 | #ifdef DEBUG | |
2731 | printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm),pr_addr(op),DOFMT(from),DOFMT(to),pr_addr(IPC)); | |
2732 | #endif /* DEBUG */ | |
2733 | ||
2734 | switch (rm) | |
2735 | { | |
2736 | case FP_RM_NEAREST: | |
2737 | /* Round result to nearest representable value. When two | |
2738 | representable values are equally near, round to the value | |
2739 | that has a least significant bit of zero (i.e. is even). */ | |
2740 | round = sim_fpu_round_near; | |
2741 | break; | |
2742 | case FP_RM_TOZERO: | |
2743 | /* Round result to the value closest to, and not greater in | |
2744 | magnitude than, the result. */ | |
2745 | round = sim_fpu_round_zero; | |
2746 | break; | |
2747 | case FP_RM_TOPINF: | |
2748 | /* Round result to the value closest to, and not less than, | |
2749 | the result. */ | |
2750 | round = sim_fpu_round_up; | |
2751 | break; | |
2752 | ||
2753 | case FP_RM_TOMINF: | |
2754 | /* Round result to the value closest to, and not greater than, | |
2755 | the result. */ | |
2756 | round = sim_fpu_round_down; | |
2757 | break; | |
2758 | default: | |
2759 | round = 0; | |
2760 | fprintf (stderr, "Bad switch\n"); | |
2761 | abort (); | |
2762 | } | |
2763 | ||
2764 | /* Convert the input to sim_fpu internal format */ | |
2765 | switch (from) | |
2766 | { | |
2767 | case fmt_double: | |
2768 | sim_fpu_64to (&wop, op); | |
2769 | break; | |
2770 | case fmt_single: | |
2771 | sim_fpu_32to (&wop, op); | |
2772 | break; | |
2773 | case fmt_word: | |
2774 | sim_fpu_i32to (&wop, op, round); | |
2775 | break; | |
2776 | case fmt_long: | |
2777 | sim_fpu_i64to (&wop, op, round); | |
2778 | break; | |
2779 | default: | |
2780 | fprintf (stderr, "Bad switch\n"); | |
2781 | abort (); | |
2782 | } | |
2783 | ||
2784 | /* Convert sim_fpu format into the output */ | |
2785 | /* The value WOP is converted to the destination format, rounding | |
2786 | using mode RM. When the destination is a fixed-point format, then | |
2787 | a source value of Infinity, NaN or one which would round to an | |
2788 | integer outside the fixed point range then an IEEE Invalid | |
2789 | Operation condition is raised. */ | |
2790 | switch (to) | |
2791 | { | |
2792 | case fmt_single: | |
2793 | sim_fpu_round_32 (&wop, round, 0); | |
2794 | sim_fpu_to32 (&result32, &wop); | |
2795 | result64 = result32; | |
2796 | break; | |
2797 | case fmt_double: | |
2798 | sim_fpu_round_64 (&wop, round, 0); | |
2799 | sim_fpu_to64 (&result64, &wop); | |
2800 | break; | |
2801 | case fmt_word: | |
2802 | sim_fpu_to32i (&result32, &wop, round); | |
2803 | result64 = result32; | |
2804 | break; | |
2805 | case fmt_long: | |
2806 | sim_fpu_to64i (&result64, &wop, round); | |
2807 | break; | |
2808 | default: | |
2809 | result64 = 0; | |
2810 | fprintf (stderr, "Bad switch\n"); | |
2811 | abort (); | |
2812 | } | |
2813 | ||
2814 | #ifdef DEBUG | |
2815 | printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64),DOFMT(to)); | |
2816 | #endif /* DEBUG */ | |
2817 | ||
2818 | return(result64); | |
2819 | } | |
2820 | #endif /* HASFPU */ | |
2821 | ||
2822 | ||
2823 | /*-- co-processor support routines ------------------------------------------*/ | |
2824 | ||
2825 | static int UNUSED | |
2826 | CoProcPresent(coproc_number) | |
2827 | unsigned int coproc_number; | |
2828 | { | |
2829 | /* Return TRUE if simulator provides a model for the given co-processor number */ | |
2830 | return(0); | |
2831 | } | |
2832 | ||
2833 | void | |
2834 | cop_lw(sd,cia,coproc_num,coproc_reg,memword) | |
2835 | SIM_DESC sd; | |
2836 | address_word cia; | |
2837 | int coproc_num, coproc_reg; | |
2838 | unsigned int memword; | |
2839 | { | |
2840 | switch (coproc_num) { | |
2841 | #if defined(HASFPU) | |
2842 | case 1: | |
2843 | #ifdef DEBUG | |
2844 | printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword)); | |
2845 | #endif | |
2846 | StoreFPR(coproc_reg,fmt_word,(uword64)memword); | |
2847 | FPR_STATE[coproc_reg] = fmt_uninterpreted; | |
2848 | break; | |
2849 | #endif /* HASFPU */ | |
2850 | ||
2851 | default: | |
2852 | #if 0 /* this should be controlled by a configuration option */ | |
2853 | sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia)); | |
2854 | #endif | |
2855 | break; | |
2856 | } | |
2857 | ||
2858 | return; | |
2859 | } | |
2860 | ||
2861 | void | |
2862 | cop_ld(sd,cia,coproc_num,coproc_reg,memword) | |
2863 | SIM_DESC sd; | |
2864 | address_word cia; | |
2865 | int coproc_num, coproc_reg; | |
2866 | uword64 memword; | |
2867 | { | |
2868 | switch (coproc_num) { | |
2869 | #if defined(HASFPU) | |
2870 | case 1: | |
2871 | StoreFPR(coproc_reg,fmt_uninterpreted,memword); | |
2872 | break; | |
2873 | #endif /* HASFPU */ | |
2874 | ||
2875 | default: | |
2876 | #if 0 /* this message should be controlled by a configuration option */ | |
2877 | sim_io_printf(sd,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(memword),pr_addr(cia)); | |
2878 | #endif | |
2879 | break; | |
2880 | } | |
2881 | ||
2882 | return; | |
2883 | } | |
2884 | ||
2885 | unsigned int | |
2886 | cop_sw(sd,cia,coproc_num,coproc_reg) | |
2887 | SIM_DESC sd; | |
2888 | address_word cia; | |
2889 | int coproc_num, coproc_reg; | |
2890 | { | |
2891 | unsigned int value = 0; | |
2892 | ||
2893 | switch (coproc_num) { | |
2894 | #if defined(HASFPU) | |
2895 | case 1: | |
2896 | #if 1 | |
2897 | { | |
2898 | FP_formats hold; | |
2899 | hold = FPR_STATE[coproc_reg]; | |
2900 | FPR_STATE[coproc_reg] = fmt_word; | |
2901 | value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted); | |
2902 | FPR_STATE[coproc_reg] = hold; | |
2903 | } | |
2904 | #else | |
2905 | #if 1 | |
2906 | value = (unsigned int)ValueFPR(coproc_reg,FPR_STATE[coproc_reg]); | |
2907 | #else | |
2908 | #ifdef DEBUG | |
2909 | printf("DBG: COP_SW: reg in format %s (will be accessing as single)\n",DOFMT(FPR_STATE[coproc_reg])); | |
2910 | #endif /* DEBUG */ | |
2911 | value = (unsigned int)ValueFPR(coproc_reg,fmt_single); | |
2912 | #endif | |
2913 | #endif | |
2914 | break; | |
2915 | #endif /* HASFPU */ | |
2916 | ||
2917 | default: | |
2918 | #if 0 /* should be controlled by configuration option */ | |
2919 | sim_io_printf(sd,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia)); | |
2920 | #endif | |
2921 | break; | |
2922 | } | |
2923 | ||
2924 | return(value); | |
2925 | } | |
2926 | ||
2927 | uword64 | |
2928 | cop_sd(sd,cia,coproc_num,coproc_reg) | |
2929 | SIM_DESC sd; | |
2930 | address_word cia; | |
2931 | int coproc_num, coproc_reg; | |
2932 | { | |
2933 | uword64 value = 0; | |
2934 | switch (coproc_num) { | |
2935 | #if defined(HASFPU) | |
2936 | case 1: | |
2937 | #if 1 | |
2938 | value = ValueFPR(coproc_reg,fmt_uninterpreted); | |
2939 | #else | |
2940 | #if 1 | |
2941 | value = ValueFPR(coproc_reg,FPR_STATE[coproc_reg]); | |
2942 | #else | |
2943 | #ifdef DEBUG | |
2944 | printf("DBG: COP_SD: reg in format %s (will be accessing as double)\n",DOFMT(FPR_STATE[coproc_reg])); | |
2945 | #endif /* DEBUG */ | |
2946 | value = ValueFPR(coproc_reg,fmt_double); | |
2947 | #endif | |
2948 | #endif | |
2949 | break; | |
2950 | #endif /* HASFPU */ | |
2951 | ||
2952 | default: | |
2953 | #if 0 /* should be controlled by configuration option */ | |
2954 | sim_io_printf(sd,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia)); | |
2955 | #endif | |
2956 | break; | |
2957 | } | |
2958 | ||
2959 | return(value); | |
2960 | } | |
2961 | ||
2962 | void | |
2963 | decode_coproc(sd,cia,instruction) | |
2964 | SIM_DESC sd; | |
2965 | address_word cia; | |
2966 | unsigned int instruction; | |
2967 | { | |
2968 | int coprocnum = ((instruction >> 26) & 3); | |
2969 | ||
2970 | switch (coprocnum) | |
2971 | { | |
2972 | case 0: /* standard CPU control and cache registers */ | |
2973 | { | |
2974 | int code = ((instruction >> 21) & 0x1F); | |
2975 | /* R4000 Users Manual (second edition) lists the following CP0 | |
2976 | instructions: | |
2977 | DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000) | |
2978 | DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000) | |
2979 | MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000) | |
2980 | MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000) | |
2981 | TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001) | |
2982 | TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010) | |
2983 | TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110) | |
2984 | TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000) | |
2985 | CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii) | |
2986 | ERET Exception return (VR4100 = 01000010000000000000000000011000) | |
2987 | */ | |
2988 | if (((code == 0x00) || (code == 0x04)) && ((instruction & 0x7FF) == 0)) | |
2989 | { | |
2990 | int rt = ((instruction >> 16) & 0x1F); | |
2991 | int rd = ((instruction >> 11) & 0x1F); | |
2992 | ||
2993 | switch (rd) /* NOTEs: Standard CP0 registers */ | |
2994 | { | |
2995 | /* 0 = Index R4000 VR4100 VR4300 */ | |
2996 | /* 1 = Random R4000 VR4100 VR4300 */ | |
2997 | /* 2 = EntryLo0 R4000 VR4100 VR4300 */ | |
2998 | /* 3 = EntryLo1 R4000 VR4100 VR4300 */ | |
2999 | /* 4 = Context R4000 VR4100 VR4300 */ | |
3000 | /* 5 = PageMask R4000 VR4100 VR4300 */ | |
3001 | /* 6 = Wired R4000 VR4100 VR4300 */ | |
3002 | /* 8 = BadVAddr R4000 VR4100 VR4300 */ | |
3003 | /* 9 = Count R4000 VR4100 VR4300 */ | |
3004 | /* 10 = EntryHi R4000 VR4100 VR4300 */ | |
3005 | /* 11 = Compare R4000 VR4100 VR4300 */ | |
3006 | /* 12 = SR R4000 VR4100 VR4300 */ | |
3007 | case 12: | |
3008 | if (code == 0x00) | |
3009 | GPR[rt] = SR; | |
3010 | else | |
3011 | SR = GPR[rt]; | |
3012 | break; | |
3013 | /* 13 = Cause R4000 VR4100 VR4300 */ | |
3014 | case 13: | |
3015 | if (code == 0x00) | |
3016 | GPR[rt] = CAUSE; | |
3017 | else | |
3018 | CAUSE = GPR[rt]; | |
3019 | break; | |
3020 | /* 14 = EPC R4000 VR4100 VR4300 */ | |
3021 | /* 15 = PRId R4000 VR4100 VR4300 */ | |
3022 | #ifdef SUBTARGET_R3900 | |
3023 | /* 16 = Debug */ | |
3024 | case 16: | |
3025 | if (code == 0x00) | |
3026 | GPR[rt] = Debug; | |
3027 | else | |
3028 | Debug = GPR[rt]; | |
3029 | break; | |
3030 | #else | |
3031 | /* 16 = Config R4000 VR4100 VR4300 */ | |
3032 | case 16: | |
3033 | if (code == 0x00) | |
3034 | GPR[rt] = C0_CONFIG; | |
3035 | else | |
3036 | C0_CONFIG = GPR[rt]; | |
3037 | break; | |
3038 | #endif | |
3039 | #ifdef SUBTARGET_R3900 | |
3040 | /* 17 = Debug */ | |
3041 | case 17: | |
3042 | if (code == 0x00) | |
3043 | GPR[rt] = DEPC; | |
3044 | else | |
3045 | DEPC = GPR[rt]; | |
3046 | break; | |
3047 | #else | |
3048 | /* 17 = LLAddr R4000 VR4100 VR4300 */ | |
3049 | #endif | |
3050 | /* 18 = WatchLo R4000 VR4100 VR4300 */ | |
3051 | /* 19 = WatchHi R4000 VR4100 VR4300 */ | |
3052 | /* 20 = XContext R4000 VR4100 VR4300 */ | |
3053 | /* 26 = PErr or ECC R4000 VR4100 VR4300 */ | |
3054 | /* 27 = CacheErr R4000 VR4100 */ | |
3055 | /* 28 = TagLo R4000 VR4100 VR4300 */ | |
3056 | /* 29 = TagHi R4000 VR4100 VR4300 */ | |
3057 | /* 30 = ErrorEPC R4000 VR4100 VR4300 */ | |
3058 | GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */ | |
3059 | /* CPR[0,rd] = GPR[rt]; */ | |
3060 | default: | |
3061 | if (code == 0x00) | |
3062 | sim_io_printf(sd,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt,rd); | |
3063 | else | |
3064 | sim_io_printf(sd,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt,rd); | |
3065 | } | |
3066 | } | |
3067 | else if (code == 0x10 && (instruction & 0x3f) == 0x18) | |
3068 | { | |
3069 | /* ERET */ | |
3070 | if (SR & status_ERL) | |
3071 | { | |
3072 | /* Oops, not yet available */ | |
3073 | sim_io_printf(sd,"Warning: ERET when SR[ERL] set not handled yet"); | |
3074 | PC = EPC; | |
3075 | SR &= ~status_ERL; | |
3076 | } | |
3077 | else | |
3078 | { | |
3079 | PC = EPC; | |
3080 | SR &= ~status_EXL; | |
3081 | } | |
3082 | } | |
3083 | else if (code == 0x10 && (instruction & 0x3f) == 0x10) | |
3084 | { | |
3085 | /* RFE */ | |
3086 | } | |
3087 | else if (code == 0x10 && (instruction & 0x3f) == 0x1F) | |
3088 | { | |
3089 | /* DERET */ | |
3090 | Debug &= ~Debug_DM; | |
3091 | DELAYSLOT(); | |
3092 | DSPC = DEPC; | |
3093 | } | |
3094 | else | |
3095 | sim_io_eprintf(sd,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia)); | |
3096 | /* TODO: When executing an ERET or RFE instruction we should | |
3097 | clear LLBIT, to ensure that any out-standing atomic | |
3098 | read/modify/write sequence fails. */ | |
3099 | } | |
3100 | break; | |
3101 | ||
3102 | case 2: /* undefined co-processor */ | |
3103 | sim_io_eprintf(sd,"COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia)); | |
3104 | break; | |
3105 | ||
3106 | case 1: /* should not occur (FPU co-processor) */ | |
3107 | case 3: /* should not occur (FPU co-processor) */ | |
3108 | SignalException(ReservedInstruction,instruction); | |
3109 | break; | |
3110 | } | |
3111 | ||
3112 | return; | |
3113 | } | |
3114 | ||
3115 | /*-- instruction simulation -------------------------------------------------*/ | |
3116 | ||
3117 | /* When the IGEN simulator is being built, the function below is be | |
3118 | replaced by a generated version. However, WITH_IGEN == 2 indicates | |
3119 | that the fubction below should be compiled but under a different | |
3120 | name (to allow backward compatibility) */ | |
3121 | ||
3122 | #if (WITH_IGEN != 1) | |
3123 | #if (WITH_IGEN > 1) | |
3124 | void old_engine_run PARAMS ((SIM_DESC sd, int next_cpu_nr, int siggnal)); | |
3125 | void | |
3126 | old_engine_run (sd, next_cpu_nr, siggnal) | |
3127 | #else | |
3128 | void | |
3129 | sim_engine_run (sd, next_cpu_nr, siggnal) | |
3130 | #endif | |
3131 | SIM_DESC sd; | |
3132 | int next_cpu_nr; /* ignore */ | |
3133 | int siggnal; /* ignore */ | |
3134 | { | |
3135 | #if !defined(FASTSIM) | |
3136 | unsigned int pipeline_count = 1; | |
3137 | #endif | |
3138 | ||
3139 | #ifdef DEBUG | |
3140 | if (STATE_MEMORY (sd) == NULL) { | |
3141 | printf("DBG: simulate() entered with no memory\n"); | |
3142 | exit(1); | |
3143 | } | |
3144 | #endif /* DEBUG */ | |
3145 | ||
3146 | #if 0 /* Disabled to check that everything works OK */ | |
3147 | /* The VR4300 seems to sign-extend the PC on its first | |
3148 | access. However, this may just be because it is currently | |
3149 | configured in 32bit mode. However... */ | |
3150 | PC = SIGNEXTEND(PC,32); | |
3151 | #endif | |
3152 | ||
3153 | /* main controlling loop */ | |
3154 | while (1) { | |
3155 | /* vaddr is slowly being replaced with cia - current instruction | |
3156 | address */ | |
3157 | address_word cia = (uword64)PC; | |
3158 | address_word vaddr = cia; | |
3159 | address_word paddr; | |
3160 | int cca; | |
3161 | unsigned int instruction; /* uword64? what's this used for? FIXME! */ | |
3162 | ||
3163 | #ifdef DEBUG | |
3164 | { | |
3165 | printf("DBG: state = 0x%08X :",state); | |
3166 | if (state & simHALTEX) printf(" simHALTEX"); | |
3167 | if (state & simHALTIN) printf(" simHALTIN"); | |
3168 | printf("\n"); | |
3169 | } | |
3170 | #endif /* DEBUG */ | |
3171 | ||
3172 | DSSTATE = (STATE & simDELAYSLOT); | |
3173 | #ifdef DEBUG | |
3174 | if (dsstate) | |
3175 | sim_io_printf(sd,"DBG: DSPC = 0x%s\n",pr_addr(DSPC)); | |
3176 | #endif /* DEBUG */ | |
3177 | ||
3178 | /* Fetch the next instruction from the simulator memory: */ | |
3179 | if (AddressTranslation(cia,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) { | |
3180 | if ((vaddr & 1) == 0) { | |
3181 | /* Copy the action of the LW instruction */ | |
3182 | unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0); | |
3183 | unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0); | |
3184 | uword64 value; | |
3185 | unsigned int byte; | |
3186 | paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2))); | |
3187 | LoadMemory(&value,NULL,cca,AccessLength_WORD,paddr,vaddr,isINSTRUCTION,isREAL); | |
3188 | byte = ((vaddr & LOADDRMASK) ^ (bigend << 2)); | |
3189 | instruction = ((value >> (8 * byte)) & 0xFFFFFFFF); | |
3190 | } else { | |
3191 | /* Copy the action of the LH instruction */ | |
3192 | unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 1) : 0); | |
3193 | unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 1) : 0); | |
3194 | uword64 value; | |
3195 | unsigned int byte; | |
3196 | paddr = (((paddr & ~ (uword64) 1) & ~LOADDRMASK) | |
3197 | | (((paddr & ~ (uword64) 1) & LOADDRMASK) ^ (reverse << 1))); | |
3198 | LoadMemory(&value,NULL,cca, AccessLength_HALFWORD, | |
3199 | paddr & ~ (uword64) 1, | |
3200 | vaddr, isINSTRUCTION, isREAL); | |
3201 | byte = (((vaddr &~ (uword64) 1) & LOADDRMASK) ^ (bigend << 1)); | |
3202 | instruction = ((value >> (8 * byte)) & 0xFFFF); | |
3203 | } | |
3204 | } else { | |
3205 | fprintf(stderr,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC)); | |
3206 | exit(1); | |
3207 | } | |
3208 | ||
3209 | #ifdef DEBUG | |
3210 | sim_io_printf(sd,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction,pr_addr(PC)); | |
3211 | #endif /* DEBUG */ | |
3212 | ||
3213 | /* This is required by exception processing, to ensure that we can | |
3214 | cope with exceptions in the delay slots of branches that may | |
3215 | already have changed the PC. */ | |
3216 | if ((vaddr & 1) == 0) | |
3217 | PC += 4; /* increment ready for the next fetch */ | |
3218 | else | |
3219 | PC += 2; | |
3220 | /* NOTE: If we perform a delay slot change to the PC, this | |
3221 | increment is not requuired. However, it would make the | |
3222 | simulator more complicated to try and avoid this small hit. */ | |
3223 | ||
3224 | /* Currently this code provides a simple model. For more | |
3225 | complicated models we could perform exception status checks at | |
3226 | this point, and set the simSTOP state as required. This could | |
3227 | also include processing any hardware interrupts raised by any | |
3228 | I/O model attached to the simulator context. | |
3229 | ||
3230 | Support for "asynchronous" I/O events within the simulated world | |
3231 | could be providing by managing a counter, and calling a I/O | |
3232 | specific handler when a particular threshold is reached. On most | |
3233 | architectures a decrement and check for zero operation is | |
3234 | usually quicker than an increment and compare. However, the | |
3235 | process of managing a known value decrement to zero, is higher | |
3236 | than the cost of using an explicit value UINT_MAX into the | |
3237 | future. Which system is used will depend on how complicated the | |
3238 | I/O model is, and how much it is likely to affect the simulator | |
3239 | bandwidth. | |
3240 | ||
3241 | If events need to be scheduled further in the future than | |
3242 | UINT_MAX event ticks, then the I/O model should just provide its | |
3243 | own counter, triggered from the event system. */ | |
3244 | ||
3245 | /* MIPS pipeline ticks. To allow for future support where the | |
3246 | pipeline hit of individual instructions is known, this control | |
3247 | loop manages a "pipeline_count" variable. It is initialised to | |
3248 | 1 (one), and will only be changed by the simulator engine when | |
3249 | executing an instruction. If the engine does not have access to | |
3250 | pipeline cycle count information then all instructions will be | |
3251 | treated as using a single cycle. NOTE: A standard system is not | |
3252 | provided by the default simulator because different MIPS | |
3253 | architectures have different cycle counts for the same | |
3254 | instructions. | |
3255 | ||
3256 | [NOTE: pipeline_count has been replaced the event queue] */ | |
3257 | ||
3258 | /* shuffle the floating point status pipeline state */ | |
3259 | ENGINE_ISSUE_PREFIX_HOOK(); | |
3260 | ||
3261 | /* NOTE: For multi-context simulation environments the "instruction" | |
3262 | variable should be local to this routine. */ | |
3263 | ||
3264 | /* Shorthand accesses for engine. Note: If we wanted to use global | |
3265 | variables (and a single-threaded simulator engine), then we can | |
3266 | create the actual variables with these names. */ | |
3267 | ||
3268 | if (!(STATE & simSKIPNEXT)) { | |
3269 | /* Include the simulator engine */ | |
3270 | #include "oengine.c" | |
3271 | #if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT) | |
3272 | #error "Mismatch between run-time simulator code and simulation engine" | |
3273 | #endif | |
3274 | #if (WITH_TARGET_WORD_BITSIZE != GPRLEN) | |
3275 | #error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN" | |
3276 | #endif | |
3277 | #if ((WITH_FLOATING_POINT == HARD_FLOATING_POINT) != defined (HASFPU)) | |
3278 | #error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU" | |
3279 | #endif | |
3280 | ||
3281 | #if defined(WARN_LOHI) | |
3282 | /* Decrement the HI/LO validity ticks */ | |
3283 | if (HIACCESS > 0) | |
3284 | HIACCESS--; | |
3285 | if (LOACCESS > 0) | |
3286 | LOACCESS--; | |
3287 | /* start-sanitize-r5900 */ | |
3288 | if (HI1ACCESS > 0) | |
3289 | HI1ACCESS--; | |
3290 | if (LO1ACCESS > 0) | |
3291 | LO1ACCESS--; | |
3292 | /* end-sanitize-r5900 */ | |
3293 | #endif /* WARN_LOHI */ | |
3294 | ||
3295 | /* For certain MIPS architectures, GPR[0] is hardwired to zero. We | |
3296 | should check for it being changed. It is better doing it here, | |
3297 | than within the simulator, since it will help keep the simulator | |
3298 | small. */ | |
3299 | if (ZERO != 0) { | |
3300 | #if defined(WARN_ZERO) | |
3301 | sim_io_eprintf(sd,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO),pr_addr(cia)); | |
3302 | #endif /* WARN_ZERO */ | |
3303 | ZERO = 0; /* reset back to zero before next instruction */ | |
3304 | } | |
3305 | } else /* simSKIPNEXT check */ | |
3306 | STATE &= ~simSKIPNEXT; | |
3307 | ||
3308 | /* If the delay slot was active before the instruction is | |
3309 | executed, then update the PC to its new value: */ | |
3310 | if (DSSTATE) { | |
3311 | #ifdef DEBUG | |
3312 | printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC)); | |
3313 | #endif /* DEBUG */ | |
3314 | PC = DSPC; | |
3315 | CANCELDELAYSLOT(); | |
3316 | } | |
3317 | ||
3318 | if (MIPSISA < 4) { /* The following is only required on pre MIPS IV processors: */ | |
3319 | /* Deal with pending register updates: */ | |
3320 | #ifdef DEBUG | |
3321 | printf("DBG: EMPTY BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in,pending_out,pending_total); | |
3322 | #endif /* DEBUG */ | |
3323 | if (PENDING_OUT != PENDING_IN) { | |
3324 | int loop; | |
3325 | int index = PENDING_OUT; | |
3326 | int total = PENDING_TOTAL; | |
3327 | if (PENDING_TOTAL == 0) { | |
3328 | fprintf(stderr,"FATAL: Mis-match on pending update pointers\n"); | |
3329 | exit(1); | |
3330 | } | |
3331 | for (loop = 0; (loop < total); loop++) { | |
3332 | #ifdef DEBUG | |
3333 | printf("DBG: BEFORE index = %d, loop = %d\n",index,loop); | |
3334 | #endif /* DEBUG */ | |
3335 | if (PENDING_SLOT_REG[index] != (LAST_EMBED_REGNUM + 1)) { | |
3336 | #ifdef DEBUG | |
3337 | printf("pending_slot_count[%d] = %d\n",index,PENDING_SLOT_COUNT[index]); | |
3338 | #endif /* DEBUG */ | |
3339 | if (--(PENDING_SLOT_COUNT[index]) == 0) { | |
3340 | #ifdef DEBUG | |
3341 | printf("pending_slot_reg[%d] = %d\n",index,PENDING_SLOT_REG[index]); | |
3342 | printf("pending_slot_value[%d] = 0x%s\n",index,pr_addr(PENDING_SLOT_VALUE[index])); | |
3343 | #endif /* DEBUG */ | |
3344 | if (PENDING_SLOT_REG[index] == COCIDX) { | |
3345 | #if defined(HASFPU) | |
3346 | SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0)); | |
3347 | #else | |
3348 | ; | |
3349 | #endif | |
3350 | } else { | |
3351 | REGISTERS[PENDING_SLOT_REG[index]] = PENDING_SLOT_VALUE[index]; | |
3352 | #if defined(HASFPU) | |
3353 | /* The only time we have PENDING updates to FPU | |
3354 | registers, is when performing binary transfers. This | |
3355 | means we should update the register type field. */ | |
3356 | if ((PENDING_SLOT_REG[index] >= FGRIDX) && (PENDING_SLOT_REG[index] < (FGRIDX + 32))) | |
3357 | FPR_STATE[PENDING_SLOT_REG[index] - FGRIDX] = fmt_uninterpreted; | |
3358 | #endif /* HASFPU */ | |
3359 | } | |
3360 | #ifdef DEBUG | |
3361 | printf("registers[%d] = 0x%s\n",PENDING_SLOT_REG[index],pr_addr(REGISTERS[PENDING_SLOT_REG[index]])); | |
3362 | #endif /* DEBUG */ | |
3363 | PENDING_SLOT_REG[index] = (LAST_EMBED_REGNUM + 1); | |
3364 | PENDING_OUT++; | |
3365 | if (PENDING_OUT == PSLOTS) | |
3366 | PENDING_OUT = 0; | |
3367 | PENDING_TOTAL--; | |
3368 | } | |
3369 | } | |
3370 | #ifdef DEBUG | |
3371 | printf("DBG: AFTER index = %d, loop = %d\n",index,loop); | |
3372 | #endif /* DEBUG */ | |
3373 | index++; | |
3374 | if (index == PSLOTS) | |
3375 | index = 0; | |
3376 | } | |
3377 | } | |
3378 | #ifdef DEBUG | |
3379 | printf("DBG: EMPTY AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL); | |
3380 | #endif /* DEBUG */ | |
3381 | } | |
3382 | ||
3383 | #if !defined(FASTSIM) | |
3384 | if (sim_events_tickn (sd, pipeline_count)) | |
3385 | { | |
3386 | /* cpu->cia = cia; */ | |
3387 | sim_events_process (sd); | |
3388 | } | |
3389 | #else | |
3390 | if (sim_events_tick (sd)) | |
3391 | { | |
3392 | /* cpu->cia = cia; */ | |
3393 | sim_events_process (sd); | |
3394 | } | |
3395 | #endif /* FASTSIM */ | |
3396 | } | |
3397 | } | |
3398 | #endif | |
3399 | ||
3400 | ||
3401 | /* This code copied from gdb's utils.c. Would like to share this code, | |
3402 | but don't know of a common place where both could get to it. */ | |
3403 | ||
3404 | /* Temporary storage using circular buffer */ | |
3405 | #define NUMCELLS 16 | |
3406 | #define CELLSIZE 32 | |
3407 | static char* | |
3408 | get_cell() | |
3409 | { | |
3410 | static char buf[NUMCELLS][CELLSIZE]; | |
3411 | static int cell=0; | |
3412 | if (++cell>=NUMCELLS) cell=0; | |
3413 | return buf[cell]; | |
3414 | } | |
3415 | ||
3416 | /* Print routines to handle variable size regs, etc */ | |
3417 | ||
3418 | /* Eliminate warning from compiler on 32-bit systems */ | |
3419 | static int thirty_two = 32; | |
3420 | ||
3421 | char* | |
3422 | pr_addr(addr) | |
3423 | SIM_ADDR addr; | |
3424 | { | |
3425 | char *paddr_str=get_cell(); | |
3426 | switch (sizeof(addr)) | |
3427 | { | |
3428 | case 8: | |
3429 | sprintf(paddr_str,"%08lx%08lx", | |
3430 | (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff)); | |
3431 | break; | |
3432 | case 4: | |
3433 | sprintf(paddr_str,"%08lx",(unsigned long)addr); | |
3434 | break; | |
3435 | case 2: | |
3436 | sprintf(paddr_str,"%04x",(unsigned short)(addr&0xffff)); | |
3437 | break; | |
3438 | default: | |
3439 | sprintf(paddr_str,"%x",addr); | |
3440 | } | |
3441 | return paddr_str; | |
3442 | } | |
3443 | ||
3444 | char* | |
3445 | pr_uword64(addr) | |
3446 | uword64 addr; | |
3447 | { | |
3448 | char *paddr_str=get_cell(); | |
3449 | sprintf(paddr_str,"%08lx%08lx", | |
3450 | (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff)); | |
3451 | return paddr_str; | |
3452 | } | |
3453 | ||
3454 | ||
3455 | /*---------------------------------------------------------------------------*/ | |
3456 | /*> EOF interp.c <*/ |