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c906108c SS |
1 | #ifndef SIM_MAIN_H |
2 | #define SIM_MAIN_H | |
3 | ||
4 | /* General config options */ | |
5 | ||
6 | #define WITH_CORE | |
7 | #define WITH_MODULO_MEMORY 1 | |
8 | #define WITH_WATCHPOINTS 1 | |
9 | ||
10 | ||
11 | /* The v850 has 32bit words, numbered 31 (MSB) to 0 (LSB) */ | |
12 | ||
13 | #define WITH_TARGET_WORD_MSB 31 | |
14 | ||
a3976a7c | 15 | #include "config.h" |
c906108c SS |
16 | #include "sim-basics.h" |
17 | #include "sim-signal.h" | |
2aaed979 | 18 | #include "sim-fpu.h" |
c906108c SS |
19 | |
20 | typedef address_word sim_cia; | |
21 | ||
14c9ad2e MF |
22 | typedef struct _sim_cpu SIM_CPU; |
23 | ||
c906108c SS |
24 | #include "sim-base.h" |
25 | ||
26 | #include "simops.h" | |
27 | #include "bfd.h" | |
28 | ||
29 | ||
30 | typedef signed8 int8; | |
31 | typedef unsigned8 uint8; | |
32 | typedef signed16 int16; | |
33 | typedef unsigned16 uint16; | |
34 | typedef signed32 int32; | |
35 | typedef unsigned32 uint32; | |
36 | typedef unsigned32 reg_t; | |
a3976a7c | 37 | typedef unsigned64 reg64_t; |
c906108c SS |
38 | |
39 | ||
40 | /* The current state of the processor; registers, memory, etc. */ | |
41 | ||
42 | typedef struct _v850_regs { | |
43 | reg_t regs[32]; /* general-purpose registers */ | |
44 | reg_t sregs[32]; /* system registers, including psw */ | |
45 | reg_t pc; | |
2aaed979 KB |
46 | int dummy_mem; /* where invalid accesses go */ |
47 | reg_t mpu0_sregs[28]; /* mpu0 system registers */ | |
48 | reg_t mpu1_sregs[28]; /* mpu1 system registers */ | |
49 | reg_t fpu_sregs[28]; /* fpu system registers */ | |
a3976a7c NC |
50 | reg_t selID_sregs[7][32]; /* system registers, selID 1 thru selID 7 */ |
51 | reg64_t vregs[32]; /* vector registers. */ | |
c906108c SS |
52 | } v850_regs; |
53 | ||
54 | struct _sim_cpu | |
55 | { | |
56 | /* ... simulator specific members ... */ | |
57 | v850_regs reg; | |
58 | reg_t psw_mask; /* only allow non-reserved bits to be set */ | |
59 | sim_event *pending_nmi; | |
60 | /* ... base type ... */ | |
61 | sim_cpu_base base; | |
62 | }; | |
63 | ||
c906108c | 64 | struct sim_state { |
14c9ad2e | 65 | sim_cpu *cpu[MAX_NR_PROCESSORS]; |
c906108c SS |
66 | #if 0 |
67 | SIM_ADDR rom_size; | |
68 | SIM_ADDR low_end; | |
69 | SIM_ADDR high_start; | |
70 | SIM_ADDR high_base; | |
71 | void *mem; | |
72 | #endif | |
73 | sim_state_base base; | |
74 | }; | |
75 | ||
76 | /* For compatibility, until all functions converted to passing | |
77 | SIM_DESC as an argument */ | |
78 | extern SIM_DESC simulator; | |
79 | ||
80 | ||
81 | #define V850_ROM_SIZE 0x8000 | |
82 | #define V850_LOW_END 0x200000 | |
83 | #define V850_HIGH_START 0xffe000 | |
84 | ||
85 | ||
86 | /* Because we are still using the old semantic table, provide compat | |
87 | macro's that store the instruction where the old simops expects | |
88 | it. */ | |
89 | ||
90 | extern uint32 OP[4]; | |
91 | #if 0 | |
92 | OP[0] = inst & 0x1f; /* RRRRR -> reg1 */ | |
93 | OP[1] = (inst >> 11) & 0x1f; /* rrrrr -> reg2 */ | |
94 | OP[2] = (inst >> 16) & 0xffff; /* wwwww -> reg3 OR imm16 */ | |
95 | OP[3] = inst; | |
96 | #endif | |
97 | ||
98 | #define SAVE_1 \ | |
99 | PC = cia; \ | |
100 | OP[0] = instruction_0 & 0x1f; \ | |
101 | OP[1] = (instruction_0 >> 11) & 0x1f; \ | |
102 | OP[2] = 0; \ | |
103 | OP[3] = instruction_0 | |
104 | ||
105 | #define COMPAT_1(CALL) \ | |
106 | SAVE_1; \ | |
107 | PC += (CALL); \ | |
108 | nia = PC | |
109 | ||
110 | #define SAVE_2 \ | |
111 | PC = cia; \ | |
112 | OP[0] = instruction_0 & 0x1f; \ | |
113 | OP[1] = (instruction_0 >> 11) & 0x1f; \ | |
114 | OP[2] = instruction_1; \ | |
115 | OP[3] = (instruction_1 << 16) | instruction_0 | |
116 | ||
117 | #define COMPAT_2(CALL) \ | |
118 | SAVE_2; \ | |
119 | PC += (CALL); \ | |
120 | nia = PC | |
121 | ||
122 | ||
123 | /* new */ | |
124 | #define GR ((CPU)->reg.regs) | |
125 | #define SR ((CPU)->reg.sregs) | |
a3976a7c | 126 | #define VR ((CPU)->reg.vregs) |
2aaed979 KB |
127 | #define MPU0_SR ((STATE_CPU (sd, 0))->reg.mpu0_sregs) |
128 | #define MPU1_SR ((STATE_CPU (sd, 0))->reg.mpu1_sregs) | |
129 | #define FPU_SR ((STATE_CPU (sd, 0))->reg.fpu_sregs) | |
c906108c SS |
130 | |
131 | /* old */ | |
132 | #define State (STATE_CPU (simulator, 0)->reg) | |
133 | #define PC (State.pc) | |
2aaed979 KB |
134 | #define SP_REGNO 3 |
135 | #define SP (State.regs[SP_REGNO]) | |
c906108c SS |
136 | #define EP (State.regs[30]) |
137 | ||
138 | #define EIPC (State.sregs[0]) | |
139 | #define EIPSW (State.sregs[1]) | |
140 | #define FEPC (State.sregs[2]) | |
141 | #define FEPSW (State.sregs[3]) | |
142 | #define ECR (State.sregs[4]) | |
143 | #define PSW (State.sregs[5]) | |
2aaed979 KB |
144 | #define PSW_REGNO 5 |
145 | #define EIIC (State.sregs[13]) | |
146 | #define FEIC (State.sregs[14]) | |
147 | #define DBIC (SR[15]) | |
c906108c SS |
148 | #define CTPC (SR[16]) |
149 | #define CTPSW (SR[17]) | |
150 | #define DBPC (State.sregs[18]) | |
151 | #define DBPSW (State.sregs[19]) | |
152 | #define CTBP (State.sregs[20]) | |
2aaed979 KB |
153 | #define DIR (SR[21]) |
154 | #define EIWR (SR[28]) | |
155 | #define FEWR (SR[29]) | |
156 | #define DBWR (SR[30]) | |
157 | #define BSEL (SR[31]) | |
c906108c SS |
158 | |
159 | #define PSW_US BIT32 (8) | |
160 | #define PSW_NP 0x80 | |
161 | #define PSW_EP 0x40 | |
162 | #define PSW_ID 0x20 | |
163 | #define PSW_SAT 0x10 | |
164 | #define PSW_CY 0x8 | |
165 | #define PSW_OV 0x4 | |
166 | #define PSW_S 0x2 | |
167 | #define PSW_Z 0x1 | |
168 | ||
2aaed979 KB |
169 | #define PSW_NPV (1<<18) |
170 | #define PSW_DMP (1<<17) | |
171 | #define PSW_IMP (1<<16) | |
172 | ||
173 | #define ECR_EICC 0x0000ffff | |
174 | #define ECR_FECC 0xffff0000 | |
175 | ||
176 | /* FPU */ | |
177 | ||
178 | #define FPSR (FPU_SR[6]) | |
179 | #define FPSR_REGNO 6 | |
180 | #define FPEPC (FPU_SR[7]) | |
181 | #define FPST (FPU_SR[8]) | |
182 | #define FPST_REGNO 8 | |
183 | #define FPCC (FPU_SR[9]) | |
184 | #define FPCFG (FPU_SR[10]) | |
185 | #define FPCFG_REGNO 10 | |
186 | ||
187 | #define FPSR_DEM 0x00200000 | |
188 | #define FPSR_SEM 0x00100000 | |
189 | #define FPSR_RM 0x000c0000 | |
190 | #define FPSR_RN 0x00000000 | |
191 | #define FPSR_FS 0x00020000 | |
192 | #define FPSR_PR 0x00010000 | |
193 | ||
194 | #define FPSR_XC 0x0000fc00 | |
195 | #define FPSR_XCE 0x00008000 | |
196 | #define FPSR_XCV 0x00004000 | |
197 | #define FPSR_XCZ 0x00002000 | |
198 | #define FPSR_XCO 0x00001000 | |
199 | #define FPSR_XCU 0x00000800 | |
200 | #define FPSR_XCI 0x00000400 | |
201 | ||
202 | #define FPSR_XE 0x000003e0 | |
203 | #define FPSR_XEV 0x00000200 | |
204 | #define FPSR_XEZ 0x00000100 | |
205 | #define FPSR_XEO 0x00000080 | |
206 | #define FPSR_XEU 0x00000040 | |
207 | #define FPSR_XEI 0x00000020 | |
208 | ||
209 | #define FPSR_XP 0x0000001f | |
210 | #define FPSR_XPV 0x00000010 | |
211 | #define FPSR_XPZ 0x00000008 | |
212 | #define FPSR_XPO 0x00000004 | |
213 | #define FPSR_XPU 0x00000002 | |
214 | #define FPSR_XPI 0x00000001 | |
215 | ||
216 | #define FPST_PR 0x00008000 | |
217 | #define FPST_XCE 0x00002000 | |
218 | #define FPST_XCV 0x00001000 | |
219 | #define FPST_XCZ 0x00000800 | |
220 | #define FPST_XCO 0x00000400 | |
221 | #define FPST_XCU 0x00000200 | |
222 | #define FPST_XCI 0x00000100 | |
223 | ||
224 | #define FPST_XPV 0x00000010 | |
225 | #define FPST_XPZ 0x00000008 | |
226 | #define FPST_XPO 0x00000004 | |
227 | #define FPST_XPU 0x00000002 | |
228 | #define FPST_XPI 0x00000001 | |
229 | ||
230 | #define FPCFG_RM 0x00000180 | |
231 | #define FPCFG_XEV 0x00000010 | |
232 | #define FPCFG_XEZ 0x00000008 | |
233 | #define FPCFG_XEO 0x00000004 | |
234 | #define FPCFG_XEU 0x00000002 | |
235 | #define FPCFG_XEI 0x00000001 | |
236 | ||
237 | #define GET_FPCC()\ | |
238 | ((FPSR >> 24) &0xf) | |
239 | ||
240 | #define CLEAR_FPCC(bbb)\ | |
241 | (FPSR &= ~(1 << (bbb+24))) | |
242 | ||
243 | #define SET_FPCC(bbb)\ | |
244 | (FPSR |= 1 << (bbb+24)) | |
245 | ||
246 | #define TEST_FPCC(bbb)\ | |
247 | ((FPSR & (1 << (bbb+24))) != 0) | |
248 | ||
249 | #define FPSR_GET_ROUND() \ | |
250 | (((FPSR & FPSR_RM) == FPSR_RN) ? sim_fpu_round_near \ | |
251 | : ((FPSR & FPSR_RM) == 0x00040000) ? sim_fpu_round_up \ | |
252 | : ((FPSR & FPSR_RM) == 0x00080000) ? sim_fpu_round_down \ | |
253 | : sim_fpu_round_zero) | |
254 | ||
255 | ||
256 | enum FPU_COMPARE { | |
257 | FPU_CMP_F = 0, | |
258 | FPU_CMP_UN, | |
259 | FPU_CMP_EQ, | |
260 | FPU_CMP_UEQ, | |
261 | FPU_CMP_OLT, | |
262 | FPU_CMP_ULT, | |
263 | FPU_CMP_OLE, | |
264 | FPU_CMP_ULE, | |
265 | FPU_CMP_SF, | |
266 | FPU_CMP_NGLE, | |
267 | FPU_CMP_SEQ, | |
268 | FPU_CMP_NGL, | |
269 | FPU_CMP_LT, | |
270 | FPU_CMP_NGE, | |
271 | FPU_CMP_LE, | |
272 | FPU_CMP_NGT | |
273 | }; | |
274 | ||
275 | ||
276 | /* MPU */ | |
277 | #define MPM (MPU1_SR[0]) | |
278 | #define MPC (MPU1_SR[1]) | |
279 | #define MPC_REGNO 1 | |
280 | #define TID (MPU1_SR[2]) | |
281 | #define PPA (MPU1_SR[3]) | |
282 | #define PPM (MPU1_SR[4]) | |
283 | #define PPC (MPU1_SR[5]) | |
284 | #define DCC (MPU1_SR[6]) | |
285 | #define DCV0 (MPU1_SR[7]) | |
286 | #define DCV1 (MPU1_SR[8]) | |
287 | #define SPAL (MPU1_SR[10]) | |
288 | #define SPAU (MPU1_SR[11]) | |
289 | #define IPA0L (MPU1_SR[12]) | |
290 | #define IPA0U (MPU1_SR[13]) | |
291 | #define IPA1L (MPU1_SR[14]) | |
292 | #define IPA1U (MPU1_SR[15]) | |
293 | #define IPA2L (MPU1_SR[16]) | |
294 | #define IPA2U (MPU1_SR[17]) | |
295 | #define IPA3L (MPU1_SR[18]) | |
296 | #define IPA3U (MPU1_SR[19]) | |
297 | #define DPA0L (MPU1_SR[20]) | |
298 | #define DPA0U (MPU1_SR[21]) | |
299 | #define DPA1L (MPU1_SR[22]) | |
300 | #define DPA1U (MPU1_SR[23]) | |
301 | #define DPA2L (MPU1_SR[24]) | |
302 | #define DPA2U (MPU1_SR[25]) | |
303 | #define DPA3L (MPU1_SR[26]) | |
304 | #define DPA3U (MPU1_SR[27]) | |
305 | ||
306 | #define PPC_PPE 0x1 | |
307 | #define SPAL_SPE 0x1 | |
308 | #define SPAL_SPS 0x10 | |
309 | ||
310 | #define VIP (MPU0_SR[0]) | |
311 | #define VMECR (MPU0_SR[4]) | |
312 | #define VMTID (MPU0_SR[5]) | |
313 | #define VMADR (MPU0_SR[6]) | |
314 | #define VPECR (MPU0_SR[8]) | |
315 | #define VPTID (MPU0_SR[9]) | |
316 | #define VPADR (MPU0_SR[10]) | |
317 | #define VDECR (MPU0_SR[12]) | |
318 | #define VDTID (MPU0_SR[13]) | |
319 | ||
320 | #define MPM_AUE 0x2 | |
321 | #define MPM_MPE 0x1 | |
322 | ||
323 | #define VMECR_VMX 0x2 | |
324 | #define VMECR_VMR 0x4 | |
325 | #define VMECR_VMW 0x8 | |
326 | #define VMECR_VMS 0x10 | |
327 | #define VMECR_VMRMW 0x20 | |
328 | #define VMECR_VMMS 0x40 | |
329 | ||
330 | #define IPA2ADDR(IPA) ((IPA) & 0x1fffff80) | |
331 | #define IPA_IPE 0x1 | |
332 | #define IPA_IPX 0x2 | |
333 | #define IPA_IPR 0x4 | |
334 | #define IPE0 (IPA0L & IPA_IPE) | |
335 | #define IPE1 (IPA1L & IPA_IPE) | |
336 | #define IPE2 (IPA2L & IPA_IPE) | |
337 | #define IPE3 (IPA3L & IPA_IPE) | |
338 | #define IPX0 (IPA0L & IPA_IPX) | |
339 | #define IPX1 (IPA1L & IPA_IPX) | |
340 | #define IPX2 (IPA2L & IPA_IPX) | |
341 | #define IPX3 (IPA3L & IPA_IPX) | |
342 | #define IPR0 (IPA0L & IPA_IPR) | |
343 | #define IPR1 (IPA1L & IPA_IPR) | |
344 | #define IPR2 (IPA2L & IPA_IPR) | |
345 | #define IPR3 (IPA3L & IPA_IPR) | |
346 | ||
347 | #define DPA2ADDR(DPA) ((DPA) & 0x1fffff80) | |
348 | #define DPA_DPE 0x1 | |
349 | #define DPA_DPR 0x4 | |
350 | #define DPA_DPW 0x8 | |
351 | #define DPE0 (DPA0L & DPA_DPE) | |
352 | #define DPE1 (DPA1L & DPA_DPE) | |
353 | #define DPE2 (DPA2L & DPA_DPE) | |
354 | #define DPE3 (DPA3L & DPA_DPE) | |
355 | #define DPR0 (DPA0L & DPA_DPR) | |
356 | #define DPR1 (DPA1L & DPA_DPR) | |
357 | #define DPR2 (DPA2L & DPA_DPR) | |
358 | #define DPR3 (DPA3L & DPA_DPR) | |
359 | #define DPW0 (DPA0L & DPA_DPW) | |
360 | #define DPW1 (DPA1L & DPA_DPW) | |
361 | #define DPW2 (DPA2L & DPA_DPW) | |
362 | #define DPW3 (DPA3L & DPA_DPW) | |
363 | ||
364 | #define DCC_DCE0 0x1 | |
365 | #define DCC_DCE1 0x10000 | |
366 | ||
367 | #define PPA2ADDR(PPA) ((PPA) & 0x1fffff80) | |
368 | #define PPC_PPC 0xfffffffe | |
369 | #define PPC_PPE 0x1 | |
370 | #define PPC_PPM 0x0000fff8 | |
371 | ||
372 | ||
c906108c SS |
373 | #define SEXT3(x) ((((x)&0x7)^(~0x3))+0x4) |
374 | ||
375 | /* sign-extend a 4-bit number */ | |
376 | #define SEXT4(x) ((((x)&0xf)^(~0x7))+0x8) | |
377 | ||
378 | /* sign-extend a 5-bit number */ | |
379 | #define SEXT5(x) ((((x)&0x1f)^(~0xf))+0x10) | |
380 | ||
381 | /* sign-extend a 9-bit number */ | |
382 | #define SEXT9(x) ((((x)&0x1ff)^(~0xff))+0x100) | |
383 | ||
384 | /* sign-extend a 22-bit number */ | |
385 | #define SEXT22(x) ((((x)&0x3fffff)^(~0x1fffff))+0x200000) | |
386 | ||
387 | /* sign extend a 40 bit number */ | |
388 | #define SEXT40(x) ((((x) & UNSIGNED64 (0xffffffffff)) \ | |
389 | ^ (~UNSIGNED64 (0x7fffffffff))) \ | |
390 | + UNSIGNED64 (0x8000000000)) | |
391 | ||
392 | /* sign extend a 44 bit number */ | |
393 | #define SEXT44(x) ((((x) & UNSIGNED64 (0xfffffffffff)) \ | |
394 | ^ (~ UNSIGNED64 (0x7ffffffffff))) \ | |
395 | + UNSIGNED64 (0x80000000000)) | |
396 | ||
397 | /* sign extend a 60 bit number */ | |
398 | #define SEXT60(x) ((((x) & UNSIGNED64 (0xfffffffffffffff)) \ | |
399 | ^ (~ UNSIGNED64 (0x7ffffffffffffff))) \ | |
400 | + UNSIGNED64 (0x800000000000000)) | |
401 | ||
402 | /* No sign extension */ | |
403 | #define NOP(x) (x) | |
404 | ||
405 | #define INC_ADDR(x,i) x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i)) | |
406 | ||
407 | #define RLW(x) load_mem (x, 4) | |
408 | ||
409 | /* Function declarations. */ | |
410 | ||
411 | #define IMEM16(EA) \ | |
412 | sim_core_read_aligned_2 (CPU, PC, exec_map, (EA)) | |
413 | ||
414 | #define IMEM16_IMMED(EA,N) \ | |
415 | sim_core_read_aligned_2 (STATE_CPU (sd, 0), \ | |
416 | PC, exec_map, (EA) + (N) * 2) | |
417 | ||
418 | #define load_mem(ADDR,LEN) \ | |
419 | sim_core_read_unaligned_##LEN (STATE_CPU (simulator, 0), \ | |
420 | PC, read_map, (ADDR)) | |
421 | ||
422 | #define store_mem(ADDR,LEN,DATA) \ | |
423 | sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \ | |
424 | PC, write_map, (ADDR), (DATA)) | |
425 | ||
426 | ||
427 | /* compare cccc field against PSW */ | |
428 | int condition_met (unsigned code); | |
429 | ||
430 | ||
431 | /* Debug/tracing calls */ | |
432 | ||
433 | enum op_types | |
434 | { | |
435 | OP_UNKNOWN, | |
436 | OP_NONE, | |
437 | OP_TRAP, | |
438 | OP_REG, | |
439 | OP_REG_REG, | |
440 | OP_REG_REG_CMP, | |
441 | OP_REG_REG_MOVE, | |
442 | OP_IMM_REG, | |
443 | OP_IMM_REG_CMP, | |
444 | OP_IMM_REG_MOVE, | |
445 | OP_COND_BR, | |
446 | OP_LOAD16, | |
447 | OP_STORE16, | |
448 | OP_LOAD32, | |
449 | OP_STORE32, | |
450 | OP_JUMP, | |
451 | OP_IMM_REG_REG, | |
452 | OP_UIMM_REG_REG, | |
453 | OP_IMM16_REG_REG, | |
454 | OP_UIMM16_REG_REG, | |
455 | OP_BIT, | |
456 | OP_EX1, | |
457 | OP_EX2, | |
458 | OP_LDSR, | |
459 | OP_STSR, | |
460 | OP_BIT_CHANGE, | |
461 | OP_REG_REG_REG, | |
462 | OP_REG_REG3, | |
463 | OP_IMM_REG_REG_REG, | |
464 | OP_PUSHPOP1, | |
465 | OP_PUSHPOP2, | |
466 | OP_PUSHPOP3, | |
467 | }; | |
468 | ||
469 | #ifdef DEBUG | |
bdca5ee4 TT |
470 | void trace_input (char *name, enum op_types type, int size); |
471 | void trace_output (enum op_types result); | |
472 | void trace_result (int has_result, unsigned32 result); | |
c906108c SS |
473 | |
474 | extern int trace_num_values; | |
475 | extern unsigned32 trace_values[]; | |
476 | extern unsigned32 trace_pc; | |
477 | extern const char *trace_name; | |
478 | extern int trace_module; | |
479 | ||
480 | #define TRACE_BRANCH0() \ | |
481 | do { \ | |
482 | if (TRACE_BRANCH_P (CPU)) { \ | |
483 | trace_module = TRACE_BRANCH_IDX; \ | |
484 | trace_pc = cia; \ | |
485 | trace_name = itable[MY_INDEX].name; \ | |
486 | trace_num_values = 0; \ | |
487 | trace_result (1, (nia)); \ | |
488 | } \ | |
489 | } while (0) | |
490 | ||
491 | #define TRACE_BRANCH1(IN1) \ | |
492 | do { \ | |
493 | if (TRACE_BRANCH_P (CPU)) { \ | |
494 | trace_module = TRACE_BRANCH_IDX; \ | |
495 | trace_pc = cia; \ | |
496 | trace_name = itable[MY_INDEX].name; \ | |
497 | trace_values[0] = (IN1); \ | |
498 | trace_num_values = 1; \ | |
499 | trace_result (1, (nia)); \ | |
500 | } \ | |
501 | } while (0) | |
502 | ||
503 | #define TRACE_BRANCH2(IN1, IN2) \ | |
504 | do { \ | |
505 | if (TRACE_BRANCH_P (CPU)) { \ | |
506 | trace_module = TRACE_BRANCH_IDX; \ | |
507 | trace_pc = cia; \ | |
508 | trace_name = itable[MY_INDEX].name; \ | |
509 | trace_values[0] = (IN1); \ | |
510 | trace_values[1] = (IN2); \ | |
511 | trace_num_values = 2; \ | |
512 | trace_result (1, (nia)); \ | |
513 | } \ | |
514 | } while (0) | |
515 | ||
516 | #define TRACE_BRANCH3(IN1, IN2, IN3) \ | |
517 | do { \ | |
518 | if (TRACE_BRANCH_P (CPU)) { \ | |
519 | trace_module = TRACE_BRANCH_IDX; \ | |
520 | trace_pc = cia; \ | |
521 | trace_name = itable[MY_INDEX].name; \ | |
522 | trace_values[0] = (IN1); \ | |
523 | trace_values[1] = (IN2); \ | |
524 | trace_values[2] = (IN3); \ | |
525 | trace_num_values = 3; \ | |
526 | trace_result (1, (nia)); \ | |
527 | } \ | |
528 | } while (0) | |
529 | ||
530 | #define TRACE_LD(ADDR,RESULT) \ | |
531 | do { \ | |
532 | if (TRACE_MEMORY_P (CPU)) { \ | |
533 | trace_module = TRACE_MEMORY_IDX; \ | |
534 | trace_pc = cia; \ | |
535 | trace_name = itable[MY_INDEX].name; \ | |
536 | trace_values[0] = (ADDR); \ | |
537 | trace_num_values = 1; \ | |
538 | trace_result (1, (RESULT)); \ | |
539 | } \ | |
540 | } while (0) | |
541 | ||
542 | #define TRACE_LD_NAME(NAME, ADDR,RESULT) \ | |
543 | do { \ | |
544 | if (TRACE_MEMORY_P (CPU)) { \ | |
545 | trace_module = TRACE_MEMORY_IDX; \ | |
546 | trace_pc = cia; \ | |
547 | trace_name = (NAME); \ | |
548 | trace_values[0] = (ADDR); \ | |
549 | trace_num_values = 1; \ | |
550 | trace_result (1, (RESULT)); \ | |
551 | } \ | |
552 | } while (0) | |
553 | ||
554 | #define TRACE_ST(ADDR,RESULT) \ | |
555 | do { \ | |
556 | if (TRACE_MEMORY_P (CPU)) { \ | |
557 | trace_module = TRACE_MEMORY_IDX; \ | |
558 | trace_pc = cia; \ | |
559 | trace_name = itable[MY_INDEX].name; \ | |
560 | trace_values[0] = (ADDR); \ | |
561 | trace_num_values = 1; \ | |
562 | trace_result (1, (RESULT)); \ | |
563 | } \ | |
564 | } while (0) | |
565 | ||
2aaed979 KB |
566 | #define TRACE_FP_INPUT_FPU1(V0) \ |
567 | do { \ | |
568 | if (TRACE_FPU_P (CPU)) \ | |
569 | { \ | |
570 | unsigned64 f0; \ | |
571 | sim_fpu_to64 (&f0, (V0)); \ | |
572 | trace_input_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \ | |
573 | } \ | |
574 | } while (0) | |
575 | ||
576 | #define TRACE_FP_INPUT_FPU2(V0, V1) \ | |
577 | do { \ | |
578 | if (TRACE_FPU_P (CPU)) \ | |
579 | { \ | |
580 | unsigned64 f0, f1; \ | |
581 | sim_fpu_to64 (&f0, (V0)); \ | |
582 | sim_fpu_to64 (&f1, (V1)); \ | |
583 | trace_input_fp2 (SD, CPU, TRACE_FPU_IDX, f0, f1); \ | |
584 | } \ | |
585 | } while (0) | |
586 | ||
587 | #define TRACE_FP_INPUT_FPU3(V0, V1, V2) \ | |
588 | do { \ | |
589 | if (TRACE_FPU_P (CPU)) \ | |
590 | { \ | |
591 | unsigned64 f0, f1, f2; \ | |
592 | sim_fpu_to64 (&f0, (V0)); \ | |
593 | sim_fpu_to64 (&f1, (V1)); \ | |
594 | sim_fpu_to64 (&f2, (V2)); \ | |
595 | trace_input_fp3 (SD, CPU, TRACE_FPU_IDX, f0, f1, f2); \ | |
596 | } \ | |
597 | } while (0) | |
598 | ||
599 | #define TRACE_FP_INPUT_BOOL1_FPU2(V0, V1, V2) \ | |
600 | do { \ | |
601 | if (TRACE_FPU_P (CPU)) \ | |
602 | { \ | |
603 | int d0 = (V0); \ | |
604 | unsigned64 f1, f2; \ | |
605 | TRACE_DATA *data = CPU_TRACE_DATA (CPU); \ | |
606 | TRACE_IDX (data) = TRACE_FPU_IDX; \ | |
607 | sim_fpu_to64 (&f1, (V1)); \ | |
608 | sim_fpu_to64 (&f2, (V2)); \ | |
609 | save_data (SD, data, trace_fmt_bool, sizeof (d0), &d0); \ | |
610 | save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f1); \ | |
611 | save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f2); \ | |
612 | } \ | |
613 | } while (0) | |
614 | ||
615 | #define TRACE_FP_INPUT_WORD2(V0, V1) \ | |
616 | do { \ | |
617 | if (TRACE_FPU_P (CPU)) \ | |
618 | trace_input_word2 (SD, CPU, TRACE_FPU_IDX, (V0), (V1)); \ | |
619 | } while (0) | |
620 | ||
621 | #define TRACE_FP_RESULT_FPU1(R0) \ | |
622 | do { \ | |
623 | if (TRACE_FPU_P (CPU)) \ | |
624 | { \ | |
625 | unsigned64 f0; \ | |
626 | sim_fpu_to64 (&f0, (R0)); \ | |
627 | trace_result_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \ | |
628 | } \ | |
629 | } while (0) | |
630 | ||
631 | #define TRACE_FP_RESULT_WORD1(R0) TRACE_FP_RESULT_WORD(R0) | |
632 | ||
633 | #define TRACE_FP_RESULT_WORD2(R0, R1) \ | |
634 | do { \ | |
635 | if (TRACE_FPU_P (CPU)) \ | |
636 | trace_result_word2 (SD, CPU, TRACE_FPU_IDX, (R0), (R1)); \ | |
637 | } while (0) | |
638 | ||
c906108c SS |
639 | #else |
640 | #define trace_input(NAME, IN1, IN2) | |
641 | #define trace_output(RESULT) | |
642 | #define trace_result(HAS_RESULT, RESULT) | |
643 | ||
644 | #define TRACE_ALU_INPUT0() | |
645 | #define TRACE_ALU_INPUT1(IN0) | |
646 | #define TRACE_ALU_INPUT2(IN0, IN1) | |
647 | #define TRACE_ALU_INPUT2(IN0, IN1) | |
648 | #define TRACE_ALU_INPUT2(IN0, IN1 INS2) | |
649 | #define TRACE_ALU_RESULT(RESULT) | |
650 | ||
651 | #define TRACE_BRANCH0() | |
652 | #define TRACE_BRANCH1(IN1) | |
653 | #define TRACE_BRANCH2(IN1, IN2) | |
654 | #define TRACE_BRANCH2(IN1, IN2, IN3) | |
655 | ||
656 | #define TRACE_LD(ADDR,RESULT) | |
657 | #define TRACE_ST(ADDR,RESULT) | |
658 | ||
659 | #endif | |
660 | ||
e551c257 NC |
661 | #define GPR_SET(N, VAL) (State.regs[(N)] = (VAL)) |
662 | #define GPR_CLEAR(N) (State.regs[(N)] = 0) | |
c906108c SS |
663 | |
664 | extern void divun ( unsigned int N, | |
665 | unsigned long int als, | |
666 | unsigned long int sfi, | |
667 | unsigned32 /*unsigned long int*/ * quotient_ptr, | |
668 | unsigned32 /*unsigned long int*/ * remainder_ptr, | |
0da2b665 | 669 | int *overflow_ptr |
c906108c SS |
670 | ); |
671 | extern void divn ( unsigned int N, | |
672 | unsigned long int als, | |
673 | unsigned long int sfi, | |
674 | signed32 /*signed long int*/ * quotient_ptr, | |
675 | signed32 /*signed long int*/ * remainder_ptr, | |
0da2b665 | 676 | int *overflow_ptr |
c906108c SS |
677 | ); |
678 | extern int type1_regs[]; | |
679 | extern int type2_regs[]; | |
680 | extern int type3_regs[]; | |
681 | ||
a3976a7c NC |
682 | #define SESR_OV (1 << 0) |
683 | #define SESR_SOV (1 << 1) | |
684 | ||
685 | #define SESR (State.sregs[12]) | |
686 | ||
687 | #define ROUND_Q62_Q31(X) ((((X) + (1 << 30)) >> 31) & 0xffffffff) | |
688 | #define ROUND_Q62_Q15(X) ((((X) + (1 << 30)) >> 47) & 0xffff) | |
689 | #define ROUND_Q31_Q15(X) ((((X) + (1 << 15)) >> 15) & 0xffff) | |
690 | #define ROUND_Q30_Q15(X) ((((X) + (1 << 14)) >> 15) & 0xffff) | |
691 | ||
692 | #define SAT16(X) \ | |
693 | do \ | |
694 | { \ | |
695 | signed64 z = (X); \ | |
696 | if (z > 0x7fff) \ | |
697 | { \ | |
698 | SESR |= SESR_OV | SESR_SOV; \ | |
699 | z = 0x7fff; \ | |
700 | } \ | |
701 | else if (z < -0x8000) \ | |
702 | { \ | |
703 | SESR |= SESR_OV | SESR_SOV; \ | |
704 | z = - 0x8000; \ | |
705 | } \ | |
706 | (X) = z; \ | |
707 | } \ | |
708 | while (0) | |
709 | ||
710 | #define SAT32(X) \ | |
711 | do \ | |
712 | { \ | |
713 | signed64 z = (X); \ | |
714 | if (z > 0x7fffffff) \ | |
715 | { \ | |
716 | SESR |= SESR_OV | SESR_SOV; \ | |
717 | z = 0x7fffffff; \ | |
718 | } \ | |
719 | else if (z < -0x80000000) \ | |
720 | { \ | |
721 | SESR |= SESR_OV | SESR_SOV; \ | |
722 | z = - 0x80000000; \ | |
723 | } \ | |
724 | (X) = z; \ | |
725 | } \ | |
726 | while (0) | |
727 | ||
728 | #define ABS16(X) \ | |
729 | do \ | |
730 | { \ | |
731 | signed64 z = (X) & 0xffff; \ | |
732 | if (z == 0x8000) \ | |
733 | { \ | |
734 | SESR |= SESR_OV | SESR_SOV; \ | |
735 | z = 0x7fff; \ | |
736 | } \ | |
737 | else if (z & 0x8000) \ | |
738 | { \ | |
739 | z = (- z) & 0xffff; \ | |
740 | } \ | |
741 | (X) = z; \ | |
742 | } \ | |
743 | while (0) | |
744 | ||
745 | #define ABS32(X) \ | |
746 | do \ | |
747 | { \ | |
748 | signed64 z = (X) & 0xffffffff; \ | |
749 | if (z == 0x80000000) \ | |
750 | { \ | |
751 | SESR |= SESR_OV | SESR_SOV; \ | |
752 | z = 0x7fffffff; \ | |
753 | } \ | |
754 | else if (z & 0x80000000) \ | |
755 | { \ | |
756 | z = (- z) & 0xffffffff; \ | |
757 | } \ | |
758 | (X) = z; \ | |
759 | } \ | |
760 | while (0) | |
761 | ||
c906108c | 762 | #endif |